Workforce Connect Zebra PTT Pro Version 2 for Ios User Guide (En)

Total Page:16

File Type:pdf, Size:1020Kb

Workforce Connect Zebra PTT Pro Version 2 for Ios User Guide (En) Workforce Connect Zebra PTT Pro Version 2 User Guide for iOS MN-003845-01 EN Rev A ZEBRA and the stylized Zebra head are trademarks of Zebra Technologies Corporation, registered in many jurisdictions worldwide. All other trademarks are the property of their respective owners. © 2020 Zebra Technologies Corporation and/or its affiliates. All rights reserved. Information in this document is subject to change without notice. The software described in this document is furnished under a license agreement or nondisclosure agreement. The software may be used or copied only in accordance with the terms of those agreements. For further information regarding legal and proprietary statements, please go to: SOFTWARE: www.zebra.com/linkoslegal COPYRIGHTS: www.zebra.com/copyright WARRANTY: www.zebra.com/warranty END USER LICENSE AGREEMENT: www.zebra.com/eula Terms of Use Proprietary Statement This manual contains proprietary information of Zebra Technologies Corporation and its subsidiaries (“Zebra Technologies”). It is intended solely for the information and use of parties operating and maintaining the equipment described herein. Such proprietary information may not be used, reproduced, or disclosed to any other parties for any other purpose without the express, written permission of Zebra Technologies. Product Improvements Continuous improvement of products is a policy of Zebra Technologies. All specifications and designs are subject to change without notice. Liability Disclaimer Zebra Technologies takes steps to ensure that its published Engineering specifications and manuals are correct; however, errors do occur. Zebra Technologies reserves the right to correct any such errors and disclaims liability resulting therefrom. Limitation of Liability In no event shall Zebra Technologies or anyone else involved in the creation, production, or delivery of the accompanying product (including hardware and software) be liable for any damages whatsoever (including, without limitation, consequential damages including loss of business profits, business interruption, or loss of business information) arising out of the use of, the results of use of, or inability to use such product, even if Zebra Technologies has been advised of the possibility of such damages. Some jurisdictions do not allow the exclusion or limitation of incidental or consequential damages, so the above limitation or exclusion may not apply to you. Publication Date August 27, 2020 2 Open Source Software Disclosure OpenSSL Copyright (c) 1998-2011 The OpenSSL Project. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: • Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. • All advertising materials mentioning features or use of this software must display the following acknowledgment: "This product includes software developed by the OpenSSL Project for use in the OpenSSL Toolkit. (http://www.openssl.org/)" • The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to endorse or promote products derived from this software without prior written permission. For written permission, please contact openssl- [email protected]. • Products derived from this software may not be called "OpenSSL" nor may "OpenSSL" appear in their names without prior written permission of the OpenSSL Project. • Redistributions of any form whatsoever must retain the following acknowledgment: "This product includes software developed by the OpenSSL Project for use in the OpenSSL Toolkit (http:// www.openssl.org/)" THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. This product includes cryptographic software written by Eric Young ([email protected]). This product includes software written by Tim Hudson ([email protected]). Opus CODEC Copyright (c) 2011 Xiph.Org Foundation, Skype Limited Written by Jean-Marc Valin and Koen Vos • Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4 Contents About This Guide................................................................................................................................ 8 Introduction ...................................................................................................................... 8 Chapter Descriptions........................................................................................................ 8 Notational Conventions.................................................................................................... 8 Related Documents.......................................................................................................... 9 Service Information .......................................................................................................... 9 Getting Started.................................................................................................................................. 10 Data Usage (Cellular Networks)..................................................................................... 10 Group Types and Maximum List Sizes .......................................................................... 10 User Interface.................................................................................................................................... 12 Recent Screen ............................................................................................................... 12 Contacts Screen............................................................................................................ 14 Contact Screen Action Bar............................................................................................ 15 Map Screen.................................................................................................................... 16 Settings Screen.............................................................................................................. 17 Icons............................................................................................................................... 18 Call Management .............................................................................................................................. 19 1:1 PTT Calls ................................................................................................................. 19 Ad Hoc PTT Calls.......................................................................................................... 20 Place an Ad Hoc PTT Call from the Contact List.................................................... 20 Place an Ad Hoc PTT Call from the Map Screen ................................................... 20 Respond to a Call ................................................................................................... 21 Place a Group PTT Call.......................................................................................... 22 1:1 Alert Calls ............................................................................................................... 23 Place an Alert Call from the Contact List................................................................ 23 Place an Alert Call from the Map............................................................................ 24 5 Contents Respond to an Alert Call......................................................................................... 24 Do Not Disturb (DnD) .................................................................................................... 24 Enable or Disable DnD ..........................................................................................
Recommended publications
  • Integrating Preemption Threshold Scheduling and Dynamic Voltage Scaling for Energy Efficient Real-Time Systems
    Integrating Preemption Threshold Scheduling and Dynamic Voltage Scaling for Energy Efficient Real-Time Systems Ravindra Jejurikar1 and Rajesh Gupta2 1 Centre for Embedded Computer Systems, University of California Irvine, Irvine CA 92697, USA jeÞÞ@cec׺ÙciºedÙ 2 Department of Computer Science and Engineering, University of California San Diego, La Jolla, CA 92093, USA gÙÔØa@c׺Ùc×dºedÙ Abstract. Preemption threshold scheduling (PTS) enables designing scalable real-time systems. PTS not only decreases the run-time overhead of the system, but can also be used to decrease the number of threads and the memory require- ments of the system. In this paper, we combine preemption threshold scheduling with dynamic voltage scaling to enable energy efficient scheduling in real-time systems. We consider scheduling with task priorities defined by the Earliest Dead- line First (EDF) policy. We present an algorithm to compute threshold preemption levels for tasks with given static slowdown factors. The proposed algorithm im- proves upon known algorithms in terms of time complexity. Experimental results show that preemption threshold scheduling reduces on an average 90% context switches, even in the presence of task slowdown. Further, we describe a dynamic slack reclamation technique that working in conjunction with PTS that yields on an average 10% additional energy savings. 1 Introduction With increasing mobility and proliferation of embedded systems, low power consump- tion is an important aspect of embedded systems design. Generally speaking, the pro- cessor consumes a significant portion of the total energy, primarily due to increased computational demands. Scaling the processor frequency and voltage based on the per- formance requirements can lead to considerable energy savings.
    [Show full text]
  • What Is an Operating System III 2.1 Compnents II an Operating System
    Page 1 of 6 What is an Operating System III 2.1 Compnents II An operating system (OS) is software that manages computer hardware and software resources and provides common services for computer programs. The operating system is an essential component of the system software in a computer system. Application programs usually require an operating system to function. Memory management Among other things, a multiprogramming operating system kernel must be responsible for managing all system memory which is currently in use by programs. This ensures that a program does not interfere with memory already in use by another program. Since programs time share, each program must have independent access to memory. Cooperative memory management, used by many early operating systems, assumes that all programs make voluntary use of the kernel's memory manager, and do not exceed their allocated memory. This system of memory management is almost never seen any more, since programs often contain bugs which can cause them to exceed their allocated memory. If a program fails, it may cause memory used by one or more other programs to be affected or overwritten. Malicious programs or viruses may purposefully alter another program's memory, or may affect the operation of the operating system itself. With cooperative memory management, it takes only one misbehaved program to crash the system. Memory protection enables the kernel to limit a process' access to the computer's memory. Various methods of memory protection exist, including memory segmentation and paging. All methods require some level of hardware support (such as the 80286 MMU), which doesn't exist in all computers.
    [Show full text]
  • Chapter 1. Origins of Mac OS X
    1 Chapter 1. Origins of Mac OS X "Most ideas come from previous ideas." Alan Curtis Kay The Mac OS X operating system represents a rather successful coming together of paradigms, ideologies, and technologies that have often resisted each other in the past. A good example is the cordial relationship that exists between the command-line and graphical interfaces in Mac OS X. The system is a result of the trials and tribulations of Apple and NeXT, as well as their user and developer communities. Mac OS X exemplifies how a capable system can result from the direct or indirect efforts of corporations, academic and research communities, the Open Source and Free Software movements, and, of course, individuals. Apple has been around since 1976, and many accounts of its history have been told. If the story of Apple as a company is fascinating, so is the technical history of Apple's operating systems. In this chapter,[1] we will trace the history of Mac OS X, discussing several technologies whose confluence eventually led to the modern-day Apple operating system. [1] This book's accompanying web site (www.osxbook.com) provides a more detailed technical history of all of Apple's operating systems. 1 2 2 1 1.1. Apple's Quest for the[2] Operating System [2] Whereas the word "the" is used here to designate prominence and desirability, it is an interesting coincidence that "THE" was the name of a multiprogramming system described by Edsger W. Dijkstra in a 1968 paper. It was March 1988. The Macintosh had been around for four years.
    [Show full text]
  • A Hardware Preemptive Multitasking Mechanism Based on Scan-Path Register Structure for FPGA-Based Reconfigurable Systems
    A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems S. Jovanovic, C. Tanougast and S. Weber Université Henri Poincaré, LIEN, 54506 Vandoeuvre lès Nancy, France [email protected] Abstract all the registers as well as all memories used in the circuit In this paper, we propose a hardware preemptive and to determine the starting point of the restoration multitasking mechanism which uses scan-path register process. On the other hand, the goal of the restoration is to structure and allows identifying the total task’s register restore the task’s context of processing as it was before its size for the FPGA-based reconfigurable systems. The interruption, in order to continue the execution previously main objective of this preemptive mechanism is to stopped. Several techniques allowing the hardware suspend hardware task having low priority, replace it by preemption are proposed in the literature. The pros and high-priority task and restart them at another time cons of mostly used approaches we will disscus in the (and/or from another area of the FPGA in FPGA-based following. designs). The main advantages of the proposed method The readback approach for context saving and storing are that it provides an attractive way for context saving of an outgoing task is one of the approaches which was and restoring of a hardware task without freezing other mostly used for the FPGA-based designs. No additional tasks during pre-emption phases and a small area hardware structures, simple implementation, no extra overhead. We show its feasibility by allowing us to design design efforts and no extra hardware consumption are the a simple computing example as well as the one of the most important advantages of this approach.
    [Show full text]
  • Preemptive Multitasking on Atmel® AVR® Microcontroller
    Advances in Information Science and Computer Engineering Preemptive Multitasking on Atmel® AVR® Microcontroller HABIBUR RAHMAN, Senthil Arumugam Muthukumaraswamy School of Engineering & Physical Sciences Heriot Watt University Dubai Campus Dubai International Academic City UNITED ARAB EMIRATES [email protected]; [email protected] Abstract: - This paper demonstrates the need for multitasking and scenario where multitasking is the only solution and how it can be achieved on an 8-bit AVR® microcontroller. This project explains how to create a simple kernel in a single C file, and execute any number of tasks in a multithreaded fashion. It first explains how the AVR® engine works and how it switches between different tasks using preemptive scheduling algorithm with the flexibility of blocking a task to allowing it more execution time based on their priority level. The code written for this project is basically in C, however the kernel code is mostly assembly functions called by C. The development environment is Atmel Studio®. The code is in such a way that it can be ported over any 8-bit AVR® microcontroller, however, this project demonstrates the results in both simulation and hardware chip on device Atmega8A. Key-Words: - AVR®, Microcontroller, Threading, Preemptive Scheduling, Multitasking. 1 Introduction architecture and will eventually lead to downloading Microcontroller development has been and compiling hundreds of files according to the exponential over the past two decades. Development provided operating system instructions and also in terms of speed, transistor density, multi-core spend time learning how to use it. embedding as well as number of peripheral subsystem on SoC(System on Chip) is common, and But if the user who has basic understanding of C development tools and compilers have been created language and very good understanding on that allows writing code for microcontroller on microcontroller wants to implement multitasking for higher level of abstraction layer an easy task.
    [Show full text]
  • UNIX History Page 1 Tuesday, December 10, 2002 7:02 PM
    UNIX History Page 1 Tuesday, December 10, 2002 7:02 PM CHAPTER 1 UNIX Evolution and Standardization This chapter introduces UNIX from a historical perspective, showing how the various UNIX versions have evolved over the years since the very first implementation in 1969 to the present day. The chapter also traces the history of the different attempts at standardization that have produced widely adopted standards such as POSIX and the Single UNIX Specification. The material presented here is not intended to document all of the UNIX variants, but rather describes the early UNIX implementations along with those companies and bodies that have had a major impact on the direction and evolution of UNIX. A Brief Walk through Time There are numerous events in the computer industry that have occurred since UNIX started life as a small project in Bell Labs in 1969. UNIX history has been largely influenced by Bell Labs’ Research Editions of UNIX, AT&T’s System V UNIX, Berkeley’s Software Distribution (BSD), and Sun Microsystems’ SunOS and Solaris operating systems. The following list shows the major events that have happened throughout the history of UNIX. Later sections describe some of these events in more detail. 1 UNIX History Page 2 Tuesday, December 10, 2002 7:02 PM 2 UNIX Filesystems—Evolution, Design, and Implementation 1969. Development on UNIX starts in AT&T’s Bell Labs. 1971. 1st Edition UNIX is released. 1973. 4th Edition UNIX is released. This is the first version of UNIX that had the kernel written in C. 1974. Ken Thompson and Dennis Ritchie publish their classic paper, “The UNIX Timesharing System” [RITC74].
    [Show full text]
  • Beyond Preemption:The Law and Policy of Intellectual Property
    Beyond Preemption:The Law and Policy of Intellectual Property Licensing Mark A. Lemley1† Table of Contents Introduction . I. The Tension Between Article 2B and Intellectual Property . A. Article 2B’s Expansion of the Scope and Power of Contracts . B. Potential Conflicts with Intellectual Property Law . 1. Patent Law . 2. Copyright Law . 3. Trade Secret Law . 4. Trademark Law . 5. Remedies . C. Conclusions . II. Preemption as a Partial Solution . A. The Nature of Intellectual Property Preemption . 1. The Basic Nature of Preemption . 2. Intellectual Property Preemption . a. Patent Law . b. Copyright Law . c. Applying Preemption to Contract Law . 1 Copyright © 1999 Mark A. Lemley and California Law Review, Inc. † Professor of Law, University of Texas School of Law; Visiting Professor of Law, Boalt Hall School of Law, University of California at Berkeley (Fall 1998); of counsel, Fish & Richardson P.C., Austin, Texas. I would like to thank Stephen Barnett, Julie Cohen, Richard Craswell, Robert Denicola, Rochelle Cooper Dreyfuss, Paul Goldstein, Robert Gomulkiewicz, Rose Hagan, Paul Heald, Dennis Karjala, Eric Lode, David McGowan, Charles McManis, Rob Merges, Maureen O’Rourke, Malla Pollack, Lloyd Weinreb, and participants in a faculty workshop at Stanford Law School and in the Berkeley Center for Law and Technology’s Conference on Article 2B of the Uniform Commercial Code for comments on an earlier draft. I would also like to thank Ryan Garcia and Sherri Shaw for research assistance. 111 CALIFORNIA LAW REVIEW [Vol. 87:111 B. The Limits of Preemption 1. Preemption Lacks Nuance . 2. Intellectual Property Rules Aren’t Always Statutory . 3. Intellectual Property Rules Aren’t Always Federal .
    [Show full text]
  • BIAS: Bluetooth Impersonation Attacks
    BIAS: Bluetooth Impersonation AttackS Daniele Antonioli Nils Ole Tippenhauer Kasper Rasmussen School of Computer and Communication Sciences CISPA Helmholtz Center Department of Computer Science EPFL for Information Security University of Oxford daniele.antonioli@epfl.ch [email protected] [email protected] Abstract—Bluetooth (BR/EDR) is a pervasive technology for subsequent secure connections. Two Bluetooth devices are wireless communication used by billions of devices. The Bluetooth expected to pair once and securely connect multiple times. standard includes a legacy authentication procedure and a secure During secure connection establishment the devices have to authentication procedure, allowing devices to authenticate to each other using a long term key. Those procedures are used authenticate the possession of the long term key that they have during pairing and secure connection establishment to prevent established while pairing. impersonation attacks. In this paper, we show that the Bluetooth In a recent paper, researchers showed that Bluetooth secure specification contains vulnerabilities enabling to perform imper- connection establishment is vulnerable to man-in-the-middle sonation attacks during secure connection establishment. Such attacks, even if the victims are already paired [4]. In that work vulnerabilities include the lack of mandatory mutual authenti- cation, overly permissive role switching, and an authentication however, the attack assumes that there is a legitimate secure procedure downgrade. We describe each vulnerability in detail, connection to break into. The attacker cannot target isolated and we exploit them to design, implement, and evaluate master Bluetooth devices, because the attacker cannot prove possession and slave impersonation attacks on both the legacy authentication of the victims’ long term key during secure connection procedure and the secure authentication procedure.
    [Show full text]
  • Precept 4: Multicore + Preemption
    Precept 4: Multicore + Preemption COS 318: Fall 2017 Project 4 Schedule ● Precept: Monday 11/6, 7:30pm ○ (You are here) ● Design Review: Monday 11/13 ● Due: Sunday, 11/19, 11:55pm Precept Overview ● Adding multicore support ● Preemption ● Producer-Consumer problem ● Project specific topics Multicore Support Supporting “SMP” ● SMP: Symmetric Multiprocessing ○ All CPUs have equivalent access to resources ● Bootup: BSP initializes system + activate APs ● Each CPU has a core and a LAPIC ○ LAPIC: Performs interrupt routing and delivery Stack organization ● Each processor needs its own kernel stack ○ Different from stacks used by process’s kernel threads ○ Location specified by processor’s TSS ● We use “kernel bootstrap stacks” ○ Switch to process kernel stack after performing setup Multiprocessor OS: CPU State ● Must distinguish between global state and per-CPU state ● What state is private to a CPU? Multiprocessor OS: Locking ● We can now have multiple CPUs in the kernel at the same time ○ What if they write to the same kernel memory? ● Strawman approach: Big Kernel Lock ● Our approach: Fine grained locking Preemptive Scheduling Preemption: Clock interrupts ● Current OS: One process can hog CPU ○ Want to preempt processes after a timeout ● On timer interrupt: forcefully switch to another thread ○ Allows interleaving without explicit yields Preemption: Scheduling ● LAPIC can give us timer interrupts ○ Count number of milliseconds thread has run for ○ Yield once runtime > threshold ● Choose another thread to run ○ We use round-robin Preempting Kernel Execution Which part will be affected? ● Temporarily enable interrupts during the executions of sys_produce and sys_consume ● Leave other parts of the kernel unchanged; ● So only enable interrupts during these two functions.
    [Show full text]
  • Evaluating the Case for Regulation of Digital Platforms Giuseppe Colangelo*
    Evaluating the Case for Regulation of Digital Platforms Giuseppe Colangelo* INTRODUCTION: THE CRISIS OF ANTITRUST IN THE DIGITAL ECONOMY Antitrust enforcement and competition policy in the digital economy is high on the agenda of authorities and policymakers. The flood of reports and policy papers recently released reflects the ongoing debate over the capability of current antitrust rules and tools to handle the emergence of large technology platforms (BigTechs) and to scrutinize their practices and business models. The distinctive features of digital markets apparently require a rethinking of the antitrust regime. The presence of strong economies of scale, extreme indirect network effects, remarkable economies of scope due the role of data as a critical input, and conglomerate effects, along with consumers’ behavioural biases and single-homing tendencies, represent significant barriers to entry that make digital markets highly concentrated, prone to tipping, and not easily contestable. Therefore, large incumbent players appear not to be under threat and hard to dislodge. Moreover, digital platforms act as gatekeepers (either by controlling the access of third-party firms to their users or controlling the consumption of products and services by their users) and regulators (due to their rule-setting role within their ecosystem), and frequently play a dual role, being simultaneously operators for the marketplace and sellers of their own products and services in competition with rival sellers. In light of this, mounting criticism against current competition policy allege that lax antitrust enforcement, flawed Judicial rules that reflect unsound economic theories or unsupported empirical claims, and the limited effectiveness of the antitrust toolkit have * Jean Monet Professor of EU Innovation Policy; Associate Professor of Law and Economics, University of Basilicata; TTLF Fellow, Stanford University and University of Vienna; giuseppe.colangelo1975 @gmail.com.
    [Show full text]
  • Multitasking and Real-Time Scheduling
    Multitasking and Real-time Scheduling EE8205: Embedded Computer Systems http://www.ee.ryerson.ca/~courses/ee8205/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview • Processes/Tasks and Concurrency • Scheduling Priorities and Policies • Multitasking • Real-time Scheduling Fixed-Priority and Earliest Deadline First Scheduling • Sporadic and Aperiodic Process Scheduling Chapter 6 of the Text by Wayne Wolf, Chapter 13 of Text by Burns and Wellings © G. Khan Embedded Computer Systems–EE8205: Multitasking & Real-time Scheduling Page: 1 Introduction to Processes All multiprogramming operating systems are built around the concept of processes. Process is also called a task. OS and Processes • OS must interleave the execution of several processes to maximize CPU usage. Keeping reasonable/minimum response time • OS must allocate resources to processes. By avoiding deadlock • OS must also support: IPC: Inter-process communication Creation of processes by other processes © G. Khan Embedded Computer Systems–EE8205: Multitasking & Real-time Scheduling Page: 2 Task/Process Concept Serial Execution of Two Processes Interleaving the Execution of Process 1 and 2 © G. Khan Embedded Computer Systems–EE8205: Multitasking & Real-time Scheduling Page: 3 Processes and Managing Timing Complexity Multiple rates • multimedia • automotive Asynchronous Input • user interfaces • communication systems Engine Control Tasks Engine • spark control Controller • crankshaft sensing • fuel/air mixture • oxygen sensor • Kalman filter © G. Khan Embedded Computer Systems–EE8205: Multitasking & Real-time Scheduling Page: 4 Concurrency • Only one thread runs at a time while others are waiting. • Processor switches from one process to another so quickly that it appears all threads are running simultaneously.
    [Show full text]
  • COS 318: Operating Systems CPU Scheduling
    COS 318: Operating Systems CPU Scheduling Jaswinder Pal Singh Computer Science Department Princeton University (http://www.cs.princeton.edu/courses/cos318/) Today’s Topics u CPU scheduling basics u CPU scheduling algorithms 2 When to Schedule? u Process/thread creation u Process/thread exit u Process thread blocks (on I/O, synchronization) u Interrupt (I/O, clock) 3 Preemptive and Non-Preemptive Scheduling Terminate Exited (call scheduler) Scheduler dispatch Running Block for resource (call scheduler) Yield, Interrupt (call scheduler) Ready Blocked Create Resource free, I/O completion interrupt (move to ready queue) 4 Scheduling Criteria u Assumptions l One process per user and one thread per process l Processes are independent u Goals for batch and interactive systems l Provide fairness l Everyone makes some progress; no one starves l Maximize CPU utilization • Not including idle process l Maximize throughput • Operations/second (min overhead, max resource utilization) l Minimize turnaround time • Batch jobs: time to execute (from submission to completion) l Shorten response time • Interactive jobs: time response (e.g. typing on a keyboard) l Proportionality • Meets user’s expectations Scheduling Criteria u Questions: l What are the goals for PCs versus servers? l Average response time vs. throughput l Average response time vs. fairness Problem Cases u Completely blind about job types l Little overlap between CPU and I/O u Optimization involves favoring jobs of type “A” over “B” l Lots of A’s? B’s starve u Interactive process trapped
    [Show full text]