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High-Precision Reference Design for Buffering a DAC Signal

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High-Precision Reference Design for Buffering a DAC Signal TI Designs High-Precision Reference Design for Buffering a DAC Signal Description Features This reference design features the industry's first zero- • 16-Bit Resolution Digital Input Output Driver crossover and zero-drift amplifier (OPA388) to buffer • 2.7- to 5.5-V Single-Supply Operation the analog output of a digital-to-analog converter (DAC). It demonstrates the importance of the zero- • High Accuracy, INL < 0.5 LSB crossover and zero-drift feature and how they can • Fast SPI, up to 50 MHz minimize the integral nonlinearity (INL) of the system • Industry-Standard Pin Configuration as well as make use of the full-scale range of the DAC (DAC8830). • OPA388 Zero-Crossover, Zero-Drift Amplifier Resources Applications • Field Transmitter TIDA-01402 Design Folder • Data Acquisition OPA388 Product Folder DAC8830 Product Folder • Wireless Infrastructure REF5050 Product Folder • Test and Measurement ASK Our E2E Experts 5.5 V SW + AMP1 SW VIN VOUT ± 5.5 V 5V Supply REF5050 GND C1 C2 GND GND GND VREF VDD 5.5V CS Serial SW Interface SCLK DAC8830 + AMP2 SW Output SDI ± GND GND GND 5.5 V SW + AMP3 SW ± GND Copyright © 2017, Texas Instruments Incorporated An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. TIDUCT8–February 2017 High-Precision Reference Design for Buffering a DAC Signal 1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated System Overview www.ti.com 1 System Overview 1.1 System Description This TI reference design features a precision voltage-output digital-to-analog converter (DAC) that provides excellent linearity and a buffered output with different precision operational amplifiers. This TI Design demonstrates the importance of having an op amp with zero-crossover and zero-drift to minimize the integral nonlinearity (INL) of the system, giving a precision analog output. The design provides a solution of linearization throughout the full scale range of the DAC using a zero-crossover, zero-drift device as the buffered output. This design guide addresses component selection, design theory, and test results of the TIDA-01402 reference design. The following subsections describe the various devices within this reference design system and highlight the characteristics most critical in implementing the corresponding functions. 1.2 Key System Specifications Table 1. Key System Specifications PARAMETER SPECIFICATIONS Resolution 16-bit resolution Output range 0 VREF Linearity error INL < 0.5 LSB DNL 0.5 LSB Gain drift 0.1 ppm/°C Zero-crossover 140-dB CMRR True RRIO 1.3 Block Diagram 5.5 V SW + AMP1 SW VIN VOUT ± 5.5 V 5V Supply REF5050 GND C1 C2 GND GND GND VREF VDD 5.5V CS Serial SW Interface SCLK DAC8830 + AMP2 SW Output SDI ± GND GND GND 5.5 V SW + AMP3 SW ± GND Copyright © 2017, Texas Instruments Incorporated Figure 1. TIDA-01402 Block Diagram 2 High-Precision Reference Design for Buffering a DAC Signal TIDUCT8–February 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated www.ti.com System Overview 1.4 Highlighted Products The TIDA-01402 reference design features the following devices: • OPA388 (Section 1.4.1): Precision, Zero-Drift, Zero-Crossover, True RRIO Operational Amplifier • DAC8830 (Section 1.4.3): 16-Bit, Single-Channel, Ultra-Low-Power, Voltage Output DAC • REF5050 (Section 1.4.4): 3 µVpp/V Noise, 3 ppm/°C Drift Precision Voltage Reference For more information on each of these devices, see their respective product folders at TI.com. 1.4.1 OPA388 The OPAx388 is a family of ultra-low-noise, zero-drift, zero-crossover, rail-to-rail input and output op amp. These devices operate from 1.8 to 5.5 V, excellent AC performance, and only 0.25 µV of offset and 0.005 µV/°C of drift over temperature. The OPAx388 is ideal for driving high-precision, analog-to-digital converters (ADCs) or buffering the output of high-resolution, DACs, as well as a wide range of general purpose applications. Low-noise Charge-pump GM_FF CCOMP CLK CLK +IN OUT ±IN GM1 GM2 GM3 CCOMP Ripple Reduction Technology Copyright © 2016, Texas Instruments Incorporated Figure 2. OPA388 Functional Block Diagram TIDUCT8–February 2017 High-Precision Reference Design for Buffering a DAC Signal 3 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated System Overview www.ti.com 1.4.2 OPA340 The OPA340 device operates on a single supply as low as 2.5 V with an input common-mode voltage range that extends 500 mV below ground and 500 mV above the positive supply. Output voltage swing is to within 1 mV of the supply rails with a 100-kΩ load. These devices offer excellent dynamic response (BW = 5.5 MHz, SR = 6 V/µs), yet the quiescent current is only 750 A. The devices class AB output stage is capable of driving 600-Ω loads series and extends 500 mV beyond the supply. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications. V+ Reference Current V + - IN VIN VBIAS1 Class AB Control VO Circuitry VBIAS2 V- (Ground) Copyright © 2016, Texas Instruments Incorporated Figure 3. OPA340 Functional Block Diagram 1.4.3 DAC8830 The DAC8830 is a single, 16-bit, serial-input, voltage-output DACs operating from a single 3- to 5-V power supply. This device provide excellent linearity (1 LSB INL), low glitch, low noise, and fast settling (1.0 µS to 1/2 LSB of full-scale output) over the specified temperature range of –40°C to 85°C. The output is unbuffered, which reduces the power consumption and the error introduced by the buffer. The DAC8830 output is 0 V to VREF. VDD DAC V VREF OUT CS AGND SCLK Input Serial DAC Latch Interface Register SDI DAC8830 DGND Copyright © 2017, Texas Instruments Incorporated Figure 4. DAC8830 Functional Block Diagram 4 High-Precision Reference Design for Buffering a DAC Signal TIDUCT8–February 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated www.ti.com System Overview 1.4.4 REF5050 The REF5050 is a low-noise, low-drift, very high precision voltage reference. This reference is capable of both sinking and sourcing current, and has excellent line and load regulation. Excellent temperature drift (3 ppm/°C) and high accuracy (0.05%) are achieved using proprietary design techniques. These features, combined with very low noise, make the REF5050 ideal for use in high-precision data acquisition systems. VIN REF50xx R2 R1 αT (10 mA at 25°C) TEMP R4 VOUT αT 10 kW R3 TRIM/NR 1.2 V 1 kW R5 60 kW GND Copyright © 2017, Texas Instruments Incorporated Figure 5. REF5050 Functional Block Diagram 1.5 Design Theory INL is the maximum deviation between the ideal output of a DAC and the actual output level after offset and gain error have been calibrated out of the measurement. This specification is important for measuring error in a DAC. For applications that require extremely high precision, INL is the most valuable specification to consider. This is because there is no way to externally compensate INL like one can offset, gain, and zero-code errors. This means for high-precision applications picking a DAC with high linearity such as the DAC8830 is vital as well as the amplifier chosen for the buffered output. The datasheet of the DAC8830 recommends an operational amplifier with low-offset to eliminate the need of offset trims. With a 16-bit DAC and 5-V reference, the LSB voltage is 76 µV. Input bias current should also be low because the bias current multiplied by the DAC output impedance (approximately 6.25 kΩ) adds to the zero-code error. Rail-to-rail input and output performance are required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code-independent, but in order to minimize gain errors the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3- dB bandwidth of 1 MHz or greater. The amplifier adds another time constant to the system, thus increasing the settling time of the output. A higher 3-dB amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier. The OPA388 and OPA340 both meet these requirements as shown in Table 2; however, the OPA340 will effect the INL because it has a crossover region due the two-input differential pairs needed to achieve rail-to-rail input. The OPA388 is a zero-crossover part that uses a charge-pump topology resulting in no crossover region that would effect the INL. Table 2. Specification Comparison of OPA388 and OPA340 INPUT BIAS CURRENT SLEW RATE UNITY GAIN DEVICE V TYPICAL (µV) RAIL-TO-RAIL OS TYPICAL (pA) (V/µS) BANDWIDTH (MHz) OPA388 ±0.25 ±30 RRIO 5 10 OPA340 ±150 ±0.2 RRIO 6 5.5 TIDUCT8–February 2017 High-Precision Reference Design for Buffering a DAC Signal 5 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated System Overview www.ti.com The internal structure of a traditional rail-to-rail CMOS op amp consists of two differential transistor pairs. In operation, the op amp switches from one pair to the other. This error induced transition region is called the crossover region. Devices with zero-crossover technology eliminate this input offset crossover region. The zero-crossover feature eliminates this input offset transition region that traditional rail-to-rail CMOS op amps have. Eliminating this region provides a highly linear common-mode voltage (VCM) range, assuring maximum linearity and lowest distortion for buffering DAC outputs.
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