National Aeronautics and Space Administration
SpaceCube v3.0 NASA Next-Generation High-Performance Processor for Science Applications
Christopher Wilson, PhD Science Data Processing Branch Software Engineering Division NASA - Goddard Space Flight Center Greenbelt, MD, USA
33rd Annual Conference on Small Satellites SpaceCube
August 2019
www.nasa.gov Outline
1 Introduction to SpaceCube
2 SpaceCube v3.0 Processor Card Overview
3 SpaceCube Comparisons and Features
4 Software and Applications
5 Conclusions
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 2 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Science Data Processing Branch Embedded Processing Group (EPG)
EPG Group Specializes in Embedded Development • Hardware acceleration of algorithms and applications • Intelligence, autonomy, and novel architectures • Flight software integration for development platforms • Advanced architectures and research platforms
Advanced Platforms for Spaceflight • SpaceCube v2.0 and v2.0 Mini • SpaceCube v3.0 and v3.0 Mini • SpaceCube Mini-Z and Mini-Z45
Key Tools and Skills • Flight Software: cFE/cFS, driver integration, flight algorithms • GSE: COSMOS, GMSEC, system testbeds • FPGA Design: Hardware acceleration, fault-tolerant structures • Mission Support: Supporting flight cards, algorithm development • On-board Autonomy and Analysis: deep-learning and machine- learning frameworks, unique architectures
SpaceCube v2.0 SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 3 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Introduction What is SpaceCube? A family of NASA developed space processors that established a hybrid- processing approach combining radiation-hardened and commercial components while emphasizing a novel architecture harmonizing the best capabilities of CPUs, DSPs, and FPGAs
SpaceCube v1.0 High performance reconfigurable science / mission data processor based on Xilinx FPGAs – Hybrid processing - algorithm profiling and partitioning to CPU, DSP, and FPGA logic – Integrated “radiation upset mitigation” techniques – SpaceCube “core software” infrastructure (SCSDK) - Example (cFE/cFS and “SpaceCube Linux” with Xenomai) – Small “critical function” manager/watchdog SpaceCube is – Standard high-speed (multi-Gbps) interfaces Hybrid Processing… SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 4 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Heritage Closing the gap with commercial processors while retaining reliability 57+ Xilinx device-years on orbit SpaceCube is 26 Xilinx FPGAs in space to date (2019) Mission Enabling… 11 systems in space to date (2019)
SpaceCube v1.0 SpaceCube v1.5 SpaceCube v2.0-EM STS-125, MISSE-7, SMART (ORS) STP-H4, STP-H5 STP-H4, STP-H5, STP-H6
SpaceCube v2.0-FLT SpaceCube v2.0 Mini RRM3, STP-H6 (NavCube) STP-H5, UVSC-GEO
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 5 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube on the ISS (Past and Present)
ELC3 STP-H6 ELC2 SpaceCube v2.0 MISSE-7/8 SpaceCube v1.0 SpaceCube v1.0 CSP
Zenith
Nadir ELC1 STP-H4 SpaceCube v1.0 SpaceCube v2.0 STP-H5 ISS Flying Towards You SpaceCube v1.0 SpaceCube Mini SpaceCube v2.06 CSP RRM3 SCIENCE DATA PROCESSING BRANCH • Code 587 • NASASpaceCube GSFC v2.0 Image Credit: DoD Space Test Program 6 SpaceCube Overview - NASA Goddard Space Flight Center SpaceCube Approach
The traditional path of developing radiation- hardened flight processor will not work … 01 they are always one or two generations behind
Use latest radiation-tolerant* processing elements to achieve massive improvement in 02 “MIPS/Watt” (for same size/weight/power)
Accept that radiation-induced upsets may happen occasionally and just deal with them appropriately … 03 any level of reliability can be achieved via smart system design!
*Radiation tolerant – susceptible to radiation-induced upsets (bit SCIENCEflips) but not radiation DATA-induced PROCESSING destructive failures BRANCH (latch-up) • Code 587 • NASA GSFC 7 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube v3.0 Processor Card SpaceCube v3.0 Architecture Overview I/O Memory High- Multi- Performance • Next-Generation SpaceCube Design Gigabit High-Speed High-Speed FPGA-2 Science Volatile Non-Volatile Non-Volatile FPGA DSP Logic, • Prototype demonstration Sept. 2019 Volatile Embedded Soft-core Data Memory Memory Memory • 3U SpaceVPX Form-Factor Memory CPUs • Ultimate goal of using High-Performance Multi-Many Core Ethernet System Monitor Processing Elements CPU / High Spaceflight Computing (HPSC) paired Performance High- with the high-performance FPGA High- Space Computer Radiation Performance Expansion (HPSC) • HPSC will not be ready in time for Performance RS-422/ Hardened FPGA-1 Plug-in FPGA DSP Logic, Multi-Core the prototype design LVDS FPGA Module Embedded Soft- MPSoCCPU • Special FMC+ Expansion Slot core CPUs High-speed A/D or other module
High-Level Specifications
1x Xilinx Kintex UltraScale 1x Xilinx Zynq MPSoC Rad-Hard Monitor FPGA • 2x 2GB DDR3 SDRAM (x72 wide) • Quad-core Arm Cortex-A53 processor (1.3GHz) • Internal SpaceWire router • 1x 16GB NAND Flash • Dual Arm R5 processor (533MHz) between Xilinx FPGAs • External Interfaces • 1x 2GB DDR3 SDRAM (x72 wide) • 1x 16GB NAND Flash • 24x Multi-Gigabit Transceivers • 1x 16GB NAND Flash • Scrubbing/configuration of Kintex FPGA • 82x LVDS pairs or 164x 1.8V single-ended I/O • External Interfaces • Power sequencing • 30x 3.3V single-ended I/O, • I2C/CAN/GigE/SPIO/GPIO/SPW • External Interfaces • 4x RS-422/LVDS/SPW • 12x Multi-Gigabit Transceivers • SpaceWire • Debug Interfaces • Debug Interfaces • 2x 8-channel housekeeping A/D • 2x RS-422 UART / JTAG • 10/100/1000 Ethernet (non-flight) with current monitoring • 2x RS-422 UART / JTAG SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 8 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Goals, Motivations, Challenges
Goals Motivations Challenges Develop reliable, high-speed Highly reliable designs for varying Managing PCB area restrictions hybrid processor using mission environmental scenarios for rad-hard components, SpaceCube design approach balancing cost, routing, and to enable next-generation New capabilities to support sensor signal and power integrity instrument and integration and design tool flows SmallSat capability Mechanical and thermal Need exceptional resources to support complex applications Supporting integrated SCIENCE DATA PROCESSINGsuch BRANCH as artificial • Codeintelligence 587 • NASA softwareGSFC development kit 9 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Card Layout and Design Approach SpaceCube v3.0 Processor Card 220.00 mm
100.00 mm
Reliable Monitor Modularity Reliable supervisors for health monitoring, Industry standard backplane-style interfaces rollback, reconfiguration, and scrubbing for compatibility and expandability Quality Parts Selection Xilinx Devices and System Design Flight-qualified parts where feasible, Emphasis on Xilinx designs for screening, qualification, and risk mitigation reconfigurability and flexibility, everywhere else and focus on fault tolerance SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 10 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Performance - Metrics
10000.00 Int8 Int16 Int32 SPFP DPFP 1000.00 State-of-the-art 100.00 Rad-Hard Processors
10.00
1.00 Note Log Scale GOPS 0.10
0.01
Lovelly, T. M. and George, A D., "Comparative Analysis of Present and Future Space-Grade Processors with Device Devices used in Metrics,"AIAA Journal of Aerospace Information Systems, Vol. 14, No. 3, Mar. 2017, pp. 184-197. doi: 10.2514/ 1.I010472 SpaceCube v3.0
*UltraScaleSCIENCEresults are an DATAestimate based PROCESSINGoff of existing BRANCH • Code 587 • NASA GSFC data, new metrics are in progress but not currently available 11 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Family Comparisons Processor Configuration CoreMark CoreMark® MicroBlaze Xilinx v8.20b Virtex-5, 5- Benchmark by the Embedded 1 Stage Pipeline 16K/16K 238 Microprocessor Benchmark Consortium (Softcore FPGA Fabric) Cache 125MHz (EMBC), measures microcontroller and CPU IBM PowerPC 405 300 MHz 664.7911 performance. CoreMark is small, portable, (SpaceCube v1.0 Virtex-4) simple, free, and displays a single number IBM PowerPC 440 400 MHz, Bus 100 MHz 1155.62 benchmark score. CoreMark has specific run (SpaceCube v2.0 Virtex-5) 125 MHz, Bus 125 MHz 361.13 and reporting rules, to avoid more problematic issues with Dhrystone ARM Cortex-R5 500 MHz 1286.03 (SpaceCube v3.0 Zynq MPSoC)
1 ARM Cortex-A53 1.2 GHz, -O3 16449.621 (SpaceCube v3.0 Zynq MPSoC) 1.2 GHz, -O2 15866.62 14x Increase in Processor Performance SpaceCube v2.0 SpaceCube SpaceCube over Prior Generation Resources v1.0 (FX130) (FX200) v3.0
LUTS (K) 101 164 246 562 FF (K) 101 164 246 1124 3.4x Increase in LUTs 49 + 27 RAM (Mb) 0.79 21 33 6.85x Increase in FFs UltraRAM over FX130-based SCv2.0 DSPs 256 640 768 4488 SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC [1] https://www.eembc.org/coremark/scores.php 12 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Interconnects NAND DDR3 DDR3 Nano 21
MGTs RS422/LVDS/GPIO UART LVDS MGTs FPGA
SPW Nano 85 Backplane SPW SPW FMC+ LVDS/GPIO RHM MGTs
NAND SPW MGTs
MGTs FPGA 2 Nano
MGTs Quad-Core 5 UART/I2C/RGMII/CAN/GPIO Processor
UART/I2C/RGMII/CAN/GPIO UART
SCIENCE DATA PROCESSING BRANCHNAND •DDR3 Code 587 • NASA GSFC 13 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Rad-Hard Monitor Power Sequencing – Monitor powers on first and controls power sequencing of numerous Xilinx FPGA voltage rails Fault-Detection – Monitors each voltage rail on the board and current on critical power rails to aid in fault detection – Allows Xilinx FPGAs to be power-cycled to clear any radiation-induced upsets Independent Operation – Can respond to ground commands even while Xilinx FPGAs are unpowered, and does not require the entire card to be power-cycled SpaceWire Router – Hosts SpaceWire (SPW) router – Allows spacecraft to communicate RHM directly with monitor and both Xilinx devices with same interface Scrubbing – Supports programmable rate (blind scrubbing) or when error is detected (readback) Configuration NAND – Verifies configuration files, can reconstruct configuration file from several corrupted ones, automatic retry, can reconfigure in-flight
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASASpecific radiation GSFCconcerns regarding MPSoC characterization 14 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 cannot be discussed without Xilinx NDA Fault-Tolerant Configurations FPGA Hybrid Adaptive Reconfigurable Fault Tolerance (HARFT) Accelerator – Framework for Adaptive Fault-Tolerance on 0 Hybrid SoCs – Environmentally Responsive / Adaptive – Modes in both CPU and FPGA Subsystems Voter Accelerator1 C. Wilson, S. Sabogal, A. George, and A. Gordon-Ross, “Hybrid, Adaptive, and Reconfigurable Fault Tolerance (HARFT),” IEEE Aerospace Conf., Big Sky, MT, Mar 4 - 11, 2017. Accelerator2 Hypervisor Fault Tolerance – Virtualized Space Applications (ViSA) – Framework leveraging the Xen hypervisor for deploying software-based fault tolerance for flight systems RHM D. Sabogal and A. D. George, “Towards resilient spaceflight systems with virtualization,” IEEE Aerospace Conf., Big Sky, MT, Mar 3 - 10, 2018.
FPGA Duplex with Compare – MPSoC includes dual-core ARM Cortex-R5
FPGA Fault Tolerance Modes – Large FPGA fabric allows for wide number of configurations (e.g. mitigation strategy, softcores) – Adapt FPGA partial reconfiguration partitions with HW accelerators or redundant soft processors
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 15 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Mechanical / Thermal Design Mechanical Design – Installs into plug-in style chassis that accommodates 220mm long card version of SpaceVPXLite standard – Mechanical frame and front panel construction conforms to industry-leading MIL-STD specifications and NASA guidelines including GSFC-STD-7000 for sine vibration, random vibration, quasi-static, shock, thermal vacuum, and thermal cycling – Analysis successfully verifies the module can survive a 14.1 GRMS 3-sigma and 50g static input load Thermal Design – Accommodates multiple thermal design solutions to dissipate the heat – Multi-functional stiffener frame acts as effective passive thermal design solution and primary thermal path from PWB to card retainers – Analysis designed to 50W worst case scenario has shown that use of the thermal design solution enables all assembled components to meet derated junction temperatures
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 16 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 HPSC Integration Quad-Core Processor Overview HPSC – NASA/AFRL Collaboration for radiation Quad-Core hardened multi-core chiplet Processor
Early Prototyping Effort FMC+ – HPSC chiplets will not be ready until 2021 – HPSC designs and prototypes can be conducted with MPSoC
MPSoC Replacement Quad-Core – Next version of SpaceCube v3.0 can pair Processor Xilinx Kintex Ultrascale with HPSC FPGA FPGAHPSC replacing MPSoC in design QuadQuad-Core-Core ProcessorProcessor FMC+ Expansion Add-on – Separate FMC+ HPSC expansion card can be directly added to SpaceCube v3.0 RHM W. A. Powell, “High-Performance Spaceflight Computing (HPSC) Project Overview,” Radiation Hardened Electronics Technology (RHET) Conference, Phoenix, AZ, November 5-8, 2018. SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 17 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Software Development Kit SpaceCube provides software packages for mission development SpaceCube includes support for several popular OS (Linux, RTEMS, FreeRTOS) and allows for end-to-end flatsat testing with ground station software such as Ball Aerospace’s COSMOS and NASA’s IRC. cFS is supported as flight software across all designs.
NASA Open Source Core Flight System
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 18 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Why do we need this capability? Massive Observatories with Multiple Large Instruments – Numerous mission concept studies required multiple SpaceCube processor cards to process and compress enormous volumes of data
Unfortunately for FPGA Resources Everywhere… AI and Machine Learning – Research shows AI/ML constructs have wide applicability for space, however, some complex models incur long execution times or massive resource overheads
S. Sabogal, A. D. George, and G. Crum, “ReCoN: Sematic Segmentation / Image Classification Reconfigurable CNN Acceleration for Space Applications A Framework for Hybrid Semantic Segmentation on Hybrid SoCs,” 12th Space – Computer Vision / Machine Learning Process Computing Conference, July 30 – August 1, 2019. learns to assign label to all pixels of image – Parallel computations are scalable and certain accelerator sizes can only be supported on larger devices
Adaptive Compression – Regenerative compression technique by training neural- network codecs on satellite imagery to improve compression – Lightweight neural network on spacecraft to encode compressed representation can be hardware accelerated SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 19 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 UPCOMING DESIGNS
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 20 SpaceCube Overview - NASA Goddard Space Flight Center SpaceCube v3.0 Mini Specification Overview
• Apply SpaceCube design approach to provide next-generation processor in CubeSat form-factor • Maintain compatibility with SpaceCube v3.0 • High-performance processor of Goddard’s modular CubeSat spacecraft bus MARES
High-Level Specifications 1x Xilinx Kintex UltraScale 91.54 • 1x 2GB DDR3 SDRAM (x72 wide) • 2x 16GB NAND Flash • Radiation-Hardened Monitor • External Interfaces • 12x Multi-Gigabit Transceivers • 48x LVDS pairs or 96x 1.8V single-ended I/O 00
• 30x 3.3V GPIO .
• 2 RS-422/LVDS 88 • SelectMAP Interface • (Front Panel) 24x LVDS pairs or 48x 1.8V single-ended I/O • Debug Interfaces • 2x RS-422 UART (external transceivers) • JTAG SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 21 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Mini-Z Overview
• Re-envisioned and upgraded version of popular CSPv1 design collaboratively developed between NASA GSFC and NSF CHREC • Supports additional IO and form-factor changes to maintain compliance with MARES architecture
High-Level Specifications Storage Dev. Tools • 1GB DDR3 SDRAM • CSP Evaluation Board Processing Capability • 4GB NAND Flash • JTAG programming support • Processing System (PS) • 10/100 Ethernet • Xilinx Zynq-7020 SoC with Dual-Core • MIO and EMIO breakout ARM Cortex-A9 up to 667 MHz IO • MIO • 3 SpaceWire breakouts • 32KB I/D L1 Cache per core • Camera Link breakout • 512KB L2 Cache • 26 single-ended configurable IO into common interfaces such as UART, SPI, CAN, and I2C • USB-UART Board • 256KB OCM • USB to UART Converter • NEON SIMD Single/Double Floating Point • EMIO Unit per core • 24 differential pairs and 12 single-ended IO • Programmable Logic (PL) • Front Panel Physical Dimensions • 85K Logic Cells • 12 differential pairs • ~82g, 620 mil thick • 53,200 LUTS /106,400 FF • <1U CubeSat form factor • 220 DSPs • 1.6-3.6W (FPGA load dependent) • 4.9Mb BRAM SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 22 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Mini-Z45 Specification Overview • Apply SpaceCube design approach to provide next-generation processor in CubeSat form-factor • Maintain compatibility with SpaceCube v3.0 Mini and Mini-Z designs • Upgrade capabilities of Mini-Z (CSPv1) to provide MGTs, more FPGA resources and more memory
High-Level Specifications 91.54
1x Xilinx Zynq 7000 System-on-Chip • 1GB DDR3 SDRAM for ARM Processors • 2GB DDR3 SDRAM for Programmable Logic • 16GB NAND Flash • Radiation-Hardened Watchdog
• External Interfaces 88
• 8x Multi-Gigabit Transceivers . 00 • 31x LVDS pairs or 62x single-ended I/O (voltage selectable) • 28x Single-ended PS MIO • Debug Interfaces • 1x RS-422 UART (external transceivers) • JTAG
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 23 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube “Spin-offs” and Technology Infusion SpaceCube designs have expanded to support variety of missions and projects 9 Mission-Unique SpaceCube I/O Cards in various stages of integration and test
“NavCube” • SSCO Video Distribution Unit • GRSSLi (Code 590) • NavCube (Code 590) • GEDI Digitizer design • Complex PWB design using 1mm pitch CCGAs – TESS, GEDI, Mustang, OSIRIS-REx
• Proposal development GRSSLi Lidar – CycloPPS (Code 550 and Code 600) – DTN (Code 450) – DFB (Code 600) – Various others • NICER/GEDI Ethernet Circuitry • NSF CHREC Space Processor
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 24 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Conclusion SpaceCube is a MISSION ENABLING technology
Delivers exceptional computing power in number of form factors
Cross-cutting technology for Comm/Nav, Earth and Space Science, Planetary, and Exploration missions
Being reconfigurable equals BIG SAVINGS
Past research / missions have proven viability
Designs support AI applications for autonomy and analysis onboard
Successful technology transfer to industry through commercialization
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 25 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Publications
• A. Geist, C. Brewer, M. Davis, N. Franconi, S. Heyward, T. Wise G. Crum, D. Petrick, R. Ripley, C. Wilson, and T. Flatley, “SpaceCube v3.0 NASA Next-Generation High-Performance Processor for Science Applications,” 33rd Annual AIAA/USU Conf. on Small Satellites, SSC19-XII-02, Logan, UT, August 3-8, 2019. • A. Schmidt, M. French, and T. Flatley, “Radiation hardening by software techniques on FPGAs: Flight experiment evaluation and results,” IEEE Aerospace Conference, Big Sky, MT, March 4-11, 2017. • A. Schmidt, G. Weisz, M. French, T. Flatley, C. Villalpando, “SpaceCubeX: A framework for evaluating hybrid multi- core CPU/FPGA/DSP architectures,” IEEE Aerospace Conference, Big Sky, MT, March 4-11, 2017. • D. Petrick, N. Gill, M. Hassouneh R. Stone, L. Winternitz, L. Thomas, M. Davis, P. Sparacino, and T. Flatley, “Adapting the SpaceCube v2.0 data processing system for mission-unique application requirements,” IEEE Aerospace Conference, Big Sky, MT, June 15-18, 2015. • T. Flatley, “Keynote 2 — SpaceCube — A family of reconfigurable hybrid on-board science data processors,” International Conference on ReConFigurable Computing and FPGAs (ReConFig14), Cancun, Mexico, Dec 8-10, 2014. • D. Petrick, A. Geist, D. Albaijes, M. Davis, P. Sparacino, G. Crum, R. Ripley, J. Boblitt, and T. Flatley, “SpaceCube v2.0 space flight hybrid reconfigurable data processing system,” IEEE Aerospace Conference, Big Sky, MT, March 1- 8, 2014. • D. Petrick, D. Espinosa, R. Ripley, G. Crum, A. Geist, and T. Flatley, “Adapting the reconfigurable spacecube processing system for multiple mission applications,” IEEE Aerospace Conference, Big Sky, MT, March 1-8, 2014. • T. Flatley, “Keynote address I: SpaceCube: A family of reconfigurable hybrid on-board science data processors,” NASA/ESA Conference on Adaptive Hardware and Systems (AHS), June 25-28, 2012. • M. Lin, T. Flatley, A. Geist, and D. Petrick, “NASA GSFC Development of the SpaceCube Mini,” 25th Annual AIAA/USU Conf. on Small Satellites, SSC11-X-11, Logan, UT, August 8-11, 2011.
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 26 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SmallSat / CubeSat Publications
• S. Sabogal, P. Gauvin, B. Shea, D. Sabogal, A. Gillette, C. Wilson, A. D. George, G. Crum, and T. Flatley, “Spacecraft Supercomputing Experiment for STP-H6,” 31st Annual AIAA/USU Conf. on Small Satellites, SSC17-XIII-02, Logan, UT, Aug 5-10, 2017. • C. Wilson, J. MacKinnon, P. Gauvin, S. Sabogal, A. D. George, G. Crum, T. Flatley, “µCSP: A Diminutive, Hybrid, Space Processor for Smart Modules and CubeSats,” 30th Annual AIAA/USU Conf. on Small Satellites, SSC16-X-4, Logan, UT, August 6-11, 2016. • C. Wilson, J. Stewart, P. Gauvin, J. MacKinnon, J. Coole, J. Urriste, A. D. George, G. Crum, A. Wilson, and M. Wirthlin, “CSP Hybrid Space Computing for STP-H5/ISEM on ISS,” 29th Annual AIAA/USU Conf. on Small Satellites, SSC15-III-10, Logan, UT, August 8-13, 2015. • B. LaMeres, S. Harkness, M. Handley, P. Moholt, C. Julien, T. Kaiser, D. Klumpar, K. Mashburn, L. Springer, G. Crum, “RadSat – Radiation Tolerant SmallSat Computer System, “29th Annual AIAA/USU Conf. on Small Satellites, SSC15-X-8, Logan, UT, August 8-13, 2015. • S. Altunc, O. Kegege, S. Bundick, H. Shaw, S. Schaire, G. Bussey, G. Crum, J. Burke, S. Palo, D. O’Conor, “X-band CubeSat Communication System Demonstration,” 29th Annual AIAA/USU Conf. on Small Satellites, SSC15-IV-8, Logan, UT, August 8-13, 2015 • D. Rudolph, C. Wilson, J. Stewart, P. Gauvin, G. Crum, A. D. George, M. Wirthlin, H. Lam, “CSP: A Multifaceted Hybrid System for Space Computing,” Proc. of 28th Annual AIAA/USU Conference on Small Satellites, SSC14-III-3, Logan, UT, August 2-7, 2014. • S. Palo, D. O’Connor, E. DeVito, R. Kohnert, G. Crum, S. Altune, “Expanding CubeSat Capabilities with a Low Cost Transceiver,” Proc. of 28th Annual AIAA/USU Conference on Small Satellites, SSC14-IX-1, Logan, UT, August 2-7, 2014.
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 27 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 AI/ML Publications
• [Submitted] J. Goodwill, D. Wilson, S. Sabogal, C. Wilson and A. D. George, “Adaptively Lossy Image Compression for Onboard Processing,” IEEE Aerospace, Big Sky, MT, Mar 7 - Mar 14, 2020.
• S. Sabogal, A. D. George, and G. Crum, “ReCoN: Reconfigurable CNN Acceleration for Space Applications A Framework for Hybrid Semantic Segmentation on Hybrid SoCs,” 12th Space Computing Conference, July 30 – August 1, 2019.
• J. Kelvey, “New Eyes on Wildfires,” EOS, 100, April 30, 2019. https://doi.org/10.1029/2019EO121485
• J. Manning, E. Gretok, B. Ramesh, C. Wilson, A. D. George, J. MacKinnon, G. Crum, “Machine-Learning Space Applications on SmallSat Platforms with TensorFlow,” 32nd Annual AIAA/USU Conference on Small Satellites, SSC18-WKVII-03, Logan, UT, Aug 4-9, 2018.
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 28 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Acronyms Acronym Definition BL-TMR BYU-LANL TMR SEL Single-Event Latchup cFE Core Flight Executive SEM Soft Error Mitigation cFS Core Flight System Spacecraft Supercomputing for Image and Video Center for High-performance Reconfigurable SSIVP Processing CHREC Computing STP-Hx Space Test Program Houston CPU Central Processing Unit TID Total Ionizing Dose CSP CHREC/CubeSat Space Processor TMR Triple Modular Redundancy DSP Digital Signal Processor TRL Technology Readiness Level ELC ExPRESS Logistics Carrier UVSC Ultraviolet Spectro-Coronagraph EM Engineering Model FF Flip-Flop FLT Flight FPGA Field Programmable Gate Array FSM Finite State Machine GMSEC Goddard Mission Services Evolution Center GOPS Giga-Operations Per Second ISA Instruction Set Architecture LEO low-Earth Orbit MGT Multi-Gigabit Transceiver MIPS Million instructions per second NSF National Science Foundation ORS Operationally Responsive Space PCB Printed Circuit Board RE Recuring Engineering SBC Single-Board Computer
SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 29 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Thank you! Questions? [email protected] [email protected] spacecube.nasa.gov
Special thanks to our sponsors: NASA/GSFC IR&D, NASA Satellite Servicing Programs Division (SSPD), NASA Earth Science Technology Office (ESTO), DoD Space Test Program (STP), DoD Operationally Responsive Space (ORS)
SCIENCE DATA PROCESSINGIcons courtesy https://www.flaticon.com/packs/marketing BRANCH • Code 587-management • NASA-2 GSFC 30 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019