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Spacecube V3.0 NASA Next-Generation High-Performance Processor for Science Applications

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Spacecube V3.0 NASA Next-Generation High-Performance Processor for Science Applications National Aeronautics and Space Administration SpaceCube v3.0 NASA Next-Generation High-Performance Processor for Science Applications Christopher Wilson, PhD Science Data Processing Branch Software Engineering Division NASA - Goddard Space Flight Center Greenbelt, MD, USA 33rd Annual Conference on Small Satellites SpaceCube August 2019 www.nasa.gov Outline 1 Introduction to SpaceCube 2 SpaceCube v3.0 Processor Card Overview 3 SpaceCube Comparisons and Features 4 Software and Applications 5 Conclusions SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 2 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Science Data Processing Branch Embedded Processing Group (EPG) EPG Group Specializes in Embedded Development • Hardware acceleration of algorithms and applications • Intelligence, autonomy, and novel architectures • Flight software integration for development platforms • Advanced architectures and research platforms Advanced Platforms for Spaceflight • SpaceCube v2.0 and v2.0 Mini • SpaceCube v3.0 and v3.0 Mini • SpaceCube Mini-Z and Mini-Z45 Key Tools and Skills • Flight Software: cFE/cFS, driver integration, flight algorithms • GSE: COSMOS, GMSEC, system testbeds • FPGA Design: Hardware acceleration, fault-tolerant structures • Mission Support: Supporting flight cards, algorithm development • On-board Autonomy and Analysis: deep-learning and machine- learning frameworks, unique architectures SpaceCube v2.0 SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 3 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Introduction What is SpaceCube? A family of NASA developed space processors that established a hybrid- processing approach combining radiation-hardened and commercial components while emphasizing a novel architecture harmonizing the best capabilities of CPUs, DSPs, and FPGAs SpaceCube v1.0 High performance reconfigurable science / mission data processor based on Xilinx FPGAs – Hybrid processing - algorithm profiling and partitioning to CPU, DSP, and FPGA logic – Integrated “radiation upset mitigation” techniques – SpaceCube “core software” infrastructure (SCSDK) - Example (cFE/cFS and “SpaceCube Linux” with Xenomai) – Small “critical function” manager/watchdog SpaceCube is – Standard high-speed (multi-Gbps) interfaces Hybrid Processing… SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 4 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Heritage Closing the gap with commercial processors while retaining reliability 57+ Xilinx device-years on orbit SpaceCube is 26 Xilinx FPGAs in space to date (2019) Mission Enabling… 11 systems in space to date (2019) SpaceCube v1.0 SpaceCube v1.5 SpaceCube v2.0-EM STS-125, MISSE-7, SMART (ORS) STP-H4, STP-H5 STP-H4, STP-H5, STP-H6 SpaceCube v2.0-FLT SpaceCube v2.0 Mini RRM3, STP-H6 (NavCube) STP-H5, UVSC-GEO SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 5 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube on the ISS (Past and Present) ELC3 STP-H6 ELC2 SpaceCube v2.0 MISSE-7/8 SpaceCube v1.0 SpaceCube v1.0 CSP Zenith Nadir ELC1 STP-H4 SpaceCube v1.0 SpaceCube v2.0 STP-H5 ISS Flying Towards You SpaceCube v1.0 SpaceCube Mini SpaceCube v2.06 CSP RRM3 SCIENCE DATA PROCESSING BRANCH • Code 587 • NASASpaceCube GSFC v2.0 Image Credit: DoD Space Test Program 6 SpaceCube Overview - NASA Goddard Space Flight Center SpaceCube Approach The traditional path of developing radiation- hardened flight processor will not work … 01 they are always one or two generations behind Use latest radiation-tolerant* processing elements to achieve massive improvement in 02 “MIPS/Watt” (for same size/weight/power) Accept that radiation-induced upsets may happen occasionally and just deal with them appropriately … 03 any level of reliability can be achieved via smart system design! *Radiation tolerant – susceptible to radiation-induced upsets (bit SCIENCEflips) but not radiation DATA-induced PROCESSING destructive failures BRANCH (latch-up) • Code 587 • NASA GSFC 7 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube v3.0 Processor Card SpaceCube v3.0 Architecture Overview I/O Memory High- Multi- Performance • Next-Generation SpaceCube Design Gigabit High-Speed High-Speed FPGA-2 Science Volatile Non-Volatile Non-Volatile FPGA DSP Logic, • Prototype demonstration Sept. 2019 Volatile Embedded Soft-core Data Memory Memory Memory • 3U SpaceVPX Form-Factor Memory CPUs • Ultimate goal of using High-Performance Multi-Many Core Ethernet System Monitor Processing Elements CPU / High Spaceflight Computing (HPSC) paired Performance High- with the high-performance FPGA High- Space Computer Radiation Performance Expansion (HPSC) • HPSC will not be ready in time for Performance RS-422/ Hardened FPGA-1 Plug-in FPGA DSP Logic, Multi-Core the prototype design LVDS FPGA Module Embedded Soft- MPSoCCPU • Special FMC+ Expansion Slot core CPUs High-speed A/D or other module High-Level Specifications 1x Xilinx Kintex UltraScale 1x Xilinx Zynq MPSoC Rad-Hard Monitor FPGA • 2x 2GB DDR3 SDRAM (x72 wide) • Quad-core Arm Cortex-A53 processor (1.3GHz) • Internal SpaceWire router • 1x 16GB NAND Flash • Dual Arm R5 processor (533MHz) between Xilinx FPGAs • External Interfaces • 1x 2GB DDR3 SDRAM (x72 wide) • 1x 16GB NAND Flash • 24x Multi-Gigabit Transceivers • 1x 16GB NAND Flash • Scrubbing/configuration of Kintex FPGA • 82x LVDS pairs or 164x 1.8V single-ended I/O • External Interfaces • Power sequencing • 30x 3.3V single-ended I/O, • I2C/CAN/GigE/SPIO/GPIO/SPW • External Interfaces • 4x RS-422/LVDS/SPW • 12x Multi-Gigabit Transceivers • SpaceWire • Debug Interfaces • Debug Interfaces • 2x 8-channel housekeeping A/D • 2x RS-422 UART / JTAG • 10/100/1000 Ethernet (non-flight) with current monitoring • 2x RS-422 UART / JTAG SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 8 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Goals, Motivations, Challenges Goals Motivations Challenges Develop reliable, high-speed Highly reliable designs for varying Managing PCB area restrictions hybrid processor using mission environmental scenarios for rad-hard components, SpaceCube design approach balancing cost, routing, and to enable next-generation New capabilities to support sensor signal and power integrity instrument and integration and design tool flows SmallSat capability Mechanical and thermal Need exceptional resources to support complex applications Supporting integrated SCIENCE DATA PROCESSINGsuch BRANCH as artificial • Codeintelligence 587 • NASA softwareGSFC development kit 9 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Card Layout and Design Approach SpaceCube v3.0 Processor Card 220.00 mm 100.00 mm Reliable Monitor Modularity Reliable supervisors for health monitoring, Industry standard backplane-style interfaces rollback, reconfiguration, and scrubbing for compatibility and expandability Quality Parts Selection Xilinx Devices and System Design Flight-qualified parts where feasible, Emphasis on Xilinx designs for screening, qualification, and risk mitigation reconfigurability and flexibility, everywhere else and focus on fault tolerance SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC 10 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Performance - Metrics 10000.00 Int8 Int16 Int32 SPFP DPFP 1000.00 State-of-the-art 100.00 Rad-Hard Processors 10.00 1.00 Note Log Scale GOPS 0.10 0.01 Lovelly, T. M. and George, A D., "Comparative Analysis of Present and Future Space-Grade Processors with Device Devices used in Metrics,"AIAA Journal of Aerospace Information Systems, Vol. 14, No. 3, Mar. 2017, pp. 184-197. doi: 10.2514/ 1.I010472 SpaceCube v3.0 *UltraScaleSCIENCEresults are an DATAestimate based PROCESSINGoff of existing BRANCH • Code 587 • NASA GSFC data, new metrics are in progress but not currently available 11 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 SpaceCube Family Comparisons Processor Configuration CoreMark CoreMark® MicroBlaze Xilinx v8.20b Virtex-5, 5- Benchmark by the Embedded 1 Stage Pipeline 16K/16K 238 Microprocessor Benchmark Consortium (Softcore FPGA Fabric) Cache 125MHz (EMBC), measures microcontroller and CPU IBM PowerPC 405 300 MHz 664.7911 performance. CoreMark is small, portable, (SpaceCube v1.0 Virtex-4) simple, free, and displays a single number IBM PowerPC 440 400 MHz, Bus 100 MHz 1155.62 benchmark score. CoreMark has specific run (SpaceCube v2.0 Virtex-5) 125 MHz, Bus 125 MHz 361.13 and reporting rules, to avoid more problematic issues with Dhrystone ARM Cortex-R5 500 MHz 1286.03 (SpaceCube v3.0 Zynq MPSoC) 1 ARM Cortex-A53 1.2 GHz, -O3 16449.621 (SpaceCube v3.0 Zynq MPSoC) 1.2 GHz, -O2 15866.62 14x Increase in Processor Performance SpaceCube v2.0 SpaceCube SpaceCube over Prior Generation Resources v1.0 (FX130) (FX200) v3.0 LUTS (K) 101 164 246 562 FF (K) 101 164 246 1124 3.4x Increase in LUTs 49 + 27 RAM (Mb) 0.79 21 33 6.85x Increase in FFs UltraRAM over FX130-based SCv2.0 DSPs 256 640 768 4488 SCIENCE DATA PROCESSING BRANCH • Code 587 • NASA GSFC [1] https://www.eembc.org/coremark/scores.php 12 SpaceCube v3.0 - NASA Goddard Space Flight Center – August 2019 Interconnects NAND DDR3 DDR3 Nano 21 Nano MGTs RS422/LVDS/GPIO UART LVDS MGTs FPGA SPW Nano 85 Nano Backplane SPW SPW FMC+ LVDS/GPIO RHM MGTs NAND SPW MGTs MGTs FPGA Nano 2 MGTs Quad-Core 5 UART/I2C/RGMII/CAN/GPIO Processor UART/I2C/RGMII/CAN/GPIO UART SCIENCE DATA PROCESSING BRANCHNAND •DDR3 Code 587 • NASA GSFC 13 SpaceCube v3.0 - NASA Goddard Space Flight Center
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