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Intel® 64 Architecture X2apic Specification

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Intel® 64 Architecture X2apic Specification Intel® 64 Architecture x2APIC Specification Reference Number: 318148-003 June 2008 i INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT- ED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Developers must not rely on the absence or characteristics of any features or instructions marked “re- served” or “undefined.” Improper use of reserved or undefined features or instructions may cause unpre- dictable behavior or failure in developer's software code when running on an Intel processor. Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from their unauthorized use. The Intel® 64 architecture processors may contain design defects or errors known as errata. Current char- acterized errata are available on request. Hyper-Threading Technology requires a computer system with an Intel® processor supporting Hyper- Threading Technology and an HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information, see http://www.in- tel.com/technology/hyperthread/index.htm; including details on which processors support HT Technology. Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, perfor- mance or other benefits will vary depending on hardware and software configurations. Intel® Virtualization Technology-enabled BIOS and VMM applications are currently in development. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, oper- ating system, device drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel® 64 architecture-enabled BIOS. Performance will vary de- pending on your hardware and software configurations. Consult with your system vendor for more infor- mation. Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo, Intel Core 2 Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, and VTune are trademarks or registered trade- marks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s website at http://www.intel.com Copyright © 2006-2008 Intel Corporation ii CONTENTS CHAPTER 1 INTRODUCTION 1.1 INTRODUCTION. 1-1 1.2 IMPACTED PLATFORM COMPONENTS. 1-1 1.3 GLOSSARY . 1-2 1.4 REFERENCES . 1-3 CHAPTER 2 LOCAL X2APIC ARCHITECTURE 2.1 X2APIC ENHANCEMENTS. 2-1 2.2 DETECTING AND ENABLING X2APIC. 2-2 2.3 X2APIC MODE REGISTER INTERFACE. 2-3 2.3.1 Instructions to Access APIC Registers . 2-3 2.3.2 APIC Register Address Space. 2-3 2.3.3 Reserved Bit Checking . 2-6 2.3.4 Error Handling. 2-7 2.3.5 MSR Access Semantics. 2-7 2.3.5.1 Interrupt Command Register Semantics. 2-7 2.3.5.2 Task Priority Register Semantics . 2-8 2.3.5.3 End Of Interrupt Register Semantics. 2-8 2.3.5.4 Error Status Register Semantics. 2-8 2.3.6 x2APIC Register Availability. 2-9 2.3.7 VM-exit Controls for MSRs and x2APIC Registers. .2-10 2.4 EXTENDED PROCESSOR ADDRESSABILITY . 2-10 2.4.1 Local APIC ID Register . .2-10 2.4.2 Logical Destination Register. .2-11 2.4.3 Interrupt Command Register . .2-13 2.4.4 Deriving Logical x2APIC ID from the Local x2APIC ID. .2-14 2.4.5 SELF IPI register. .2-14 2.5 X2APIC ENHANCEMENTS TO LEGACY XAPIC ARCHITECTURE . 2-15 2.5.1 Directed EOI. .2-15 2.6 INTERACTION WITH PROCESSOR CORE OPERATING MODES . 2-16 2.7 X2APIC STATE TRANSITIONS. 2-17 2.7.1 x2APIC States. .2-17 2.7.1.1 x2APIC After RESET . .2-18 2.7.1.2 x2APIC Transitions From x2APIC Mode . .2-19 2.7.1.3 x2APIC Transitions From Disabled Mode . .2-19 2.7.1.4 State Changes From xAPIC Mode to x2APIC Mode . .2-19 2.8 CPUID EXTENSIONS AND TOPOLOGY ENUMERATION . 2-19 2.8.1 Consistency of APIC IDs and CPUID . .2-22 2.9 SYSTEM TRANSITIONS. 2-23 2.10 LEGACY XAPIC CLARIFICATIONS . 2-23 APPENDIX A ACPI EXTENSIONS FOR X2APIC SUPPORT A.1 ACPI SPECIFICATION CHANGES TO SUPPORT THE X2APIC ARCHITECTURE. A-1 A.2 MULTIPLE APIC DESCRIPTION TABLE AND X2APIC. A-1 A.2.1 x2APIC Structure. A-3 A.2.2 x2APIC NMI Structure. A-4 A.3 SYSTEM RESOURCE AFFINITY TABLE (SRAT). A-6 iii A.4 ACPI NAMESPACE AND X2APIC SUPPORT . A-7 iv This page intentionally left blank v vi TABLES Table 1-1. Description of terminology . 1-2 Table 2-1. x2APIC Operating Mode Configurations . 2-2 Table 2-2. Local APIC Register Address Map Supported by x2APIC . 2-4 Table 2-3. MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation . .2-10 Table 2-4. CPUID Leaf 0BH Information . .2-21 Table A-1. Multiple APIC Description Table Format . A-2 Table A-2. MADT APIC Structure Type Definition . A-3 Table A-3. Processor x2APIC Structure Format . .A-4 Table A-4. x2APIC Structure Flag Field Definition . .A-4 Table A-5. x2APIC NMI Structure Format . A-5 Table A-6. MPS INTI Flag Field Definition . A-5 Table A-7. System Resource Affinity Table Format . A-6 Table A-8. Processor x2APIC Affinity Structure Format . A-7 Table A-9. x2APIC Affinity Structure Flag Field Definition . A-7 vii This page intentionally left blank viii FIGURES Figure 2-1. IA32_APIC_BASE MSR Supporting x2APIC . 2-2 Figure 2-2. Error Status Register (ESR) . ..
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