Chapter 2 Fundamentals of Electromigration
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In Situ STEM Technique for Characterization of Nanoscale Interconnects During Electromigration Testing
University of Nebraska - Lincoln DigitalCommons@University of Nebraska - Lincoln Mechanical & Materials Engineering Faculty Mechanical & Materials Engineering, Publications Department of Spring 1999 In situ STEM Technique for Characterization of Nanoscale Interconnects During Electromigration Testing Ismail Gobulukoglu University of Nebraska-Lincoln Brian W. Robertson University of Nebraska-Lincoln, [email protected] Follow this and additional works at: https://digitalcommons.unl.edu/mechengfacpub Part of the Mechanical Engineering Commons Gobulukoglu, Ismail and Robertson, Brian W., "In situ STEM Technique for Characterization of Nanoscale Interconnects During Electromigration Testing" (1999). Mechanical & Materials Engineering Faculty Publications. 11. https://digitalcommons.unl.edu/mechengfacpub/11 This Article is brought to you for free and open access by the Mechanical & Materials Engineering, Department of at DigitalCommons@University of Nebraska - Lincoln. It has been accepted for inclusion in Mechanical & Materials Engineering Faculty Publications by an authorized administrator of DigitalCommons@University of Nebraska - Lincoln. eo I'. ~ ! r , , IN SITU STEM TECHNIQUE FOR CHARACTERIZATION OF NANOSCALE INTERCONNECTS DURING ELECTROWGRATION TESTING Ismail Gobulukoglu and Brian W. Robertson Department of Mechanical Engineering and the Center for Materials Research and Analysis University of Nebraska, Lincoln. Nebraska 68588-0656 Abstract A technique for obsetviilg microstructure and morphology changes during annealing or electromigration of 100 run-scale and smaller interconnects is presented. The technique is based on dynamic in situ characterization using a UHV field-emission scanning transmission electron microscope (STEM) and can enable full microstructural characterization (images, diffraction patterns and compositions) during electromigration testing. Initial steps in the validation of the approach include in situ electron-beam OMCVD of Al-containing wires and observation of these wires. -
Electromigration Behavior and Reliability of Bamboo Al(Cu) Interconnects for Integrated Circuits by V
Electromigration Behavior and Reliability of Bamboo Al(Cu) Interconnects for Integrated Circuits by V. T. Srikar B.Tech., Banaras Hindu University, India (1994) Submitted to the Department of Materials Science and Engineering in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Materials Science at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY February 1999 @ Massachusetts Institute of Technology 1999. All rights reserved. A uth or ............................................................ Department of Materials Science and Engineering January 8, 1999 C ertified by.............................I Carl V. Thompson Stavros Salapatas Professor of Materials Science and Engineering Thesis Supervisor A ccepted by ....................................................... Linn W. Hobbs MASSACHUSETTS INSTITUTE John F. Elliot Professor of Materials oFHNOLOG j airman, Departmental Committee on Graduate Students IE'1 Electromigration Behavior and Reliability of Bamboo Al(Cu) Interconnects for Integrated Circuits by V. T. Srikar Submitted to the Department of Materials Science and Engineering on January 8, 1999, in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Materials Science Abstract Thin lines of Al(Cu) with bamboo grain structures, capped with Al 3Ti layers and terminating in W-studs, are an increasingly common class of interconnects used in Si integrated circuits. These lines are susceptible to transgranular electromigration- induced failure. Electromigration-induced stress evolution can be modeled using a diffusion-drift equation in one dimension, the solution of which requires knowledge of the transport parameters. The transgranular diffusion and electromigration characteristics of Al and Cu in Al were unambiguously determined by developing and carrying out exper- iments using single-crystal Al interconnects fabricated on oxidized Si substrates. -
I N Situ SEM Observation of Electromigration Phenomena in Fully Embedded Copper Interconnect Structures M.A
Microelectronic Engineering 64 (2002) 375–382 www.elsevier.com/locate/mee I n situ SEM observation of electromigration phenomena in fully embedded copper interconnect structures M.A. Meyera,* , M. Herrmann b , E. Langer a , E. Zschech a a AMD Saxony Manufacturing GmbH Dresden, Materials Analysis Department, D-01330 Dresden, Germany bTechnische Universtat¨ Dresden, D-01062 Dresden, Germany Abstract An experimental set-up is presented, that allows in situ scanning electron microscope (SEM) investigations of the progress of electromigration damage in fully embedded copper interconnect structures. A LEO Gemini 1550 SEM has been equipped with a heating stage and electrical connections for the experiment. The studied interconnect structures are usually used for reliability testing in electromigration ovens. These test structures are located within the scribelines of wafers. Therefore, they allow the characterization of the electromigration behaviour of products on the wafer. To enable the SEM observation, focused ion beam (FIB) was used to prepare cross-sections of the samples maintaining their electrical functionality. Thereby, a thin layer of passivation was left over in front of the interconnects to keep them fully embedded. The SEM images which were taken at an angle of 608 allow the observation of both the entire via/contact and the connecting lines. Multiple images were recorded during the degradation experiments. The resulting video sequences provide a good visualization of the formation, growth and motion of voids at the stressed interconnects. The dominant diffusion path has been identified. 2002 Published by Elsevier Science B.V. Keywords: SEM; In situ; Electromigration; Dual–inlaid; Copper interconnect; Cross-section 1 . Introduction Electromigration and stress-induced degradation phenomena are reliability concerns for integrated circuits fabricated with inlaid copper technology. -
Process Integration Issues of Low-Permittivity Dielectrics with Copper for High-Performance Interconnects
PROCESS INTEGRATION ISSUES OF LOW-PERMITTIVITY DIELECTRICS WITH COPPER FOR HIGH-PERFORMANCE INTERCONNECTS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Alvin Leng Sun Loke March 1999 © Copyright by Alvin Leng Sun Loke 1999 All Rights Reserved Prepared under the support of the Semiconductor Research Corporation, and Graduate Research Fellowships from the Natural Sciences and Engineering Research Council of Canada and Rockwell Semiconductor Systems Integrated Circuits Laboratory Center for Integrated Systems Stanford University, Stanford, CA 94305-4070 ii I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. ___________________________ S. Simon Wong (Principal Advisor) I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. ___________________________ Krishna C. Saraswat I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. ___________________________ James S. Harris, Jr. Approved for the University Committee on Graduate Studies: ___________________________ Dean of Graduate Studies iii iv To Papa, Mummy, Alan, and Selene... v vi Abstract The relentless drive toward high-speed and high-density silicon-based integrated cir- cuits (IC’s) has necessitated significant advances in interconnect technology. In current process technologies, transistors are interconnected by multilevel aluminum and tungsten conductors encased in silicon dioxide (oxide) insulators. -
An Accelerated Test Method for Electromigration in Integrated Circuits Paul Andrew Uliana Lehigh University
Lehigh University Lehigh Preserve Theses and Dissertations 1989 An accelerated test method for electromigration in integrated circuits Paul Andrew Uliana Lehigh University Follow this and additional works at: https://preserve.lehigh.edu/etd Part of the Electrical and Computer Engineering Commons Recommended Citation Uliana, Paul Andrew, "An accelerated test method for electromigration in integrated circuits" (1989). Theses and Dissertations. 5251. https://preserve.lehigh.edu/etd/5251 This Thesis is brought to you for free and open access by Lehigh Preserve. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of Lehigh Preserve. For more information, please contact [email protected]. "... -( ' .. ,., •. AN ACCELERATED TEST METHOD FOR ELECTROMIGRATION · IN INTEGRATED CIRCUITS ! . i by Paul Andrew Uliana A Thesis Presented to the Graduate Committee of Lehigh University in Candidacy for the Degree of . Master of Science in the Department of Computer Science and Electrical Engineering \ ·, i '· ' /' ~ Lehigh University June 1989 1, ... ' . ' ' • " : ,\, \ ,· • ..• ,, · This thesis is accepted and approved in partial fulfillment of the requirements for the degree. of Master of S~ience. Date ., Professor in Charge .. 'r \ Chairman of Department • ,',/ f.,-"\ •• 11 .. !. ( f ,! Acknowledgements I ) The author would like to express his appreciation to the following people for their contributions: My advisor, Dr. F. H. Hielscher, for his help and suggestions. Daniel P. Chesire for use of the equipment, designing the test structures, and guidance through the entire project. Daniel L. Barton for helpful discussions and many wise comments. Scott Shive and Nancy Minor for providing fabricated wafers. Robert Graver for writing the prober control and other portions of the software. -
Effect of Microstructure on Electromigration
UC Berkeley UC Berkeley Electronic Theses and Dissertations Title The Influence of Sn Orientation on the Electromigration of Idealized Lead-free Interconnects Permalink https://escholarship.org/uc/item/3ht3215h Author Linares, Xioranny Publication Date 2015 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California The Influence of Sn Orientation on the Electromigration of Idealized Lead-free Interconnects By Xioranny Linares A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Materials Science and Engineering in the Graduate Division of the University of California, Berkeley Committee in charge: Professor J.W. Morris Jr., Chair Professor Andrew Minor Professor Tsu-Jae King Liu Summer 2015 Abstract The Influence of Sn Orientation on the Electromigration of Idealized Lead-free Interconnects By Xioranny Linares Doctor of Philosophy in Materials Science and Engineering University of California, Berkeley Professor J.W. Morris Jr., Chair As conventional lead solders are being replaced by Pb-free solders in electronic devices, the reliability of solder joints in integrated circuits (ICs) has become a high concern. Due to the miniaturization of ICs and consequently solder joints, the current density through the solder interconnects has increased causing electrical damage known as electromigration. Electromigration, atomic and mass migration due to high electron currents, is one of the most urgent reliability issues delaying the implementation of Pb-free solder materials in electronic devices. The research on Pb-free solders has mainly focused on the qualitative understanding of failure by electromigration. There has been little progress however, on the quantitative analysis of electromigration because of the lack of available material parameters, such as the effective charge, (z*), the driving force for electromigration. -
UNIVERSITY of CALIFORNIA, SAN DIEGO Optimization of the BEOL
UNIVERSITY OF CALIFORNIA, SAN DIEGO Optimization of the BEOL Interconnect Stack for Advanced Semiconductor Technology Nodes A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Electrical Engineering (Computer Engineering) by Pooja Pradeep Shah Committee in charge: Professor Andrew B. Kahng, Chair Professor Chung-Kuan Cheng Professor Bill Lin 2015 Copyright Pooja Pradeep Shah, 2015 All rights reserved. The thesis of Pooja Pradeep Shah is approved, and it is ac- ceptable in quality and form for publication on microfilm and electronically: Chair University of California, San Diego 2015 iii DEDICATION I dedicate this thesis to my loving husband Rakesh, my mother and my sister. This thesis would not have been possible without their encouragement and support. iv TABLE OF CONTENTS Signature Page . iii Dedication . iv Table of Contents . v List of Figures . vii List of Tables . ix Acknowledgments . x Vita ......................................... xi Abstract of the Thesis . xii Chapter 1 Introduction . 1 1.1 Motivation . 2 1.2 Our Contributions . 3 1.3 Limitations . 5 1.4 Outline of the Thesis . 5 Chapter 2 Previous Works . 7 2.1 Landmark Works . 8 2.2 Wire Optimization at System Level . 11 2.3 Wire Optimization Considering Layer Assignment . 13 2.4 Wire Sizing and Repeater Insertion . 14 2.5 Other Works . 16 2.6 Predictive Technology Models . 18 2.7 Reliability . 19 2.8 The ITRS BEOL Structure and Prediction . 20 2.9 Pitch Prediction . 22 2.10 Summary of Previous Works . 23 Chapter 3 Experiments for Interconnect Dimension Optimization and Vali- dation . 26 3.1 Our Flow . -
Preliminary Reliability Evaluation of Copper-Interconnect Metallization Technology
Preliminary Reliability Evaluation of Copper-Interconnect Metallization Technology Ashok K. Sharma NASA/Goddard Space Flight Center, Greenbelt, MD 20771 Alexander Teverovsky QSS Group, Inc., Goddard Space Flight Center, Greenbelt, MD 20771 1.0 Background The advantages of using copper for interconnection in microcircuits are mostly due to its lower resistance compared to the aluminum metallization. Copper-based metallization has specific resistance of less than 2 µΩ-cm compared to more than 3 µΩ-cm for aluminum metallization. In combination with a reduced susceptibility to electromigration failures, this enables designing of highly scaled devices with significantly reduced time delays. These features are mostly beneficial for high-performance microprocessors and fast static RAMs (FSRAM). In addition, copper interconnect process uses the dual damascene technology for deposition of copper, which can potentially reduce the manufacturing cost by eliminating some labor intensive steps of aluminum etching. This makes copper interconnect use quite attractive for semiconductor industry, and positions this technology as a standard interconnect process for the most high performance microcircuits in the future. Major problems with copper metallization are due to some specific physical/electrochemical properties. Copper does not create a passive oxide film (as aluminum does), has poor adhesion and high rate of diffusion through silicon and dielectric layers (organic and inorganic). This introduces new failure mechanisms such as poisoning of the P-N junctions, charge instability and formation of resistive shorts caused by copper electrochemical migration. The first on the market, copper-based FSRAM was manufactured by Motorola (the part is available since 1999). This part was used to gain experience with the copper-based interconnect design and technology, to analyze problems related to their evaluation and to obtain preliminary results of destructive physical analysis (DPA) of the parts. -
Finite-Element Modelling and Analysis of Hall Effect and Extraordinary Magnetoresistance Effect
Chapter 10 Finite-Element Modelling and Analysis of Hall Effect and Extraordinary Magnetoresistance Effect Jian Sun and Jürgen Kosel Additional information is available at the end of the chapter http://dx.doi.org/10.5772/47777 1. Introduction The Hall effect was discovered in 1879 by the American physicist Edwin Herbert Hall. It is a result of the Lorentz force, which a magnetic field exerts on moving charge carriers that constitute the electric current [1, 2]. Whether the current is a movement of holes, or electrons in the opposite direction, or a mixture of the two, the Lorentz force pushes the moving electric charge carriers in the same direction sideways at right angles to both the magnetic field and the direction of current flow. As a consequence, it produces a charge accumulation at the edges of the conductor orthogonal to the current flow, which, in turn, causes a differential voltage (the Hall voltage). This effect can be modeled by an anisotropic term added to the conductivity tensor of a nominally homogeneous and isotropic conductor. The Hall effect is widely used in magnetic field measurements due to its simplicity and sensitivity [2]. Hall sensors are readily available from a number of different manufacturers and are used in various applications as, for example, rotating speed sensors (bicycle wheels, gear-teeth, automotive speedometers, and electronic ignition systems), fluid flow sensors, current sensors or pressure sensors. Recently, a large dependence of the resistance on magnetic fields, the so-called extraordinary magnetoresistance (EMR), was found at room temperature in a certain kind of semiconductor/metal hybrid structure [3]. -
3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives Ayad Ghannam, David Bourrier, Lamine Ourak, Christophe Viallon, Thierry Parra
3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives Ayad Ghannam, David Bourrier, Lamine Ourak, Christophe Viallon, Thierry Parra To cite this version: Ayad Ghannam, David Bourrier, Lamine Ourak, Christophe Viallon, Thierry Parra. 3-D Multi- layer Copper Interconnects for High-Performance Monolithic Devices and Passives. Components, Packaging and Manufacturing Technology, 2013, 3 (6), pp.935-942. 10.1109/TCPMT.2013.2258073. hal-00920609 HAL Id: hal-00920609 https://hal.archives-ouvertes.fr/hal-00920609 Submitted on 19 Dec 2013 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. 1 3D Multi-layer Copper Interconnects for High Performance Monolithic Devices and Passives Ayad Ghannam, David Bourrier, Lamine Ourak, Christophe Viallon, and Thierry Parra suspended planar or 3D structures [9]-[12] are other Abstract—This paper presents a new and efficient low-cost technologies that enable direct above-IC integration of high-Q multi-layer 3D copper interconnect process for monolithic inductors. However, these approaches are either complex and devices and passives. It relies on the BPN and SU-8 photoresists, expensive or incompatible with standard silicon technologies associated with an optimized electroplating process to form which use low resistivity substrate. -
Electrochemical Atomic Layer Deposition of Metals for Applications in Semiconductor Interconnect Metallization
ELECTROCHEMICAL ATOMIC LAYER DEPOSITION OF METALS FOR APPLICATIONS IN SEMICONDUCTOR INTERCONNECT METALLIZATION by KAILASH VENKATRAMAN Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Thesis Advisor: Professor Rohan Akolkar Department of Chemical & Biomolecular Engineering CASE WESTERN RESERVE UNIVERSITY January, 2019 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the dissertation of Kailash Venkatraman Candidate for the Doctor of Philosophy degree* (signed) Prof. Rohan Akolkar (chair of the committee) Prof. Uziel Landau Prof. Christine Duval Prof. Mark De Guire Date: October 22, 2018 *We also certify that written approval has been obtained for any proprietary material contained therein. 1 DEDICATION Dedicated to my grandparents, Late Shri. S. Krishnaswamy and Smt. S. Sundaresan. 2 TABLE OF CONTENTS DEDICATION .....................................................................................................................2 LIST OF TABLES ...............................................................................................................6 LIST OF FIGURES .............................................................................................................7 ACKNOWLEDGEMENTS ...............................................................................................13 LIST OF SYMBOLS .........................................................................................................14 CHAPTER 1. Introduction ........................................................................................... -
"Process Integration Issues of Low-Permittivity Dielectrics with Copper for High-Performance Interconnects", Chapter
PROCESS INTEGRATION ISSUES OF LOW-PERMITTIVITY DIELECTRICS WITH COPPER FOR HIGH-PERFORMANCE INTERCONNECTS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Ph.D. CHAPTER 2 Alvin Leng Sun Loke March 1999 Chapter 2 Review of Interconnect Integration The investigations to be presented in subsequent chapters assume a basic command of interconnect process technologies. This chapter provides an overview of interconnect integration, emphasizing key features in both conventional Al and Damascene Cu technol- ogies. It is hoped that with this review, the less familiar reader will have acquired some relevant background information for comprehending the context of the work to follow. In conventional silicon IC technologies, the interconnects are incorporated after front- end processing. Frontend processing refers to the sequence of fabrication steps, typically at very high temperatures (700−1100°C), that form the MOS transistors in the active regions, the pockets of thick isolation in the field regions that separate adjacent transistors, and the silicidation of the transistor terminals for low-resistance contacts. The reader is directed to [38]−[40] for a representative flavor of manufacturable advanced frontend tech- nologies. The backend, referring to the interconnection of transistors, is subsequently formed by contacting the transistor terminals and then vertically stacking alternating layers of metal wires and vias encased in dielectric. Backend process temperatures typically do not exceed 450°C to avoid melting of the metals and to control stress. 17 Chapter 2: Review of Interconnect Integration 2.1 Conventional Technology The state-of-the-art 0.25-µm backend, shown in Figure 2-1, is revisited to illustrate the integration of conventional Al metallization.