Circuit Design for Realization of a 16 Bit 1MS/S Successive Approximation Register Analog-To-Digital Converter
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Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter by Cody Brenneman A Thesis Submitted to the Faculty of the WORCESTER POLYTECHNIC INSTITUTE in partial fulfillment of the requirements for the Degree of Master of Science in Electrical and Computer Engineering by May 2010 APPROVED: Professor John McNeill, Major Advisor Professor Stephen Bitar Professor Andrew Klein Abstract As the use of digital systems continues to grow, there is an increasing need to con- vert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0:18µm CMOS process, successfully operates at 1MS/s, and consumes a die area of 1:2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter. iii Acknowledgements It has been a great honor to work under Professor McNeill for the past three years. He has simultaneously helped me progress greatly in my knowledge of analog circuit design, while helping me realize how little I yet actually know. His insights into the technical aspects of the project helped push me through some of the more difficult design challenges. And his occasional "`well that's why we call it research"' pep-talks helped me get through some of the more mentally challenging aspects of the work, and helped me realize that failure is indeed a learning process. I would also like to thank my friends and lab mates. Chris David, for helping with the digital aspect of this project, and for always being willing to help me work through problems I encountered in my own design. Hattie Spetla, for always being there to share her food, and for giving me someone to talk to when I was tired of talking to myself. Tsai Chen and Shant Orchanian for never hesitating to help when I needed it. I would also like to thank all my friends outside the lab for all their support, and for helping me to get my mind off my work. I would especially like to thank my friends Valerie and Belinda Dietel, for constantly reminding me to get back to work whenever I was procrastinating. Last, but not least, I would like to thank my family. Without their support and encouragement I never would have been able to make it this far. I really appreciate their understanding and encouragement during the more stressful times. And a home cooked meal to go home to most evenings is always nice! iv Contents List of Figures vii List of Tables x 1 Introduction 1 2 Background 4 2.1 SAR Operation . .4 2.2 Differential SAR Architecture . .9 2.3 ADC Characterization . 12 2.3.1 Resolution and Sampling Rate . 12 2.3.2 Gain and Offset Errors . 14 2.3.3 Differential and Integral Nonlinearities . 14 2.3.4 SNR and ENOB . 16 2.4 SAR Error Sources . 16 2.5 Split ADC Review . 18 3 Circuit Design 20 3.1 DAC Design . 22 3.1.1 DAC Modifications . 22 3.1.2 Capacitor Switches . 23 3.1.3 DAC Settling Time . 25 3.2 Comparator . 29 3.2.1 Preamplifier Design . 30 3.2.2 Base Amplifier Design . 31 3.2.3 Front End Preamplifier . 35 Optimizing Device Sizes and Bias Current . 38 Simulation Results . 42 3.2.4 Secondary Amplifiers . 43 Simulation Results . 43 3.2.5 Preamplifier Chain . 44 v 3.2.6 Regenerative Latch . 46 Simulation Results . 48 3.2.7 Final Comparator . 48 3.3 Biasing . 50 3.3.1 Replica Bias . 52 4 Circuit Layout 57 4.1 First Layout Attempt . 57 4.1.1 Capacitor Switches . 58 4.1.2 Capacitor Blocks . 61 4.1.3 Regenerative Latch . 63 4.1.4 Front End Preamplifier . 64 4.1.5 Secondary Preamplifiers . 66 4.1.6 Comparator . 67 4.1.7 DAC and Comparator . 67 4.2 Final Layout . 69 4.2.1 Half DAC . 72 4.2.2 Comparator . 73 4.2.3 Complete SAR . 74 4.3 Pad Ring . 76 4.3.1 Analog Pads . 76 4.3.2 Digital Pad Selection . 79 4.4 Full Chip Layout . 79 5 Chip Evaluation 81 5.1 Support Circuitry . 82 5.1.1 Power Rails . 82 5.1.2 Single to Differential Converter . 83 5.1.3 Reference Voltages . 85 Stability Analysis . 87 5.2 Filter Design . 89 5.2.1 Notch Filter . 90 5.2.2 Lowpass Filter . 93 5.3 Problems . 97 5.4 Results . 101 6 Conclusions 106 6.1 Future Work . 107 A Buffer Stability Code 108 B Filter Calculations Code 110 vi C PCB Schematics 112 D Bonding Diagram 117 E IC Packaging 118 Bibliography 119 vii List of Figures 2.1 Single Ended SAR Block Diagram . .5 2.2 Algorithm Illustration . .6 2.3 DAC Voltage for 4-bit SAR . .7 2.4 Single Ended Capacitive SAR Circuit . .8 2.5 Differential SAR Block Diagram . .9 2.6 Differential SAR DAC Voltages . 10 2.7 Differential Capacitive SAR Circuit . 11 2.8 Ideal ADC Transfer Function . 13 2.9 Ideal ADC Quantization Error . 13 2.10 ADC Transfer Function with Gain and Offset Errors . 14 2.11 DNL and INL Errors in ADC Transfer Characteristic . 15 2.12 DAC Waveforms with Redundant Bit Recovery . 17 2.13 Split ADC Architecture . 18 2.14 SAR Capacitor Selection . 19 3.1 Split SAR System Block Diagram . 20 3.2 Split SAR Timing Diagram . 21 3.3 Differential SAR with Modified DAC Structures . 23 3.4 1pF Capacitor Switches . 24 3.5 125fF Capacitor Switches . 24 3.6 Parasitic Model . 25 3.7 DAC Switching Action . 26 3.8 Undamped DAC Oscillations . 27 3.9 Damped DAC Oscillations . 28 3.10 Damping Network . 28 3.11 Comparator Symbol . 29 3.12 Base Preamplifier Topology . 31 3.13 Preamplifier Small Signal Model . 32 3.14 Front End Preamplifier Schematic . 35 3.15 Transconductance Curves . 39 3.16 Width vs Bias Current . 41 viii 3.17 Time vs Bias Current . 41 3.18 Front End Preamplifier Gain . 42 3.19 Secondary Preamplifier Gain . 44 3.20 Preamplifier Chain . 45 3.21 Preamplifier Chain Gain . 45 3.22 Regenerative Latch Schematic . 46 3.23 Regenerative Latch Simulations . 49 3.24 Final Comparator Symbol . 49 3.25 Bias Block Schematic . 51 3.26 Bias Current vs Bias Resistor Value . 52 3.27 Bias Block Multiplier vs Bias Resistor Value . 53 3.28 Normal Current Mirror Biasing . 54 3.29 Current Deviation without Replica . 54 3.30 Replica Current Mirror Biasing . 55 3.31 Current Deviation with Replica . 56 4.1 Original Layout Hierarchy for Analog Portion of SAR . 59 4.2 Capacitor and Switch Layout Plan . 60 4.3 1pF Cap Switches . 61 4.4 125fF Cap Switches . 61 4.5 1pF Cap Block . 62 4.6 125fF Block . ..