CpE 252 Organization & Design

Digital Logic Circuits Content

 Digital

 Logic Gates

 Expression Simplification

 Combinational Logic

 Sequential Logic

Dr. T. Eldos 2 Digital Computers: Block Diagram

Random Access Memory ( R A M )

Central Processing Unit ( C P U )

Input Input-Output Output Devices ( I O P ) Devices

Dr. T. Eldos 3 Computer Hardware

 Computer Architecture

 Concerned with the structure and behavior of the computer as seen by the user

 Specifies the various functional modules

 Include: Instruction Set, Information Formats and Addressing Modes

 Computer Organization

 Concerned with the way the hardware components are connected, and

 The way the hardware components operate

 Computer Design

 Concerned with the hardware design of the computer

 Once the specifications are formulated, it is the task of the designer to develop hardware for the system (sometimes called computer) implementation

Dr. T. Eldos 4 Design Levels

Architecture Logic Electronic

Dr. T. Eldos 5 Logic Gates

A A F A B F F A B F A F A F B B 0 0 0 0 0 0 0 1 AND 0 1 0 OR 0 1 1 NOT 1 0 1 0 0 1 0 1 1 1 1 1 1 1

A A F A B F F A B F A F A F B B 0 0 1 0 0 1 0 0 NAND 0 1 1 NOR 0 1 0 BUF 1 1 1 0 1 1 0 0 1 1 0 1 1 0

A A F A B F F A B F B B 0 0 0 0 0 1 XOR 0 1 1 XNOR 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1

Dr. T. Eldos 6 Representation: Truth Tables & Logic Diagrams

Description F is true IF  A is true, OR  C is true AND B is false  B will never be true if neither A nor B is true

Truth Table SOP & POS Forms Expression K-Map A B C F BC 0 0 0 0 F = A’B’C+AB’C’+AB’C+ABC’+ABC 00 01 11 10 0 0 1 1 F = (A+B+C)(A+B’+C)(A+B’+C’) A 0 1 0 x 0 1 x 0 1 1 0 1 1 1 1 1 0 0 1 Minterms & Maxterm List 1 1 0 1 1 1 1 0 1 F =  m (1, 4, 5, 6, 7) + d(2) 1 1 1 1 F =  M(0,2,3) D(2) Standard Form F = A = B’C

Logic Diagram A F B C

Dr. T. Eldos 7 Boolean Algebra: Basic Identities & Symbols

X + 0 = X X  0 = 0 X + 1 = 1 X  1 = X X + X = X X  X = X X + X’ = 1 X  X’ = 0 X + Y = Y + X X  Y = Y  X X + (Y + Z) = (X + Y) + Z X  (Y  Z) = (X  Y)  Z X  (Y+Z) = X  Y + X  Z X + Y  Z = (X + Y)  (X + Z) (X + Y)’=X’  Y’ (X  Y)’ = X’ + Y’ (X’)’ = X

A A NOR: OR-NOT & NOT-AND B F B F C C

A A NAND: AND-NOT & NOT-OR B F B F C C

Dr. T. Eldos 8 Function Simplification: 2 Diagrams & 1 Function

A B C

F

F = ABC + ABC’ + A’C

A B C F

F = AB + A’C

Dr. T. Eldos 9 Combinational & Sequential Logic

 Combinational Logic Circuits

 Output at any instant of time depends on

 Input at that instant of time, ONLY

 Sequential Logic Circuits

 Output at any instant of time depends on

 Input at that instant of time, AND

 Current of the circuit (or the past input)

 So, difference is that combinational has no memory

Combinational Combinational Input Output Input Output Logic Gates Logic Gates

Combinational Logic Memory or Delay

Sequential Logic

Dr. T. Eldos 10 Combinational Logic Example

Truth Table Cout S A B C C S in out BCin BCin ------00 01 11 10 00 01 11 10 0 0 0 0 0 A A 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 Cout = BCin + ACin + AB S = A  B  Cin 1 1 1 1 1 Cout = AB + Cin (A  B)

A S A B S B Full Cin Couyt Cin Couyt

Dr. T. Eldos 11 Set/Reset Latch, Gated Latch & Flip-Flop

S’ S’ Q Q S’R’ Latch Q’ R’ R’ Q’

S S Q Q SR C C S’R’ Gated Latch Latch R Q’ R Q’

Q J Q J SR JK C Gated C Gated K Latch Latch Q’ K Q’

Dr. T. Eldos 12 D-type & T-type Flip-Flops

J Q J Q JK JK JK CK Gated Gated CK Flip Latch Latch Flop K Q’ K Q’

D Q D Q JK D CK Flip CK Flip Flop Flop Q’ Q’

T Q T Q T JK CK Flip CK Flip Flop Flop Q’ Q’

Dr. T. Eldos 13 Latches and Flip-Flops Characteristics Tables

S’R’ Latch S’R’ Gated Latch JK Gated Latch S’ R’ Q+ C S R Q+ C J K Q+ ------0 0 Undetermined 0 x x Q 0 x x Q 0 1 1 1 0 0 1 0 0 Undetermined 1 0 0 Q 1 1 Q 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 1 Q 1 1 1 Q’

JK Flip-Flop D Flip-Flop T Flip-Flop CK J K Q+ CK D Q+ CK T Q+ ------0 x x Q 0 x Q 0 x Q 1 x x Q 1 x Q 1 x Q  x x Q  x Q  x Q

 0 0 Q’  0 0  0 Q  0 1 1  1 1  1 Q’  1 0 0  1 1 Q’

Dr. T. Eldos 14 Sequential Circuits Design Example

Present Next x =0 x =0 State Input State Flip-Flop Inputs x =1 A B x A B J K J K 00 11 0 0 0 0 0 0 x 0 x 0 0 1 0 1 0 x 1 x x =1 x =1 0 1 0 0 1 0 x x 0 0 1 1 1 0 1 x x 1 01 10 1 0 0 1 0 x 0 0 x x =1 1 0 1 1 1 x 0 1 x x =0 x =0 1 1 0 1 1 x 0 x 0 1 1 1 0 0 x 1 x 1

Bx Bx x A 00 01 11 10 A 00 01 11 10 A J 0 1 0 x x x x 1 1 K x x x x 1

Bx Bx 00 01 11 10 00 01 11 10 B A A J 0 0 CK 1 x x x x 1 K 1 1 x x 1 x x 1

Dr. T. Eldos 15