STRS Compliant FPGA Waveform Development
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AN FPGA ABSTRACTION LAYER FOR THE SPACE TELECOMMUNICATIONS RADIO SYSTEM by JENNIFER NAPPIER Submitted in partial fulfillment of the requirements For the degree of Master of Science Thesis Advisor: Dr. Frank Merat Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY January, 2009 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis/dissertation of _____________________________________________________Jennifer M. Nappier Master of Science candidate for the ______________________degree *. Dr. Frank Merat (signed)_______________________________________________ (chair of the committee) Dr. Marc Buchner ________________________________________________ Dr. Christos Papachristou ________________________________________________ ________________________________________________ ________________________________________________ ________________________________________________ 11/05/08 (date) _______________________ *We also certify that written approval has been obtained for any proprietary material contained therein. Table of Contents List of Abbreviations ......................................................................................................... vi List of Abbreviations ......................................................................................................... vi Abstract............................................................................................................................viii 1 Introduction............................................................................................................... 10 2 STRS Waveform Development Goals ...................................................................... 14 2.1 Design a waveform that is reconfigurable ........................................................ 14 2.2 Design a waveform that is reusable and portable across SDRs........................ 14 2.3 Design a waveform that is platform independent ............................................. 15 3 Current STRS Architecture Standard ....................................................................... 16 4 Other Standards......................................................................................................... 18 4.1 Joint Tactical Radio System (JTRS) Software Communication Architecture.. 18 4.2 WISHBONE System-on-Chip Interconnection Architecture ........................... 19 4.3 Open Core Protocol Specification .................................................................... 20 5 Extension to STRS: Firmware Developer Interface ................................................. 22 6 Implementation ......................................................................................................... 27 7 FDI Testing ............................................................................................................... 33 7.1 GPP Control Read and Control Write............................................................... 33 7.2 GPP Data Read and Data Write........................................................................ 34 7.3 ADC Data Read and DAC Data Write ............................................................. 35 8 Future Work.............................................................................................................. 37 9 References................................................................................................................. 39 iii List of Tables Table 1: Control FDI signals. ........................................................................................... 25 Table 2: Corresponding FDI DATA and API NAME pairs. ............................................ 25 Table 3: Data FDI signals. ................................................................................................ 26 Table 4: FDI Verilog file descriptions.............................................................................. 30 iv List of Figures Figure 1: STRS Hardware Architecture Diagram............................................................. 11 Figure 2: MHAL API diagram [4].................................................................................... 19 Figure 3: WISHBONE module interfaces [5]................................................................... 20 Figure 4: OCP IP cores communicate via a wrapped buss [6]. ........................................ 21 Figure 5: Conceptual drawing of the Firmware Developer Interface in the FPGA.......... 23 Figure 6: High level block diagram of SDR breadboard.................................................. 28 Figure 7: Conceptual implementation example of the Firmware Developer Interface. ... 28 Figure 8: FDI implementation with file structure labeled. ............................................... 29 Figure 9: FPGA waveform controller............................................................................... 33 Figure 10: GPP control read and control write test. ......................................................... 34 Figure 11: GPP data read and data write test.................................................................... 35 Figure 12: ADC data read and DAC data write loop back test......................................... 36 v List of Abbreviations ADC – Analog to digital converter API – Application programmer interface ASIC – Application specific integrated circuit CoNNeCT – Communications, Navigation and Networking re-Configurable Test bed DAC – Digital to analog computer DSP – Digital signal processor FDI – Firmware developer interface FEC – Forward error correction FIFO – First in first out FPGA – Field programmable gate array GPM – General-purpose processing module GPP – General purpose processor GRC – Glenn Research Center HDL – Hardware description language HID – Hardware interface description IF – Intermediate frequency ISE – Integrated software environment ISS – International Space Station JPEO – Joint Program Executive Office JTRS – Joint Tactical Radio System MHAL – Modem Hardware Abstraction Layer OCP – Open Core Protocol vi NASA – National Aeronautics and Space Administration RF – Radio frequency RFM – Radio frequency module SCA – Software Communications Architecture SDR – Software defined radio SPM – Signal processing module SOC – Silicon-on-a-chip SSP – Specialized signal processing STRS – Space Telecommunications Radio System VHDL – Very high speed integrated circuits (VHSIC) hardware description language VHSIC – Very high speed integrated circuits vii An FPGA Abstraction Layer for the Space Telecommunications Radio System Abstract by Jennifer Nappier The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the specialized signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. The extension of STRS to the SSP hardware will promote easier waveform reconfiguration and reuse. Extensions of the STRS Architecture Standard in the field programmable gate array (FPGA) were proposed. The extensions included a standard hardware abstraction layer for firmware in FPGAs. Current existing FPGA hardware abstraction layer standards were researched. These standards included the Joint Tactical Radio System (JTRS) Modem Hardware Abstraction Layer (MHAL), the WISHBONE Architecture, and the Open Core Protocol (OCP). The proposed STRS hardware abstraction layer was designed to provide standardized interfaces to the STRS waveform application running on the FPGA. Therefore, the waveform developer would not have to know a lot of viii information about the rest of the SDR platform. This standard hardware abstraction layer was called the Firmware Developer Interface (FDI). The FDI was implemented and tested on a laboratory breadboard SDR. The implementation and testing of the FDI on a laboratory breadboard SDR will be discussed. ix 1 Introduction The Space Telecommunications Radio System (STRS) Architecture Standard [1] specifies an open architecture for NASA space software defined radios (SDRs). The STRS Architecture Standard divides the SDR into three functional hardware modules – the general-purpose processing module (GPM), the radio frequency module (RFM), and the signal processing module (SPM). There is a hardware interface description (HID) between each module that describes all of the physical hardware interfaces. The GPM contains a general purpose processor (GPP), memory, and the Spacecraft Telemetry Interface. The GPM runs the STRS Infrastructure and configures and controls the entire radio. The RFM contains filters, up/down converters, power amplifiers, digital to analog converters (DACs), and analog to digital converters (ADCs). It handles the conversion between the radio frequency (RF) and the intermediate frequency (IF) signals. The SPM contains a field programmable gate array (FPGA), digital signal processor (DSP), application specific integrated circuit (ASIC), or other specialized signal processing (SSP) device. The SPM performs the transformations between the IF digitally sampled signals and