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Formal Methods in Computer Aided Design Computer Aided Design Aided Computer Methods in Formal Formal Methods in Computer Aided Design Lugano, Switzerland • 20-23 October, 2010 Edited by Roderick Bloem and Natasha Sharygina Lugano, Switzerland • 20-23 October, 2010 • 20-23 October, Switzerland Lugano, In cooperation with ACM’s SIGPLAN (Special Interest Group on Programming Languages) and SIGSOFT (Special Interest Group on Software Engineering) Technical Sponsorship from IEEE Council on Electronic Design Automation (CEDA) 2010 Formal Methods in Computer Aided Design Copyright © 2010 by Formal Methods in Computer Aided Design Inc. All rights reserved. Copyright and Reprints Permission Personal use of the material is permitted. 46954 IEEE PMCAD Cover_mp.indd 1 9/30/2010 10:34:23 AM Formal Methods in Computer Aided Design -VHBOP 4XJU[FSMBOEt0DUPCFS &EJUFECZ3PEFSJDL#MPFNBOE/BUBTIB4IBSZHJOB *ODPPQFSBUJPOXJUI"$.T4*(1-"/ 4QFDJBM*OUFSFTU (SPVQPO1SPHSBNNJOH-BOHVBHFT BOE4*(40'5 4QFDJBM*OUFSFTU(SPVQPO4PGUXBSF&OHJOFFSJOH 5FDIOJDBM4QPOTPSTIJQGSPN*&&&$PVODJMPO&MFDUSPOJD %FTJHO"VUPNBUJPO $&%" 'PSNBM.FUIPETJO$PNQVUFS"JEFE%FTJHO $PQZSJHIUªCZ'PSNBM.FUIPETJO$PNQVUFS"JEFE%FTJHO*OD "MMSJHIUTSFTFSWFE $PQZSJHIUBOE3FQSJOUT1FSNJTTJPO 1FSTPOBMVTFPGUIFNBUFSJBMJTQFSNJUUFE Formal Methods in Computer Aided Design Copyright © 2010 by Formal Methods in Computer Aided Design, Inc. All rights reserved. Copyright and Reprint permission: Personal use of the material is permitted For other copying, reprint, or republication permission, write to IEEE Copyrights Manager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. All rights reserved. IEEE Catalog Number CFP10FMC-ART ISBN 978-0-9835678-0-6 Additional copies of this publication are available from: Curran Associates, Inc. 57 Morehouse Lane, Red Hook, NY 12571 USA Phone: (845) 758-0400 Fax: (845) 758-2633 E-mail: [email protected] Conference Organization Program Chairs Roderick Bloem, Graz University of Technology, Austria Natasha Sharygina, University of Lugano, Switzerland and CMU, USA Industrial Track Chairs Wolfgang Ecker, Infineon, Germany Cindy Eisner, IBM Haifa Research Laboratory Tutorial Chair Helmut Veith, TU Wien Publication Chair Hana Chockler, IBM Haifa Research Laboratory Panel Chair Tom Melham, University of Oxford, UK Steering Committee Jason Baumgartner, IBM, USA Aarti Gupta, NEC Labs, USA Warren Hunt, University of Texas at Austin, USA Panagiotis Manolios, Northeastern University, USA Mary Sheeran, Chalmers University of Technology, Sweden iii Local Arrangements Umberto Bondi, University of Lugano Daniela Dimitrova,University of Lugano Elisa Larghi, University of Lugano Francesco Regazzoni, USI Lugano,andUCL Louvain-la-Neuve (Belgium) Mariagiovanna Sami, University of Lugano iv Programme Committee Technical Program: Jason Baumgartner, IBM, USA Valeria Bertacco, University of Michigan, USA Armin Biere, Johannes Kepler University, Austria Per Bjesse, Synopsys, Inc., USA Roderick Bloem, Graz University of Technology, Austria Doron Bustan, Intel, Israel Gianpiero Cabodi, Politecnico di Torino, Italy Alessandro Cimatti, IRST, Italy Koen Claessen, Chalmers University of Technology, Sweden Ganesh Gopalakrishnan, University of Utah, USA Aarti Gupta, NEC Labs, USA Ziyad Hanna, Jasper Design Automation, USA Alan Hu, University of British Columbia, Canada Jie-Hong Roland Jiang, National Taiwan University, Taiwan Barbara Jobstmann, CNRS-Verimag, France Vineet Kahlon, NEC, USA Gerwin Klein, NICTA, Australia Daniel Kroening, Oxford University Computing Laboratory, UK Thomas Kropf, University of T¨ubingen, Germany Marta Kwiatkowska, Oxford University Computing Laboratory, UK Oded Maler, CNRS-Verimag, France Panagiotis Manolios, Northeastern University, USA Ken McMillan, Cadence Berkeley Labs, USA Tom Melham, Oxford University Computing Laboratory, UK John O’Leary, Intel, USA Lee Pike, Galois, Inc., USA Marc Pouzet, University of Paris-Sud, France Julien Schmaltz, Open University of The Netherlands, Netherlands Natarajan Shankar, Computer Science Laboratory, SRI, USA Natasha Sharygina, University of Lugano, Switzerland and CMU, USA Satnam Singh, Microsoft Research Anna Slobodova, Centaur Technology, USA Sofiene Tahar, Concordia University, Canada Helmut Veith, Vienna University of Technology, Austria Karen Yorav, IBM Haifa Research Laboratory, Israel Industrial track: Pranav Ashar, RealIntent, USA Lyes Benalycherif, ST-Ericsson, France Per Bjesse, Synopsys, Inc., USA Holger Busch, Infineon, Germany v Joachim Gerlach, Albstadt-Sigmaringen University, Germany Ziyad Hanna, Jasper Design Automation, USA Christian Jacobi, IBM, Germany Peter Jensen, SyoSil Aps, Denmark Andreas Kuehlmann, Cadence Berkeley Labs, USA Ajeetha Kumari, CVC Pvt Ltd, India Viresh Paruthi, IBM, USA Axel Scherer, Cadence Design Systems. Inc, USA Michael Siegel, OneSpin Solutions, Germany vi External Reviewers Naeem Abbasi, Rawan Abdel-Khalek, Sa’ed Abed, Oshri Adler, Behzad Ak- barpour, Holzer Andreas, Gadiel Auerbach, Shoham Ben-David, Jesse Bing- ham, Magnus Bjork, Nicolas Blanc, Sascha B¨ohme, Ahmed Bouajjani, Marius Bozga, Marco Bozzano, Sebastian Burckhardt, Michael Case, Paul Caspi, Harsh Raju Chamarthi, Debapriya Chatterjee, Wei-Fan Chiang, Chris Chilton, Hana Chockler, David Cock, Claudionor Coelho Jr., Scott Cotton, William Denman, Andrew DeOrio, Flavio M. De Paula, Alastair Donaldson, Vijay D’silva, Ashvin Dsouza, Bruno Dutertre, Wolfgang Ecker, Kai Engelhardt, Levent Erk¨ok, Ranan Fraer, Amjad Gawanmeh, Steven German, Amit Goel, Eugene Goldberg, Joseph Greathouse, David Greenaway, Andreas Griesmayer, Alberto Griggio, Ali Habibi, Leopold Haller, Hakan Hjort, Andreas Holzer, Wei-Lun Hung, Norris Ip, Alexan- der Ivrii, Himanshu Jain, Geert Janssen, Matti J¨arvisalo, Susmit Jha, Ian Johnson, Krishnan Kailas, Alexander Kaiser, Mark Kattenbelt, Zurab Khasi- dashvili, Johannes Kinder, Udo Krautz, Smita Krishnaswamy, Sumit Kumar Jha, Sudipta Kundu, Julien Legriel, Rebekah Leslie, Djones Lettnin, Guodong Li, Michael Lifshits, Lars Lundgren, Louis Mandel, Johan Martensson, John Matthews, Stephan Merz, Alan Mishchenko, David Monniaux, Hari Mony, In- Ho Moon, John Moondanos, Shiri Moran, Cesar Munoz, Iman Narasamdya, Rajeev Narayanan, Ziv Nevo, Dejan Nickovic, Sergio Nocco, Michael Norrish, Steven Obua, Ritesh Parikh, David Parker, Grant Olney Passmore, Andrea Pel- legrini, Florence Plateau, Hongyang Qu, Stefano Quer, Kairong Quian, Sivan Rabinovitch, Silvio Ranise, Rajeev Ranjan, Pascal Raymond, Marco Roveri, Philipp Ruemmer, Georgia Safe, Bastian Schlich, Viktor Schuppan, Subodh Sharma, Nishant Sinha, Sebastian Skalberg, Jeremy Sproston, Stefan Staber, Muralidhar Talupur, Murali Talupur, Michael Tautschnig, Andrei Tchaltsev, Ashish Tiwari, Aaron Tomb, Stefano Tonetta, Rob van Glabbeek, Tatyana Vek- sler, Srinivasan Venkataramanan, Freek Verbeek, Anh Vo, Kai Weber, Georg Weissenbacher, Tobias Welp, Andy Yu, Florian Zuleger. vii Table of Contents Tutorials. Dimensions in Program Synthesis ....................................................................... 1 Sumit Gulwani Verifying VIA Nano Microprocessor Components ................................................ 3 Warren A. Hunt, Jr. Session 1. Invited Talk Embedded Systems Design: Scientific Challenges and Work Directions ........... 11 Joseph Sifakis Session 2. Industrial Track – Case Studies Formal Verification of an ASIC Ethernet Switch Block ....................................... 13 Balekudru Krishna, Anamaya Sullerey, Alok Jain Formal Verification of Arbiters using Property Strengthening and Under-approximations ........................................................................................ 21 Gadiel Auerbach, Fady Copty, Viresh Paruthi SAT-Based Semiformal Verification of Hardware ............................................... 25 Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, Alexander Nadel DFT Logic Verification through Property Based Formal Methods - SOC to IP ........................................................................................................... 33 Lopamudra Sen, Supriya Bhattacharjee, Amit Roy, Bijitendra Mittra, Subir K Roy Session 3. Software Verification SLAM2: Static Driver Verification with Under 4% False Alarms ......................... 35 Thomas Ball, Ella Bounimova, Rahul Kumar, Vladimir Levin ix Precise Static Analysis of Untrusted Driver Binaries .......................................... 43 Johannes Kinder, Helmut Veith Verifying SystemC: a Software Model Checking Approach ................................ 51 Alessandro Cimatti, Andrea Micheli, Iman Narasamdya, Marco Roveri Session 4. Decision Procedures Coping with Moore's Law (and More): Supporting Arrays in State-of-the-Art Model Checkers ................................................................................................. 61 Jason Baumgartner, Michael Case, Hari Mony CalCS: SMT Solving for Nonlinear Convex Constraints ..................................... 71 Pierluigi Nuzzo, Alberto Puggelli, Sanjit Seshia, Alberto Sangiovanni-Vincentelli Integrating ICP and LRA Solvers for Deciding Nonlinear Real Arithmetic Problems ............................................................................................................ 81 Sicun Gao, Malay Ganai, Franjo Ivancic, Aarti Gupta, Sriram Sankaranarayanan, Edmund Clarke Session 5. Synthesis A Halting Algorithm to Determine the Existence of Decoder .............................. 91 ShengYu Shen, Ying Qin, Jianmin Zhang, SiKun Li Synthesis for Regular Specifications over Unbounded Domains ...................... 101 Jad
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