DOCSLIB.ORG

WISHBONE Interface for Our SOC Design

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
WISHBONE Interface for Our SOC Design DESIGN AND VERIFICATION OF WISHBONE BUS INTERFACE FOR SOC INTEGRATION A thesis submitted in partial fulfilment of the requirements for the degree of Master of Technology (Research) in Electronics & Communication Engineering By Ayas Kanta Swain Roll No: 60609001 Under the supervision of Dr. KamalaKanta Mahapatra Professor Department of Electronics & Communication Engineering National Institute of Technology, Rourkela, Orissa January 2010 Dedicated to my family Department of Electronics & Communication Engineering NATIONAL INSTITUTE OF TECHNOLOGY, ROURKELA ORISSA, INDIA – 769 008 CERTIFICATE This is to certify that the thesis titled “Design and Verification of WISHBONE Bus Interface for SOC Integration” submitted to the National Institute of Technology, Rourkela by Ayas Kanta Swain, Roll No. 60609001 for the award of the degree of Master of Technology (Research) in Electronics & Communication Engineering, is a bonafide record of research work carried out by him under my supervision and guidance. The candidate has fulfilled all the prescribed requirements. The thesis, which is based on candidate’s own work, has not been submitted elsewhere for a degree/diploma. In my opinion, the thesis is of standard required for the award of a Master of Technology (Research) degree in Electronics & Communication Engineering. To the best of my knowledge, he bears a good moral character and decent behaviour. Prof. K. K. Mahapatra Professoor Department of Electronics & Communication Engineering NATIONAL INSTITUTE OF TECHNOLOGY Rourkela‐769 008 (INDIA) Email: [email protected] ACKNOWLEDGEMENT I would like to take this opportunity to extend my deepest gratitude to my teacher and supervisor, Prof. K. K. Mahapatra, for his continuous encouragement and active guidance. I am indebted to him for the valuable time he has spared for me during this work. He is always there to meet and talk about my ideas and he is great moral support behind me in carrying out my research work. I am very much thankful to Prof. S. K. Patra, HOD, ECE Department for his continuous encouragement. I am grateful to Prof. G.S.Rath, Prof.S.Meher, Prof.T.K.Dan and Dr.D.P.Acharya, Prof. S.K.Behera, Prof. Ajit Sahoo and Prof.B.D.Sahoo for valuable suggestions and comments during this research period. In addition, I am grateful to Prof. A. Routray and Prof. B.S. Das, IIT Kharagpur for giving me an opportunity to work with them; this introduced me to the area of research and development. I am grateful to www.opencores.org for their technical support during the complete project period. I need to thank my friends especially Saroj, who stands with me in all my endeavours. And also I am thankful to him for making my thesis more representable. In addition, let me thank all my friends Jitendra sir, Sushant, Sudeendra, Trillochan, Sanatan, Devi, Prasanta, Karuppanan, Deepak,Arun, Tom, Soumya, Jagannath and Peter for their great support and encouragement during the research period. Also, I am thankful to all the non-teaching staffs of ECE Department for their kind cooperation. I would like to thank Department of Information Technology, Govt. of India, for supporting me under SMDP-VLSI project. Last but not the least; I would like to thank my parents, brother and sister for their unconditional support and encouragement to carry out research. I am also thankful to my sister for helping me in typing the part of my thesis. Ayas Kanta Swain BIO-DATA Name of the Candidate : Ayas Kanta Swain Father’s Name : Kulamani Swain S/o. Kulamani Swain Permanent Address : F-17, Sector-7 Rourkela-3 Date of Birth : 26th August 1979 Email ID : [email protected] ACADEMIC QUALIFICATION • Continuing M. Tech (Research) in Dept. of Electronics and Communication Engineering, National Institute of Technology Rourkela, Orissa (INDIA). • B. E. (Hons.) (Electrical Engineering), IGIT, Sarang, Utkal University, Orissa EXPERIENCE • Working as a Contractual Faculty, in Project “Special Man Power Development Project for VLSI Design and its Related Software” funded by DIT under MCIT, Delhi. • Worked as a Research Engineer in DST Sponsored Project in Dept. of AG&FE. & Dept. of Electrical Engg., IIT Kharagpur • Worked as a Guest Faculty at Dept. Elect. Engg.,IGIT Sarang, Dhenkanal, Orissa. PUBLICATIONS: Published 01 paper in International Conferences; ABSTRACT The rapid development in the field of mobile communication, digital signal processing (DSP) motivated the design engineer to integrate complex systems of multimillion transistors in a single chip. The integration of the transistor in a single chip greatly increases the performance of the system while reduction in system size. Recently, there is a considerable increase in the application front in several areas of engineering and technology. Moore’s law states that integration density gets doubled every two years, so the complexity of the integrated circuits also increases by keeping the used chip area constant. In order to keep pace with the levels of integration available, design engineers have developed new methodologies and techniques to manage the increased complexity in these large chips. System-on-Chip (SOC) design is proposed as an extended methodology to this problem where pre-designed and pre-verified IP cores of embedded processors, memory blocks, interface blocks, and analog blocks are combined on a single chip targeting a specific application. These chips may have one or more processors on chip, a large amount of memory, bus-base architectures, peripherals, co processors, and I/O channels. These chips integrates systems far more similar to the boards designed ten years ago that to the chips of even a few years ago. The primary drivers for this are the reduction of power, smaller form factor, and lower overall cost. SOC offers many benefits such as smaller space requirements with higher performance. Design reuse- the use of predesigned and pre-verified cores – is now the cornerstone of SOC design. It uses reusable IP blocks that supports plug and play integration and in turn allows huge chips to be designed at an acceptable cost, and quality. The benefits SOC design methodology also come with challenges such as: larger design space, higher design and prototype costs. Apart from these challenges, the design again needs an expertise in both hardware and software levels for proper hardware and software co-design. Another important aspect of SOC integration is the development of a proper test methodology for post manufacturing test. All these integration issues makes the design time consuming and also expensive. To deal with this inherent integration problems and reduction in design cycle time, platform based SoC design was proposed where new designs could be quickly created from the original platform over many design derivatives. More specifically a platform is an abstraction level that covers a number of refinements to a lower level resulting in improvement of the design productivity. In other side, a new concept that is gaining interest is the Open Core SoC design methodology which is based on publishing all necessary information about the hardware. Open Core group has provided many pre-synthesized and pre-verified hardware core for the designer under GPL/LGPL license. This thesis investigates the Open core based SOC design platform. Open Core uses a standard bus WISHBONE to alleviate System-on-Chip problem. The various issues related to Open Core WISHBONE bus interfaces are presented in this thesis. These include WISHBONE specification, types of interconnections, WISHBONE Bus cycles.etc. A comparison of three bus protocol has been discussed. The issues related to design of a WISHBONE compatible IP core, Point-to-Point interconnection, shared bus interconnection is also presented in this investigation. All the designs are validated by XILINX ISE simulation results and real time debugging signals though ChipScope Pro. A SOC design methodology has been presented for a proposed SOC architecture. Afterwards a SOC architecture of 32-bit RISC CPU, memory, System Controller, UART and PIO has been proposed and the design methodology used to implement the SOC in FPGA has been discussed. The functionality of CPU operation in SOC architecture is verified by simulation results and corresponding steps for FPGA implementation of the SOC architecture with synthesis results have been presented. Finally, application software ha been developed in C and the object file is ported to FPGA system for validation of the SOC functionality of the SOC architecture. Table of Contents: List of Figures i List of Tables v List of Abbreviations vi 1. System on Chip: An Overview 1 1.1 Concept of System-on-Chip 2 1.2 History of SOC 4 1.3 Design Reuse Concept 4 1.3.1 Design for reuse 5 1.4 The system on chip design flow and process 6 1.4.1 A canonical SOC design 6 1.4.2 System Design Flow 7 I. Waterfall vs. Spiral 7 II. Top-down Vs. Bottom up 9 1.4.3 The System Design Process 11 1.5 System level Design Issues 14 1.5.1 Different Types of IP Cores 14 I. Digital IP 14 II. AMS IP 15 1.5.2 System Interconnect and On Chip-Buses 15 1.5.3 SOC Test Methodologies 15 I. IP core level test 16 II. SOC level test 19 1.5.4 SOC Verification 19 1.6 Motivation 20 1.7 Work Presented in the Thesis 21 1.8 Thesis Outline 21 1.8 Conclusions 22 2. Open Core Based SOC Design Methodology 23 2.1 Platform Based SOC Design 24 2.2 Open Core Based SOC Design Platform 26 2.3 The Objective behind WISHBONE 26 2.4 WISHBONE Basics 27 2.5 WISHBONE Interface Specification 28 2.5.1 Documentation for IP Cores 28 2.5.1 WISHBONE Interface Signal 29 2.6. Wishbone Interconnections 32 2.6.1 Point-to-Point Interconnection 32 2.6.2 Data Flow Interconnection 33 2.6.3 Share Bus Interconnection 33 2.6.4 Cross Bar Switch Interconnection 34 2.7 WISHBONE Bus Cycle 34 2.7.1 Handshaking Protocol 34 2.7.2 Single Read/ Write Cycle 35 2.7.3 Block Read/ Write Cycle 36 2.7.4 Read-Modify-Write (RMW) Cycle 37 2.8 Data Organization and Customized Tag 39 2.9 WISHBONE SOC Bus Comparison with AMBA and CoreConnect 39 2.10 Conclusions 41 3.
Load more

Recommended publications
  • IOTA: Detecting Erroneous I/O Behavior Via I/O Transaction Auditing
    Appears in the First Workshop on Compiler and Architectural Techniques for Application Reliability and Security (CATARS) In Conjunction with the 2008 International Conference on Dependable Systems and Networks (DSN 2008) Anchorage, Alaska, June 2008 IOTA: Detecting Erroneous I/O Behavior via I/O Transaction Auditing Albert Meixner and Daniel J. Sorin Duke University [email protected], [email protected] Abstract nosed, the system could suggest that the user or system The correctness of the I/O system—and thus the administrator replace this device. If a driver bug is diag- nosed, the bug can be reported and the driver can be correctness of the computer—can be compromised by restarted (which is often sufficient). If a security breach hardware faults, driver bugs, and security breaches in is diagnosed, the system can shutdown the driver under downloaded device drivers. To detect erroneous I/O suspicion and alert the user. In this work, we focus on behavior, we have developed I/O Transaction Auditing error detection, rather than diagnosis and recovery. (IOTA), which checks the high-level behavior of I/O Our error detection mechanism, I/O Transaction transactions. In an IOTA-protected system, the operat- Auditing (IOTA), uses end-to-end checking [13] of I/O ing system creates a signature of the I/O transactions it transactions. We define a transaction as a high-level, expects to occur and every I/O device computes a signa- semantically atomic I/O operation, such as sending an ture of the transactions it actually performs. By compar- Ethernet frame. A transaction represents the basic I/O ing these signatures, IOTA can discover erroneous operation for higher level OS services such as the file behavior in both the hardware and the software respon- system or network stack.
    [Show full text]
  • DESIGN of WISHBONE INTERFACED I2CMASTER CORE CONTROLLER USING VERILOG Ramesh Babu Dasara1, Y
    DESIGN OF WISHBONE INTERFACED I2CMASTER CORE CONTROLLER USING VERILOG Ramesh Babu Dasara1, Y. Chandra Sekhar Reddy2 1Pursuing M.tech, 2Assistant Professor, from Nalanda Institute of Engineering and Technology (NIET), Siddharth Nagar, Kantepudi village, Sattenepalli Mandal, Guntur Dist.,A.P. (India) ABSTRACT In this paper we are implementing one of the serial communication protocol called Inter integrated circuit (I2C) master controller. The protocol is made of set of standards with the master and slave configuration to allow data transfer. The I2C master with wishbone controller is implemented in Verilog HDL. The modules are synthesized in Xilinx 13.2i. Then simulated to observe the operation of the Master controller and wishbone controller which performs high speed data transfer in presence of master or slave. This yields higher speed data transfer over the network. Keywords: Master,Wishbone, SDA,SCK,SLAVE I. INTRODUCTION In electronic world to make communication between any two digital hardware devices needs serial communication standards. There are several communication standards are RS232, RS435, and SPI to make high speed and low speed data transfer. To implement protocols actually we require more number of pin connections, whereas the size of IC gradually decreasing so we need a protocol that can have minimum number of pin connections. The protocols existed earlier are SPI, MOCROWIRE and USB needs point to point connection such that needs multiplexing of data and address. The proposed protocol requires only two lines two communicate with nay number of devices while other needs more number of pin connections. The I2c is best suited for medium range communication between the circuit boards within the equipment.
    [Show full text]
  • Open Borders for System-On-A-Chip Buses: a Wire Format for Connecting Large Physics Controls
    PHYSICAL REVIEW SPECIAL TOPICS - ACCELERATORS AND BEAMS 15, 082801 (2012) Open borders for system-on-a-chip buses: A wire format for connecting large physics controls M. Kreider,1,2 R. Ba¨r,1 D. Beck,1 W. Terpstra,1 J. Davies,2 V. Grout,2 J. Lewis,3 J. Serrano,3 and T. Wlostowski3 1GSI Helmholtz Centre for Heavy Ion Research, Darmstadt, Germany 2Glyndwˆ r University, Wrexham, United Kingdom 3CERN, Geneva, Switzerland (Received 27 January 2012; published 23 August 2012) System-on-a-chip (SoC) bus systems are typically confined on-chip and rely on higher level compo- nents to communicate with the outside world. The idea behind the EtherBone (EB) protocol is to extend the reach of the SoC bus to remote field-programmable gate arrays or processors. The EtherBone core implementation connects a Wishbone (WB) Ver. 4 Bus via a Gigabit Ethernet based network link to remote peripheral devices. EB acts as a transparent interconnect module towards attached WB Bus devices. EB was developed in the scope of the WhiteRabbit Timing Project at CERN and GSI/FAIR. WhiteRabbit will make use of EB as a means to issue commands to its timing nodes and control connected accelerator hardware. DOI: 10.1103/PhysRevSTAB.15.082801 PACS numbers: 84.40.Ua, 29.20.Àc, 07.05.Àt systems hosted inside a field-programmable gate array I. PURPOSE AND ENVIRONMENT (FPGA). EtherBone was named after these underlying This article builds on the paper by the title ‘‘EtherBone—A technologies, Ethernet and Wishbone. However, EB re- network Layer for the Wishbone SoC Bus’’ in the sides in the Open Systems Interconnection session layer ICALEPCS 2011 conference proceedings and aims to pro- (OSI layer 5) and does not depend on a specific choice of vide details on design choices and performance analysis for lower layer protocols in implementation.
    [Show full text]
  • UVM Based Reusable Verification IP for Wishbone Compliant SPI Master
    UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core Lakhan Shiva Kamireddy∗, Lakhan Saiteja Ky ∗VLSI CAD Research Group, Department of Electrical and Computer Engineering, University of Colorado Boulder, CO 80303, USA, Email: [email protected] yDepartment of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur West Bengal 721302, India, Email: [email protected] Abstract—The System on Chip design industry relies heavily ming, coverage analysis, constrained randomization and as- on functional verification to ensure that the designs are bug- sertion based VIP. A methodological approach for verification free. As design engineers are coming up with increasingly dense increases the efficiency and reduces the verification effort. In chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we use UVM, a System Verilog based methodology this paper, we present verification of a wishbone compliant for testing an SPI master core that is wishbone compliant. Serial Peripheral Interface (SPI) Master core using a System The paper is organized into the following sections: Section Verilog based standard verification methodology, the Universal II introduces the key features of SV and UVM environment. Verification Methodology (UVM). By making use of UVM factory In Section-III, we introduce the SPI Master IP core for pattern with parameterized classes, we have developed a robust and reusable verification IP. SPI is a full duplex communication which the UVM framework is developed. Section-IV presents protocol used to interface components most likely in embedded our approach towards the development of UVM based VIP. systems. We have verified an SPI Master IP core design that Simulation results with snapshots and a critical discussion of is wishbone compliant and compatible with SPI protocol and the limitations of the design are presented in Section-V.
    [Show full text]
  • Wishbone Bus Architecture – a Survey and Comparison
    International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012 WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON Mohandeep Sharma 1 and Dilip Kumar 2 1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India [email protected] 2ACS - Division, Center for Development of Advanced Computing, Mohali, India [email protected] ABSTRACT The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. KEYWORDS SoC buses, WISHBONE Bus, WISHBONE Interface 1. INTRODUCTION The introduction and advancement of multimillion-gate chips technology with new levels of integration in the form of the system-on-chip (SoC) design has brought a revolution in the modern electronics industry. With the evolution of shrinking process technologies and increasing design sizes [1], manufacturers are integrating increasing numbers of components on a chip.
    [Show full text]
  • Copyright by Iat Pui Chan Master of Science in Engineering December 2009
    Copyright by Iat Pui Chan Master of Science in Engineering December 2009 The Report Committee for Iat Pui Chan Certifies that this is the approved version of the following report: USB 2.0 ULPI Design APPROVED BY SUPERVISING COMMITTEE: Supervisor: Jacob Abraham Mark McDermott USB2.0 ULPI Design by Iat Pui Chan, BSEE Report Presented to the Faculty of the Graduate School of The University of Texas at Austin in Partial Fulfillment of the Requirements for the Degree of Master of Science in Engineering The University of Texas at Austin December 2009 Abstract USB2.0 ULPI Design Iat Pui Chan, MSE The University of Texas at Austin, Fall 2009 Supervisor: Jacob Abraham This report outlines an implementation of an USB 2.0 ULPI LINK design. Chapter 1 presents an overview of the design and hardware required in the project. Chapter 2 presents how the design functions in an USB system. Chapter 3 describes the hardware implementation. Simulation result and synthesis result are shown in Chapter 4 and 5. iv Table of Contents List of Tables ........................................................................................................ vii List of Figures...................................................................................................... viii List of Figures...................................................................................................... viii Chapter 1: Introduction...........................................................................................1 1.1 System Overview......................................................................................1
    [Show full text]
  • Machxo3d Device Family Data Sheet
    MachXO3D Device Family Data Sheet FPGA-DS-02026-1.0 November 2019 MachXO3D Device Family Data Sheet Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02026-1.0 MachXO3D Device Family
    [Show full text]
  • Design and Verification Point-To-Point Architecture of WISHBONE Bus for System-On-Chip
    International Journal of Emerging Engineering Research and Technology Volume 2, Issue 2, May 2014, PP 155-159 Design and Verification Point-to-Point Architecture of WISHBONE Bus for System-on-Chip Chandrala Brijesh A.1, Mahesh T. Kolte2 1Department of electronics and telecommunication, MIT College of Engineering, Pune, India 2Department of electronics and telecommunication, MIT College of Engineering, Pune, India Abstract: SOC design is an integration of multi million transistors in a single chip for time to market and reducing the cost of the design. This paper presents point-to-point Architecture of WISHBONE bus. Main aim of the WISHBONE bus Architectures are to transfer the data from master to slave in different application without redesign of IP core. And that one will increase the productivity with reduction in design time. Standard interface bus protocol should do the plug and play. Keywords: SOC, WISHBONE, Point-to-Point, Shared Bus interconnection, Data Flow interface architecture, Crossbar switch interconnection. 1. INTRODUCTION cores together. With the use of standard interconnection scheme, the cores may be Recent advancement in technology allows integrated more easily and quickly by the end integration of logic functions of multimillion user. This specification may be used for firm transistors into a single chip. To keep pace with core or hard core and soft core IP. Since hard the levels of integration, design engineers have cores and firm are generally conceived as soft developed new methodologies and techniques to cores. manage the increased complexity in these large chips [1]. System-on-Chip (SOC) design is The evolution of shrinking process technologies proposed as an extended methodology to this and increasing design sizes [3][4] has problem where intellectual property (IP) cores of encouraged the manufacturers to undertake and embedded processors, interface blocks, analog do this kind of multiple component integration blocks and memory blocks are combined on a on a single chip.
    [Show full text]
  • Design and Verification of Serial Peripheral Interface Master Core Using Universal Verification Methodology
    International Journal of Computer Sciences and Engineering Open Access Research Paper Vol.-7, Special Issue-14, May 2019 E-ISSN: 2347-2693 Design and Verification of Serial Peripheral Interface Master Core Using Universal Verification Methodology Punith Kumar M B1*, Sreekantesha H N 2 1,2Deparment of ECE, PESCE, Mandya, India Corresponding Author: [email protected] DOI: https://doi.org/10.26438/ijcse/v7si14.711 | Available online at: www.ijcseonline.org Abstract--In today’s world, number of communication protocols for both long and short distance communication purpose, long distance protocols is USB (Universal Serial Bus), ETHERNET, PCI-EXPRESS. SPI (Serial Peripheral interface) and I2C are used for short distance communication protocols. SPI is one of the commonly used bus protocol for connecting peripheral devices to microprocessor .SPI is full duplex, high speed an synchronous bus protocol used for on-board or intra-chip communication In this project the configurable architecture of SPI Protocol with Wishbone Interface has been designed .The main advantage of this design is it overcomes the weaknesses of traditional SPI Bus protocol. As the complexity of the circuit is numerous so there is need of verification methodology to quench the product failure. This project emphasizes on verification of SPI master core verification using Universal Verification Methodology. Keywords—SPI, Wishbone, UVM, SystemVerilog. UVM is a reusable SystemVerilog based on Verification I. INTRODUCTION environment. The development of advanced integrated circuits not only Objective of this work is: increased the complexity of IC design but also IC verification Design Serial Peripheral Interface (SPI) protocol equally challenging. Around 70% spend on verification and using Verilog.
    [Show full text]
  • Wishbone Soc Reference Design for EFM-02
    Wishbone SoC Reference Design for EFM-02 The efm02_soc reference design demonstrates, how to connect FPGA IP cores like peripheral modules and memory to a host PC via the on-board Cypress FX-3 super-speed USB3.0 controller. It uses the CESYS UDK3 that comes with the EFM02 module. It is ideally suited as a starting point for user designs. The host software can read and write all functional blocks of the reference design (i.e. DDR2 SDRAM, Flash memory or General Purpose IO ports), by calling the read and write functions of the API. The referenced addresses are embedded in the UDK3 protocol, transferred serial over the USB (Universal Serial Bus) and converted into Wishbone bus-cycles. This way, the host-software can access registers or memory locations in the FPGA by addressing them. You can easily expand the efm02_soc design by adding your own blocks to the Wishbone bus or modifying existing ones. The reference design comes in VHDL source code. Depending on the target device (SLX45 or SLX150), the Xilinx(tm) ISE Webpack or ISE Design Suite can be used to generate FPGA bitfiles. UG100 (v1.1) April 07, 2014 www.cesys.com 1 Features Features The efm02_soc reference design contains the follwing basic elements: • A clock manager to generate independent clocks for the FX-3 GPIF interface and the Wishbone bus with its peripheral modules. • Wishbone SoC interconnect Architecture, 32 Bit data bus • FX-3 GPIF-II interface, Wishbone busmaster • DDR2 SDRAM interface based on Xilinx(tm) MIG Memory Interface Generator with a Wishbone wrapper.
    [Show full text]
  • WISHBONE System-On-Chip (Soc) Interconnection Architecture for Portable IP Cores
    Specification for the: WISHBONE System-On-Chip (SoC) Interconnection Architecture for Portable IP Cores Revision: B.1 Preliminary Silicore Corporation 6310 Butterworth Lane – Corcoran, MN 55340 TEL: (763) 478-3567 FAX: (763) 478-3568 www.silicore.net Electronic DeDeesignsign Sensors • IP Cores This Page is Intentionally Blank WISHBONE SoC Architecture Specification, Revision B 2 Stewardship Stewardship for this specification is maintained by Silicore Corporation. Questions, comments and suggestions about this document are welcome and should be directed to: Wade D. Peterson, Silicore Corporation 6310 Butterworth Lane – Corcoran, MN 55340 TEL: (763) 478-3567; FAX: (763) 478-3568 E-MAIL: [email protected] URL: www.silicore.net Silicore Corporation maintains this document as a service to its customers and to the IP core in- dustry as a whole. The intent of this specification is to improve the quality of Silicore products, as well as to foster cooperation among the users and suppliers of IP cores. Copyright & Trademark Release / Royalty Release / Patent Notice Notice is hereby given that this document is not copyrighted, and is in the public domain. It may be freely copied and distributed by any means. The term WISHBONE and the WISHBONE compatible logo are not trademark protected. The WISHBONE logo may be freely used under the compatibility conditions stated elsewhere in this document. This specification may be used for the design and production of system-on-chip (SoC) compo- nents without royalty or other financial obligation to Silicore Corporation. The author(s) of this specification are not aware that the information contained herein, nor of products designed to the specification, cause infringement on the patent, copyright, trademark or trade secret rights of others.
    [Show full text]
  • Modular, Configurable Bus Architecture for Ease of IP Reuse on System on Chip and ASIC Devices
    Portland State University PDXScholar Dissertations and Theses Dissertations and Theses 1-1-2010 Modular, Configurable Bus Architecture for Ease of IP Reuse on System on Chip and ASIC Devices Naveendran Balasingam Portland State University Follow this and additional works at: https://pdxscholar.library.pdx.edu/open_access_etds Let us know how access to this document benefits ou.y Recommended Citation Balasingam, Naveendran, "Modular, Configurable Bus Architecture for Ease of IP Reuse on System on Chip and ASIC Devices" (2010). Dissertations and Theses. Paper 163. https://doi.org/10.15760/etd.163 This Thesis is brought to you for free and open access. It has been accepted for inclusion in Dissertations and Theses by an authorized administrator of PDXScholar. Please contact us if we can make this document more accessible: [email protected]. Modular, Configurable Bus Architecture Targeted for Ease of IP Reuse on System on Chip and ASIC Devices by Naveendran Balasingam A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Computer Engineering Thesis Committee: Xiaoyu Song, Chair Douglas V. Hall Jingke Li Portland State University 2010 i Abstract Integrated Circuit (IC) designs are increasingly moving towards Intellectual Property (IP) reuse for various targeted products and market segments. Therefore, there is a need to share and synergize internal bus architectures to enable the reuse of IP blocks for various ASIC and SoC applications. Due to the different market segments of various ASICs and SoCs, design teams and architects have opted to use customized internal bus architectures to suit the respective targeted features for their market segments.
    [Show full text]