DS1286 Watchdog Timekeeper

DS1286 DS1286 Watchdog Timekeeper FEATURES PIN ASSIGNMENT • Keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and INTA 1 28 VCC years; valid leap year compensation up to 2100 NC 2 27 WE • Watchdog timer restarts an out–of–control processor NC 3 26 INTB(INTB) • Alarm function schedules real time–related activities NC 4 25 NC A5 5 24 NC • Embedded lithium energy cell maintains time, watch- A4 SQW dog, user RAM, and alarm information 6 23 A3 7 22 OE • Programmable interrupts and square wave outputs A2 8 21 NC maintain 28–pin JEDEC footprint A1 9 20 CE • All registers are individually addressable via the ad- A0 10 19 DQ7 dress and data bus DQ0 11 18 DQ6 • Accuracy is better than ±1 minute/month at 25°C DQ1 12 17 DQ5 13 16 DQ4 • Greater than 10 years of timekeeping in the absence DQ2 GND 14 15 DQ3 of VCC • 28–PIN ENCAPSULATED PACKAGE 50 bytes of user NV RAM (720 MIL FLUSH) PIN DESCRIPTION INTA – Interrupt Output A (open drain) INTB(INTB) – Interrupt Output B (open drain) A0–A5 – Address Inputs DQ0-DQ7 – Data Input/Output CE – Chip Enable OE – Output Enable WE – Write Enable VCC – +5 Volts GND – Ground NC – No Connection SQW – Square Wave Output DESCRIPTION The DS1286 Watchdog Timekeeper is a self–contained RAM. Data is maintained in the Watchdog Timekeeper real time clock, alarm, watchdog timer, and interval tim- by intelligent control circuitry which detects the status of er in a 28–pin JEDEC DIP package. The DS1286 con- VCC and write protects memory when VCC is out of tol- tains an embedded lithium energy source and a quartz erance. The lithium energy source can maintain data crystal which eliminates the need for any external cir- and real time for over ten years in the absence of VCC. cuitry. Data contained within 64 eight–bit registers can Watchdog Timekeeper information includes hun- be read or written in the same manner as bytewide static dredths of seconds, seconds, minutes, hours, day, date, ECopyright 1997 by Dallas Semiconductor Corporation. 033197 1/12 All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. DS1286 month, and year. The date at the end of the month is au- support circuitry. The DS1286 constantly monitors VCC. tomatically adjusted for months with less than 31 days, Should the supply voltage decay, the Watchdog Time- including correction for leap year. The Watchdog Time- keeper will automatically write protect itself and all in- keeper operates in either 24 hour or 12 hour format with puts to the registers become “Don’t Care”. Both INTA an AM/PM indicator. The watchdog timer provides and INTB(INTB) are open drain outputs. The two inter- alarm windows and interval timing between 0.01 sec- rupts and the internal clock continue to run regardless of onds and 99.99 seconds. The real time alarm provides the level of VCC. However, it is important to insure that for preset times of up to one week. the pull–up resistors used with the interrupt pins are never pulled up to a value which is greater than VCC + 0.3V. As VCC falls below approximately 3.0 volts, a OPERATION – READ REGISTERS power switching circuit turns the lithium energy source The DS1286 executes a read cycle whenever WE on to maintain the clock, and timer data functionality. It (Write Enable) is inactive (High) and CE (Chip Enable) is also required to insure that during this time (battery and OE (Output Enable) are active (Low). The unique backup mode), the voltage present at INTA and address specified by the six address inputs (A0–A5) de- INTB(INTB) does never exceed 3.0V. At all times the fines which of the 64 registers is to be accessed. Valid current on each should not exceed +2.1 mA or –1.0 mA. data will be available to the eight data output drivers However, if the active high mode is selected for within tACC (Access Time) after the last address input INTB(INTB), this pin will only go high in the presence of signal is stable, providing that CE and OE access times VCC. During power–up, when VCC rises above approxi- are also satisfied. If OE and CE access times are not mately 3.0 volts, the power switching circuit connects satisfied, then data access must be measured from the external VCC and disconnects the internal lithium ener- latter occurring signal (CE or OE) and the limiting pa- gy source. Normal operation can resume after VCC ex- rameter is either tCO for CE or tOE for OE rather than ad- ceeds 4.5 volts for a period of 150 ms. dress access. WATCHDOG TIMEKEEPER REGISTERS OPERATION – WRITE REGISTERS The Watchdog Timekeeper has 64 registers which are The DS1286 is in the write mode whenever the WE eight bits wide that contain all of the Timekeeping, (Write Enable) and CE (Chip Enable) signals are in the Alarm, Watchdog, Control, and Data information. The active (Low) state after the address inputs are stable. Clock, Calendar, Alarm, and Watchdog registers are The latter occurring falling edge of CE or WE will deter- memory locations which contain external (user–acces- mine the start of the write cycle. The write cycle is termi- sible) and internal copies of the data. The external co- nated by the earlier rising edge of CE or WE. All address pies are independent of internal functions except that inputs must be kept valid throughout the write cycle. WE they are updated periodically by the simultaneous trans- must return to the high state for a minimum recovery fer of the incremented internal copy (see Figure 1). The state (tWR) before another cycle can be initiated. Data Command Register bits are affected by both internal must be valid on the data bus with sufficient Data Set Up and external functions. This register will be discussed (tDS) and Data Hold Time (tDH) with respect to the earlier later. The 50 bytes of RAM registers can only be ac- rising edge of CE or WE. The OE control signal should cessed from the external address and data bus. Regis- be kept inactive (High) during write cycles to avoid bus ters 0, 1, 2, 4, 6, 8, 9, and A contain time of day and date contention. However, if the output bus has been en- information (see Figure 2). Time of Day information is abled (CE and OE active), then WE will disable the out- stored in BCD. Registers 3, 5, and 7 contain the Time of puts in tODW from its falling edge. Day Alarm information. Time of Day Alarm information is stored in BCD. Register B is the Command Register DATA RETENTION and information in this register is binary. Registers C The Watchdog Timekeeper provides full functional ca- and D are the Watchdog Alarm registers and information which is stored in these two registers is in BCD. pability when VCC is greater than 4.5 volts and write protects the register contents at 4.25 volts typical. Data is Registers E through 3F are user bytes and can be used to contain data at the user’s discretion. maintained in the absence of VCC without any additional 033197 2/12 BLOCK DIAGRAM OSCILLATOR & JITTER JITTER PRESCALER GENERATOR GENERATOR VCC (VBAT) (X1) Figure1 QUARTZ DIVIDE OSCILLATOR DIVIDE DIVIDE PF DELAY POWER CRYSTAL BY 8 BY 40.96 BY 40.96 DIVIDE BY 10 SWITCH (X2) 32.768 LKz 4096HZ DIVIDE 1024HZ BY 4 SQW INTERNAL REGISTERS EXTERNAL REGISTERS, UPDATE SECONDS THRU CLOCK, CALENDAR, YEARS AND CHECK TIME OF DAY ALARM TIME OF DAY ALARM TD INT INTA SWAP COMMAND REGISTER WD INT PINS INTB(INTB) A0-A5 ADN COUNTROL 100HZ ADDRESS DECODE 100HZ USER RAM “AVG” CE “AVG” 50 BYTES INTERNAL COUNTERS INTERNAL REGISTERS OE EXTERNAL REGISTERS EXTERNAL REGISTERS WATCHDOG ALARM HUNDREDTHS WE INTERNAL COUNTERS OF SECONDS PSUR 033197 3/12 DATA I/0 BUFFERS DS1286 DQ0-DQ7 DS1286 DS1286 WATCHDOG TIMEKEEPER REGISTERS Figure 2 ADDRESS BIT 7 BIT 0 RANGE 0 0.1 SECONDS 0.01 SECONDS 00–99 00–59 1 0 10 SECONDS SECONDS 00–59 2 010 MINUTES MINUTES 3 M10 MIN ALARM MIN ALARM 00–59 10 01–12+A/P 4 0 12/24 10 HR HOURS A/P 00–23 CLOCK, CALENDAR, TIME OF DAY ALARM 10 01–12+A/P 5 M 12/24 10 HR HR ALARM REGISTERS A/P 00–23 6 00000 DAYS 01–07 01–07 7 M 0000DAY ALARM 01–31 8 0 0 10 DATE DATE 01–12 9 EOSC ESQW 0 10MO MONTHS A 10 YEARS YEARS 00–99 COMMAND IBH PU B TE IPSW WAM TDM WAF TDF REGISTERS LO LVL C 0.1 SECONDS 0.01 SECONDS 00–99 WATCHDOG ALARM REGISTERS D 10 SECONDS SECONDS 00–99 (RETRIGGERABLE/ REPETITIVE COUNTDOWN ALARM) E USER REGISTERS 3F 033197 4/12 DS1286 TIME OF DAY REGISTERS of making sure that the write cycle has caused proper Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time of Day update is to do read verifies and re–execute the write data in BCD. Ten bits within these eight registers are not cycle if data is not correct. While the possibility of erro- used and will always read zero regardless of how they neous results from reads and write cycles has been are written. Bits 6 and 7 in the Months Register (9) are stated, it is worth noting that the probability of an incor- binary bits.

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