ERC Advanced Grant Research Proposal (Part B2)
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Operating Systems and Applications for Embedded Systems >>> Toolchains
>>> Operating Systems And Applications For Embedded Systems >>> Toolchains Name: Mariusz Naumowicz Date: 31 sierpnia 2018 [~]$ _ [1/19] >>> Plan 1. Toolchain Toolchain Main component of GNU toolchain C library Finding a toolchain 2. crosstool-NG crosstool-NG Installing Anatomy of a toolchain Information about cross-compiler Configruation Most interesting features Sysroot Other tools POSIX functions AP [~]$ _ [2/19] >>> Toolchain A toolchain is the set of tools that compiles source code into executables that can run on your target device, and includes a compiler, a linker, and run-time libraries. [1. Toolchain]$ _ [3/19] >>> Main component of GNU toolchain * Binutils: A set of binary utilities including the assembler, and the linker, ld. It is available at http://www.gnu.org/software/binutils/. * GNU Compiler Collection (GCC): These are the compilers for C and other languages which, depending on the version of GCC, include C++, Objective-C, Objective-C++, Java, Fortran, Ada, and Go. They all use a common back-end which produces assembler code which is fed to the GNU assembler. It is available at http://gcc.gnu.org/. * C library: A standardized API based on the POSIX specification which is the principle interface to the operating system kernel from applications. There are several C libraries to consider, see the following section. [1. Toolchain]$ _ [4/19] >>> C library * glibc: Available at http://www.gnu.org/software/libc. It is the standard GNU C library. It is big and, until recently, not very configurable, but it is the most complete implementation of the POSIX API. * eglibc: Available at http://www.eglibc.org/home. -
On Various Ways to Split a Floating-Point Number
On various ways to split a floating-point number Claude-Pierre Jeannerod Jean-Michel Muller Paul Zimmermann Inria, CNRS, ENS Lyon, Universit´ede Lyon, Universit´ede Lorraine France ARITH-25 June 2018 -1- Splitting a floating-point number X = ? round(x) frac(x) 0 2 First bit of x = ufp(x) (for scalings) X All products are s computed exactly 2 2 X with one FP p 2 2 k a b multiplication a + b ! 2 k + k X (Dekker product) 2 2 X Dekker product (1971) -2- Splitting a floating-point number absolute splittings (e.g., bxc), vs relative splittings (e.g., most significant bits, splitting of the significands for multiplication); In each "bin", the sum is no bit manipulations of the computed exactly binary representations (would result in less portable Matlab program in a paper by programs) ! onlyFP Zielke and Drygalla (2003), operations. analysed and improved by Rump, Ogita, and Oishi (2008), reproducible summation, by Demmel & Nguyen. -3- Notation and preliminary definitions IEEE-754 compliant FP arithmetic with radix β, precision p, and extremal exponents emin and emax; F = set of FP numbers. x 2 F can be written M x = · βe ; βp−1 p M, e 2 Z, with jMj < β and emin 6 e 6 emax, and jMj maximum under these constraints; significand of x: M · β−p+1; RN = rounding to nearest with some given tie-breaking rule (assumed to be either \to even" or \to away", as in IEEE 754-2008); -4- Notation and preliminary definitions Definition 1 (classical ulp) The unit in the last place of t 2 R is ( βblogβ jt|c−p+1 if jtj βemin , ulp(t) = > βemin−p+1 otherwise. -
Floating Point Arithmetic
Systems Architecture Lecture 14: Floating Point Arithmetic Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED). Lec 14 Systems Architecture 1 Introduction • Objective: To provide hardware support for floating point arithmetic. To understand how to represent floating point numbers in the computer and how to perform arithmetic with them. Also to learn how to use floating point arithmetic in MIPS. • Approximate arithmetic – Finite Range – Limited Precision • Topics – IEEE format for single and double precision floating point numbers – Floating point addition and multiplication – Support for floating point computation in MIPS Lec 14 Systems Architecture 2 Distribution of Floating Point Numbers e = -1 e = 0 e = 1 • 3 bit mantissa 1.00 X 2^(-1) = 1/2 1.00 X 2^0 = 1 1.00 X 2^1 = 2 1.01 X 2^(-1) = 5/8 1.01 X 2^0 = 5/4 1.01 X 2^1 = 5/2 • exponent {-1,0,1} 1.10 X 2^(-1) = 3/4 1.10 X 2^0 = 3/2 1.10 X 2^1= 3 1.11 X 2^(-1) = 7/8 1.11 X 2^0 = 7/4 1.11 X 2^1 = 7/2 0 1 2 3 Lec 14 Systems Architecture 3 Floating Point • An IEEE floating point representation consists of – A Sign Bit (no surprise) – An Exponent (“times 2 to the what?”) – Mantissa (“Significand”), which is assumed to be 1.xxxxx (thus, one bit of the mantissa is implied as 1) – This is called a normalized representation • So a mantissa = 0 really is interpreted to be 1.0, and a mantissa of all 1111 is interpreted to be 1.1111 • Special cases are used to represent denormalized mantissas (true mantissa = 0), NaN, etc., as will be discussed. -
Author Guidelines for 8
ACCELERATED CODE GENERATOR FOR PROCESSING OCEAN COLOR REMOTE SENSING DATA ON GPU Jae-Moo Heo1, Gangwon Jo2, Hee-Jeong Han1, Hyun Yang 1 1Korea Ocean Satellite Center, Korea Institute of Ocean Science and Technology, Pusan, South Korea 2Seoul National University and ManyCoreSoft Co., Ltd., Seoul, South Korea ABSTRACT GOCI-II ground system in July 2017 and decided to process As the satellite data gradually increases, the processing time algorithms on the Graphics Processing Unit (GPU) in order of the algorithm for remote sensing also increases. It is now to process large amounts of data. essential to make efforts to improve the processing Nowadays, we can take advantage of computation devices performance in various accelerators such as Graphics of various architectures: Many Integrated Core (i.e., Intel Processing Unit (GPU). However, it is very difficult to use Xeon Phi), GPU, and Filed Programmable Gate Array programming models that make programs to run on (FPGA). These accelerators are constantly improving and accelerators. Especially for scientists, easy programming changing. And, parallel programming models that are and performance are often more important than providing compatible with these various accelerators are being many optimization functions and directives. To meet these developed at the same time. However, algorithm source requirements, we developed the accelerated code generator codes have been generally improved for several years or based on Open Computing Language (OpenCL) for several decades and it is not easy to develop a large amount processing ocean color remote sensing data. We easily of these source codes into the existing parallel programming applied our generator to atmospheric correction program for models. -
Floating Point Square Root Under HUB Format
View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Repositorio Institucional Universidad de Málaga Floating Point Square Root under HUB Format Julio Villalba-Moreno Javier Hormigo Dept. of Computer Architecture Dept. of Computer Architecture University of Malaga University of Malaga Malaga, SPAIN Malaga, SPAIN [email protected] [email protected] Abstract—Unit-Biased (HUB) is an emerging format based on maintaining the same accuracy, the area cost and delay of FIR shifting the representation line of the binary numbers by half filter implementations has been drastically reduced in [3], and unit in the last place. The HUB format is specially relevant similarly for the QR decomposition in [4]. for computers where rounding to nearest is required because it is performed simply by truncation. From a hardware point In [5] the authors carry out an analysis of using HUB format of view, the circuits implementing this representation save both for floating point adders, multipliers and converters from a area and time since rounding does not involve any carry propa- quantitative point of view. Experimental studies demonstrate gation. Designs to perform the four basic operations have been that HUB format keeps the same accuracy as conventional proposed under HUB format recently. Nevertheless, the square format for the aforementioned units, simultaneously improving root operation has not been confronted yet. In this paper we present an architecture to carry out the square root operation area, speed and power consumption (14% speed-up, 38% less under HUB format for floating point numbers. The results of area and 26% less power for single precision floating point this work keep supporting the fact that the HUB representation adder, 17% speed-up, 22% less area and slightly less power for involves simpler hardware than its conventional counterpart for the floating point multiplier). -
AC Library for Emulating Low-Precision Arithmetic Fasi
CPFloat: A C library for emulating low-precision arithmetic Fasi, Massimiliano and Mikaitis, Mantas 2020 MIMS EPrint: 2020.22 Manchester Institute for Mathematical Sciences School of Mathematics The University of Manchester Reports available from: http://eprints.maths.manchester.ac.uk/ And by contacting: The MIMS Secretary School of Mathematics The University of Manchester Manchester, M13 9PL, UK ISSN 1749-9097 CPFloat: A C library for emulating low-precision arithmetic∗ Massimiliano Fasi y Mantas Mikaitis z Abstract Low-precision floating-point arithmetic can be simulated via software by executing each arith- metic operation in hardware and rounding the result to the desired number of significant bits. For IEEE-compliant formats, rounding requires only standard mathematical library functions, but handling subnormals, underflow, and overflow demands special attention, and numerical errors can cause mathematically correct formulae to behave incorrectly in finite arithmetic. Moreover, the ensuing algorithms are not necessarily efficient, as the library functions these techniques build upon are typically designed to handle a broad range of cases and may not be optimized for the specific needs of rounding algorithms. CPFloat is a C library that of- fers efficient routines for rounding arrays of binary32 and binary64 numbers to lower precision. The software exploits the bit level representation of the underlying formats and performs only low-level bit manipulation and integer arithmetic, without relying on costly library calls. In numerical experiments the new techniques bring a considerable speedup (typically one order of magnitude or more) over existing alternatives in C, C++, and MATLAB. To the best of our knowledge, CPFloat is currently the most efficient and complete library for experimenting with custom low-precision floating-point arithmetic available in any language. -
N2429 V 1 Function Failure Annotation
ISO/IEC JTC 1/SC 22/WG14 N2429 September 23, 2019 v 1 Function failure annotation Niall Douglas Jens Gustedt ned Productions Ltd, Ireland INRIA & ICube, Université de Strasbourg, France We have been seeing an evolution in proposals for the best syntax for describing how to mark how a function fails, such that compilers and linkers can much better optimise function calls than at present. These papers were spurred by [WG21 P0709] Zero-overhead deterministic exceptions, which proposes deterministic exception handling for C++, whose implementation could be very compatible with C code. P0709 resulted in [WG21 P1095] Zero overhead deterministic failure – A unified mecha- nism for C and C++ which proposed a C syntax and exception-like mechanism for supporting C++ deterministic exceptions. That was responded to by [WG14 N2361] Out-of-band bit for exceptional return and errno replacement which proposed an even wider reform, whereby the most popular idioms for function failure in C code would each gain direct calling convention support in the compiler. This paper synthesises all of the proposals above into common proposal, and does not duplicate some of the detail in the above papers for brevity and clarity. It hews closely to what [WG14 N2361] proposes, but with different syntax, and in addition it shows how the corresponding C++ features can be constructed on top of it, without loosing call compatibility with C. Contents 1 Introduction 2 1.1 Differences between WG14 N2361 and WG21 P1095 . .3 2 Proposed Design 4 2.1 errno-related function failure editions . .5 2.2 When to choose which edition . -
Arm C/C++ Compiler Developer and Reference Guide Document ID: 101458 21.1 01 En Version 21.1
Arm C/C++ Compiler Version 21.1 Developer and Reference Guide Non-Confidential Issue 01 Copyright © 2018–2021 Arm Limited (or its affiliates). 101458_21.1_01_en All rights reserved. Arm C/C++ Compiler Developer and Reference Guide Document ID: 101458_21.1_01_en Version 21.1 Arm C/C++ Compiler Developer and Reference Guide Copyright © 2018–2021 Arm Limited (or its affiliates). All rights reserved. Release information Document history Issue Date Confidentiality Change 1900-00 2 November 2018 Non-Confidential Document release for Arm C/C++ Compiler version 19.0 1910-00 8 March 2019 Non-Confidential Update for Arm C/C++ Compiler version 19.1 1920-00 7 June 2019 Non-Confidential Update for Arm C/C++ Compiler version 19.2 1930-00 30 August 2019 Non-Confidential Update for Arm C/C++ Compiler version 19.3 2000-00 29 November 2019 Non-Confidential Update for Arm C/C++ Compiler version 20.0 2010-00 23 April 2020 Non-Confidential Update for Arm C/C++ Compiler version 20.1 2010-01 23 April 2020 Non-Confidential Documentation update 1 for Arm C/C++ Compiler version 20.1 2020-00 25 June 2020 Non-Confidential Update for Arm C/C++ Compiler version 20.2 2030-00 4 September 2020 Non-Confidential Update for Arm C/C++ Compiler version 20.3 2030-01 16 October 2020 Non-Confidential Documentation update 1 for Arm C/C++ Compiler version 20.3 2100-00 30 March 2021 Non-Confidential Update for Arm C/C++ Compiler version 21.0 2110-00 24 August 2021 Non-Confidential Update for Arm C/C++ Compiler version 21.1 2110-01 26 August 2021 Non-Confidential Documentation update 1 for Arm C/C++ Compiler version 21.1 Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. -
Numerical Computation Guide
Numerical Computation Guide A Sun Microsystems, Inc. Business 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. Part No.: 801-7639-10 Revision A, August 1994 1994 Sun Microsystems, Inc. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. All rights reserved. This product and related documentation are protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® and Berkeley 4.3 BSD systems, licensed from UNIX System Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and the University of California, respectively. Third-party font software in this product is protected by copyright and licensed from Sun’s font suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, the Sun logo, Sun Microsystems, Sun Microsystems Computer Corporation, Solaris, are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and certain other countries. UNIX is a registered trademark of Novell, Inc., in the United States and other countries; X/Open Company, Ltd., is the exclusive licensor of such trademark. OPEN LOOK® is a registered trademark of Novell, Inc. -
Cab Programming Manual
Product Marking 1 1 A+ series Mach 4 PX Print Module XD4 Programming Manual J-Script and abc for cab printers Edition 7.0 cab Produkttechnik GmbH & Co KG 1 2 2 JScript - the programming language for cab printers. The usage of all described functions in this manual requires firmware version 3.17 or higher. This is a generic manual which describes the commands for different printer models,which means that it may contain descriptions or explanations of features which are not available on every printer model. cab Produkttechnik GmbH & Co KG 2 3 3 cab Programming Manual valid for following printer types: A+ -Series TM XD4 -Series TM Mach 4 TM PX -Print Module TM and all printing systems based on the cab „X2“ board copyright © cab Produkttechnik GmbH & Co KG all rights reserved No parts of this manual may be copied, rewritten or used for anything else than for original cab printers. This interdicts the usage of the manual for OEM products unless you have a written permission. The cab printers command language is owned and copyrighted by cab Produkttechnik GmbH & Co KG cab Produkttechnik GmbH & Co KG Wilhelm Schickard Str. 14 76131 Karlsruhe / Germany Tel: +49 - 721-6626-0 Fax:+49 - 721-6626-239 Email: [email protected] http://www.cabgmbh.com All registered trademarks or product names are trademarks of their respectives companies SwissTM is registered Trademark of Bitstream Inc. cab Produkttechnik GmbH & Co KG 3 4 4 Table of contents copyright © cab Produkttechnik GmbH & Co KG.................................................................................. -
A Study of the Floating-Point Tuning Behaviour on the N-Body Problem
A Study of the Floating-Point Tuning Behaviour on the N-body Problem Dorra Ben Khalifa1 and Matthieu Martel1;2 1 University of Perpignan, LAMPS laboratory, 52 Av. P. Alduy, Perpignan, France 2 Numalis, Cap Omega, Rond-point Benjamin Franklin, Montpellier, France fdorra.ben-khalifa, [email protected] Abstract. In this article, we apply a new methodology for precision tun- ing to the N-body problem. Our technique, implemented in a tool named POP, makes it possible to optimize the numerical data types of a pro- gram performing floating-point computations by taking into account the requested accuracy on the results. POP reduces the problem of finding the minimal number of bits needed for each variable of the program to an Integer Linear Problem (ILP) which can be optimally solved in one shot by a classical linear programming solver. The POP tool has been suc- cessfully tested on programs implementing several numerical algorithms coming from mathematical libraries and other applicative domains such as IoT. In this work, we demonstrate the efficiency of POP to tune the classical gravitational N-body problem by considering five bodies that interact under gravitational force from one another, subject to Newton's laws of motion. Results on the effect of POP in term of mixed-precision tuning of the N-body example are discussed. Keywords: Computer arithmetic, precision tuning, integer linear prob- lems, N-body problem, numerical accuracy. 1 Introduction Reducing the precision of floating-point data, also called precision tuning, pro- vides for many practitioners in High-Performance Computing (HPC) and related fields an opportunity for exploring trade-offs in accuracy and performance [16]. -
Customizing Floating-Point Units for Fpgas: Area-Performance-Standard
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs Pedro Echeverría *, Marisa López-Vallejo Departamento de Ingeniería Electrónica, Universidad Politécnica de Madrid, Spain ABSTRACT The high integration density of current nanometer technologies allows the implementation of complex floating-point applications in a single FPGA. In this work the intrinsic complexity of floating-point oper ators is addressed targeting configurable devices and making design decisions providing the most suit Keywords: able performance-standard compliance trade-offs. A set of floating-point libraries composed of adder/ Floating-point arithmetic subtracter, multiplier, divisor, square root, exponential, logarithm and power function are presented. FPGAs Each library has been designed taking into account special characteristics of current FPGAs, and with this Library of operators purpose we have adapted the IEEE floating-point standard (software-oriented) to a custom FPGA-ori- High performance ented format. Extended experimental results validate the design decisions made and prove the usefulness of reducing the format complexity. 1. Introduction impossible or makes the design cycle extremely long. Thus, the availability of complete and fully characterized floating-point Current deep sub-micron technologies allow manufacturing of libraries targeting FPGAs has become a must. FPGAs with extraordinary logic density and speed. The initial chal The IEEE standard for binary floating-point arithmetic was con lenges related to FPGAs programmability and large interconnection ceived to be implemented through custom VLSI units developed for capacitances (poor performance, low logic density and high power microprocessors. However, if the target hardware is an FPGA, the dissipation) have been overcome while providing attractive low internal architecture of these operators must be highly optimized cost and flexibility [1].