DOCSLIB.ORG

Implementation of a Four-Bit Adding Machine Bryanna Davison, Kristopher Cotten Santa Rosa Junior College

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Implementation of a Four-Bit Adding Machine Bryanna Davison, Kristopher Cotten Santa Rosa Junior College Implementation of a Four-bit Adding Machine Bryanna Davison, Kristopher Cotten Santa Rosa Junior College Abstract Methods Results Digital computation lies at the basis of nearly all modern pursuits of knowledge. This computation is performed utilizing only a single voltage, manipulating the voltage on or off to simulate a base two number of either a one or a zero. Numerous logic devices have sprung up to implement computations in this digital space, and most modern computers perform their computations through the use of addition and nothing else. The half adder, and consequently the full adder, make everything in the Central Processing Unit possible. Their logic may be • A logical AND gate with output • An OR Gate with its expected • The Exclusive-OR, or XOR, gate is • Users input two numbers truth table that demonstrates extended through the use of a carry out signal to output. similar to an OR gate. • Each number consists of four bits, also known another adder, all the way up to an arbitrary expected output from given inputs. • An OR operation could be said to be • The operation will only have an • as a byte amount of n bits. In the interest of minimizing An AND operation might be said to adding the two inputs together. output if A or B is high, not if both be Multiplying the two inputs • Input is adjusted through the use of toggle complexity the four-bit binary adding machine • If both inputs are high then the inputs are high. • The only way to ensure an output output will also produce a carry bit • XOR gates can model a linear switches. The switches simulate either a one or a was chosen to showcase these fundamentals of is by having two high inputs, or that is resolved with the use of an feedback shift register, in order to zero, for high and low voltage respectively computer processing. In order to realize binary ones. adder generate random numbers • A one or a zero must always be applied to the computation, a circuit design was first gate or results may become unpredictable approached through the use of a Simulation • The four-bit adder will compute the result of the Program with Integrated Circuit Emphasis • The Half Adder can provide the addition without any need for user interaction (SPICE). Once the SPICE was complete, a expected sum and carry for the • The result of the binary addition is displayed to working circuit was implemented with integrated addition of two numbers in binary the user in binary through an array of LEDs circuit logic gates on a solderless breadboard. • Can not account for a carry in bit from any previous operation • Combines with a second half adder Conclusion Introduction and an OR gate to form a full adder • The ability to add two four-bit binary numbers At the most fundamental level of all computing the • Possibility exists to emulate subtraction using one-bit adding circuit consists of a single half Gray Code adder. A second half adder can then be added to • The four-bit adder is a small step towards a account for the carry bit (that results from base Finite State Machine and other more complex two addition) transforming the adder into what is automata known as a full adder. The chosen implementation of the adder required two AND gates, two exclusive OR gates (XOR gate), and a single OR Acknowledgements • All of these calculations • A typical transistor adder gate. Once the first adder is complete the carry and are made possible schematic that uses Not AND Thanks to the Santa Rosa Junior College MESA the sum go on to become the inputs of the next through the use of gates, also known as NAND gates program and its director Darci Rosales for adder, continuing in this fashion until the circuit transistors • NAND gates are common in providing funding for this project and to Monica includes the requisite gates for four-bit addition. • Easily outputs digital commercial and industrial Acosta for poster planning and editing assistance. signals applications due to fewer wires • Has the advantages of being able to account for a Materials carry in bit • Carry in and out allows for the full adder to be References • Transistors strung together and calculate numbers with “n” Petzold, Charles. Code: The Hidden Language of • Integrated Circuits bits • In practice the adder will output in accordance Computer Hardware and Software. • Light Emitting Diodes with the truth table seen here, just as if the Redmond, WA: Microsoft Press, 2000. Print. • Resistors “numbers” had been added by hand • Jumper Wire • The logic diagram and truth table shown here can Malvino, Albert Paul, and Donald P. Leach. Digital • Toggle Switches also be implemented using diodes, relays, Principles and Applications. 2nd ed. • Breadboards software, or even with carefully crafted wood and • The Four-Bit Adder will actualize the addition of two New York: McGraw-Hill, 1975. Print. marbles • AC to DC transformer four bit binary numbers POSTER TEMPLATE BY: www.PosterPresentations.com.
Load more

Recommended publications
  • The Equation for the 3-Input XOR Gate Is Derived As Follows
    The equation for the 3-input XOR gate is derived as follows The last four product terms in the above derivation are the four 1-minterms in the 3-input XOR truth table. For 3 or more inputs, the XOR gate has a value of 1when there is an odd number of 1’s in the inputs, otherwise, it is a 0. Notice also that the truth tables for the 3-input XOR and XNOR gates are identical. It turns out that for an even number of inputs, XOR is the inverse of XNOR, but for an odd number of inputs, XOR is equal to XNOR. All these gates can be interconnected together to form large complex circuits which we call networks. These networks can be described graphically using circuit diagrams, with Boolean expressions or with truth tables. 3.2 Describing Logic Circuits Algebraically Any logic circuit, no matter how complex, may be completely described using the Boolean operations previously defined, because of the OR gate, AND gate, and NOT circuit are the basic building blocks of digital systems. For example consider the circuit shown in Figure 1.3(c). The circuit has three inputs, A, B, and C, and a single output, x. Utilizing the Boolean expression for each gate, we can easily determine the expression for the output. The expression for the AND gate output is written A B. This AND output is connected as an input to the OR gate along with C, another input. The OR gate operates on its inputs such that its output is the OR sum of the inputs.
    [Show full text]
  • Hardware Abstract the Logic Gates References Results Transistors Through the Years Acknowledgements
    The Practical Applications of Logic Gates in Computer Science Courses Presenters: Arash Mahmoudian, Ashley Moser Sponsored by Prof. Heda Samimi ABSTRACT THE LOGIC GATES Logic gates are binary operators used to simulate electronic gates for design of circuits virtually before building them with-real components. These gates are used as an instrumental foundation for digital computers; They help the user control a computer or similar device by controlling the decision making for the hardware. A gate takes in OR GATE AND GATE NOT GATE an input, then it produces an algorithm as to how The OR gate is a logic gate with at least two An AND gate is a consists of at least two A NOT gate, also known as an inverter, has to handle the output. This process prevents the inputs and only one output that performs what inputs and one output that performs what is just a single input with rather simple behavior. user from having to include a microprocessor for is known as logical disjunction, meaning that known as logical conjunction, meaning that A NOT gate performs what is known as logical negation, which means that if its input is true, decision this making. Six of the logic gates used the output of this gate is true when any of its the output of this gate is false if one or more of inputs are true. If all the inputs are false, the an AND gate's inputs are false. Otherwise, if then the output will be false. Likewise, are: the OR gate, AND gate, NOT gate, XOR gate, output of the gate will also be false.
    [Show full text]
  • Designing Combinational Logic Gates in Cmos
    CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1).
    [Show full text]
  • 8-Bit Adder and Subtractor with Domain Label Based on DNA Strand Displacement
    Article 8-Bit Adder and Subtractor with Domain Label Based on DNA Strand Displacement Weixuan Han 1,2 and Changjun Zhou 1,3,* 1 College of Mathematics and Computer Science, Zhejiang Normal University, Jinhua 321004, China; [email protected] 2 College of Nuclear Science and Engineering, Sanmen Institute of technicians, Sanmen 317100, China 3 Key Laboratory of Advanced Design and Intelligent Computing (Dalian University) Ministry of Education, Dalian 116622, China * Correspondence: [email protected] Academic Editor: Xiangxiang Zeng Received: 16 October 2018; Accepted: 13 November 2018; Published: 15 November 2018 Abstract: DNA strand displacement, which plays a fundamental role in DNA computing, has been widely applied to many biological computing problems, including biological logic circuits. However, there are many biological cascade logic circuits with domain labels based on DNA strand displacement that have not yet been designed. Thus, in this paper, cascade 8-bit adder/subtractor with a domain label is designed based on DNA strand displacement; domain t and domain f represent signal 1 and signal 0, respectively, instead of domain t and domain f are applied to representing signal 1 and signal 0 respectively instead of high concentration and low concentration high concentration and low concentration. Basic logic gates, an amplification gate, a fan-out gate and a reporter gate are correspondingly reconstructed as domain label gates. The simulation results of Visual DSD show the feasibility and accuracy of the logic calculation model of the adder/subtractor designed in this paper. It is a useful exploration that may expand the application of the molecular logic circuit. Keywords: DNA strand displacement; cascade; 8-bit adder/subtractor; domain label 1.
    [Show full text]
  • –Not –And –Or –Xor –Nand –Nor
    Gates Six types of gates –NOT –AND –OR –XOR –NAND –NOR 1 NOT Gate A NOT gate accepts one input signal (0 or 1) and returns the complementary (opposite) signal as output 2 AND Gate An AND gate accepts two input signals If both are 1, the output is 1; otherwise, the output is 0 3 OR Gate An OR gate accepts two input signals If both are 0, the output is 0; otherwise, the output is 1 4 XOR Gate An XOR gate accepts two input signals If both are the same, the output is 0; otherwise, the output is 1 5 XOR Gate Note the difference between the XOR gate and the OR gate; they differ only in one input situation When both input signals are 1, the OR gate produces a 1 and the XOR produces a 0 XOR is called the exclusive OR because its output is 1 if (and only if): • either one input or the other is 1, • excluding the case that they both are 6 NAND Gate The NAND (“NOT of AND”) gate accepts two input signals If both are 1, the output is 0; otherwise, the output is 1 NOR Gate The NOR (“NOT of OR”) gate accepts two inputs If both are 0, the output is 1; otherwise, the output is 0 8 AND OR XOR NAND NOR 9 Review of Gate Processing Gate Behavior NOT Inverts its single input AND Produces 1 if all input values are 1 OR Produces 0 if all input values are 0 XOR Produces 0 if both input values are the same NAND Produces 0 if all input values are 1 NOR Produces 1 if all input values are 0 10 Combinational Circuits Gates are combined into circuits by using the output of one gate as the input for another This same circuit using a Boolean expression is AB + AC 11 Combinational Circuits Three inputs require eight rows to describe all possible input combinations 12 Combinational Circuits Consider the following Boolean expression A(B + C) Does this truth table look familiar? Compare it with previous table 13.
    [Show full text]
  • Exclusive Or from Wikipedia, the Free Encyclopedia
    New features Log in / create account Article Discussion Read Edit View history Exclusive or From Wikipedia, the free encyclopedia "XOR" redirects here. For other uses, see XOR (disambiguation), XOR gate. Navigation "Either or" redirects here. For Kierkegaard's philosophical work, see Either/Or. Main page The logical operation exclusive disjunction, also called exclusive or (symbolized XOR, EOR, Contents EXOR, ⊻ or ⊕, pronounced either / ks / or /z /), is a type of logical disjunction on two Featured content operands that results in a value of true if exactly one of the operands has a value of true.[1] A Current events simple way to state this is "one or the other but not both." Random article Donate Put differently, exclusive disjunction is a logical operation on two logical values, typically the values of two propositions, that produces a value of true only in cases where the truth value of the operands differ. Interaction Contents About Wikipedia Venn diagram of Community portal 1 Truth table Recent changes 2 Equivalencies, elimination, and introduction but not is Contact Wikipedia 3 Relation to modern algebra Help 4 Exclusive “or” in natural language 5 Alternative symbols Toolbox 6 Properties 6.1 Associativity and commutativity What links here 6.2 Other properties Related changes 7 Computer science Upload file 7.1 Bitwise operation Special pages 8 See also Permanent link 9 Notes Cite this page 10 External links 4, 2010 November Print/export Truth table on [edit] archived The truth table of (also written as or ) is as follows: Venn diagram of Create a book 08-17094 Download as PDF No.
    [Show full text]
  • Combinational Logic Circuits
    CHAPTER 4 COMBINATIONAL LOGIC CIRCUITS ■ OUTLINE 4-1 Sum-of-Products Form 4-10 Troubleshooting Digital 4-2 Simplifying Logic Circuits Systems 4-3 Algebraic Simplification 4-11 Internal Digital IC Faults 4-4 Designing Combinational 4-12 External Faults Logic Circuits 4-13 Troubleshooting Prototyped 4-5 Karnaugh Map Method Circuits 4-6 Exclusive-OR and 4-14 Programmable Logic Devices Exclusive-NOR Circuits 4-15 Representing Data in HDL 4-7 Parity Generator and Checker 4-16 Truth Tables Using HDL 4-8 Enable/Disable Circuits 4-17 Decision Control Structures 4-9 Basic Characteristics of in HDL Digital ICs M04_WIDM0130_12_SE_C04.indd 136 1/8/16 8:38 PM ■ CHAPTER OUTCOMES Upon completion of this chapter, you will be able to: ■■ Convert a logic expression into a sum-of-products expression. ■■ Perform the necessary steps to reduce a sum-of-products expression to its simplest form. ■■ Use Boolean algebra and the Karnaugh map as tools to simplify and design logic circuits. ■■ Explain the operation of both exclusive-OR and exclusive-NOR circuits. ■■ Design simple logic circuits without the help of a truth table. ■■ Describe how to implement enable circuits. ■■ Cite the basic characteristics of TTL and CMOS digital ICs. ■■ Use the basic troubleshooting rules of digital systems. ■■ Deduce from observed results the faults of malfunctioning combina- tional logic circuits. ■■ Describe the fundamental idea of programmable logic devices (PLDs). ■■ Describe the steps involved in programming a PLD to perform a simple combinational logic function. ■■ Describe hierarchical design methods. ■■ Identify proper data types for single-bit, bit array, and numeric value variables.
    [Show full text]
  • Tutorial on Adder and Subtractor Logic Circuits Digital Adder: 1. Half Adder 2. Full Adder. Half Adder- Full Adder
    Tutorial on Adder and Subtractor Logic Circuits Digital Adder: In digital electronics an adder is a logic circuit that implements addition of numbers. In many computers and other types of processors, adders are used to calculate addresses, similar operations and table indices in the arithmetic logic unit (ALU) and also in other parts of the processors. These can be built for many numerical representations like binary coded decimal or excess-3. Adders are classified into two types: 1. Half adder 2. Full adder. Half Adder- The half adder circuit is required to add two input digits (for Ex. A and B) and generate a carry and sum. The half adder adds two binary digits called as augend and addend and produces two outputs as sum and carry (XOR is applied to both inputs to produce sum and AND gate is applied to both inputs to produce carry). It means half adder circuits can add only two digits in other words if we need to add more than 2 digits it will not work, so, it the limitation of an half adder electronic circuits. To resolve this problem a full adder circuit is required. Application- The ALU of a computer uses half adder to compute the binary addition operation on two bits. Half adder is used to make full adder as a full adder requires 3 inputs, the third input being an input carry i.e. we will be able to cascade the carry bit from one adder to the other. Ripple carry adder is possible to create a logical circuit using multiple full adders to add N- bit numbers.
    [Show full text]
  • Logic Families
    Logic Families PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Mon, 11 Aug 2014 22:42:35 UTC Contents Articles Logic family 1 Resistor–transistor logic 7 Diode–transistor logic 10 Emitter-coupled logic 11 Gunning transceiver logic 16 Transistor–transistor logic 16 PMOS logic 23 NMOS logic 24 CMOS 25 BiCMOS 33 Integrated injection logic 34 7400 series 35 List of 7400 series integrated circuits 41 4000 series 62 List of 4000 series integrated circuits 69 References Article Sources and Contributors 75 Image Sources, Licenses and Contributors 76 Article Licenses License 77 Logic family 1 Logic family In computer engineering, a logic family may refer to one of two related concepts. A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using one of several different designs, usually with compatible logic levels and power supply characteristics within a family. Many logic families were produced as individual components, each containing one or a few related basic logical functions, which could be used as "building-blocks" to create systems or as so-called "glue" to interconnect more complex integrated circuits. A "logic family" may also refer to a set of techniques used to implement logic within VLSI integrated circuits such as central processors, memories, or other complex functions. Some such logic families use static techniques to minimize design complexity. Other such logic families, such as domino logic, use clocked dynamic techniques to minimize size, power consumption, and delay. Before the widespread use of integrated circuits, various solid-state and vacuum-tube logic systems were used but these were never as standardized and interoperable as the integrated-circuit devices.
    [Show full text]
  • IST 4 Information and Logic Mon Tue Wed Thr Fri
    IST 4 Information and Logic mon tue wed thr fri 30 M1 T = today 1 6 oh M1 oh x= hw#x out 13 oh oh 1 2M2 x= hw#x due 20 oh oh 2 27 oh M2 oh midterms Students’ MQ oh = office hours presentations 4 3 oh oh Mx= MQx out 11 oh 3 4 oh 18 T Mx= MQx due oh oh 4 5 25 oh oh 1 oh 5 oh Last Lecture - Stoc has tic chem ica l network s Stochastic logic design The B- algorithm Duality - Molecular switches DNA strand displacement 1 1 - Stochastic flow networks 2 2 Feedback helps! 1 2 1 2 3 2 1 3 A relay circuit is a physical system for syntax manipulation Relay circuits are not the only option! AND gate OR gate Circuits with Gates AON: AND, OR, Not Questions about building blocks? Feasibility Given a set of building blocks: What can/cannot be constructed? Efficiency and complexity If feasible, how many blocks are needed? Algorizm? AND, OR and NOT (AON) What is the function computed by this circuit? a a b 3 total number of gates in the circuit a 2 b longest path from input b to output – counting the number of gates Every 0-1 Boolean Function Can be Implemented Using A Depth Two AON Circuit Implement the DNF representation: OR of many ANDs XOR of 3 Variables abc XOR(a,b,c) 000 0 001 1 010 1 011 0 100 1 101 0 110 0 111 1 XOR of 3 Variables DthDepth = 2 a b c > Size = 5 a b > c > a b c >> is the complement a b c >> XOR of More Variables? How many gates in a depth-2 circuit for XOR of n variables with AON? It is optimal size for depth-2 Depth-2 AON Circuit for XOR Theorem: An optimal size depth-2 AON circuit for has gates Proof: The construction follows from the DNF representation: a b normal terms + one OR gate c >>> a b > The lower bound: c >>> WLOG a b c >>>>>> (i) Every AND gate must have a b ??? all n inputs c >>> (ii) Every AND gate computes a normal term DNF is a representation, hence, Without Loss Of there are AND gates Generality?? Depth-2 AON Circuit for XOR Theorem: An optimal size depth-2 AON circuit for has gates Proof (cont): Need to prove: (i) Every AND gate must have all n inputs By contradiction: Assume that there is a gate G with n-1 Making G=1 ? inputs .
    [Show full text]
  • Quantum Gates and Circuits
    Quantum Gates and Circuits B y David P. DiVincenzo IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY 10598 USA A historical review is given of the emergence of the idea of the quantum logic gate from the theory of reversible Boolean gates. I highlight the quantum XOR or controlled NOT as the fundamental two-bit gate for quantum computation. This gate plays a central role in networks for quantum error correction. 1. Introduction In this contribution I survey some topics of current interest in the properties of quantum gates and their assembly into interesting quantum circuits. It may be noted that this paper, like a large fraction of the others to be found in this volume of contributions to the ITP conference on Quantum Coherence and Decoherence, is about quantum computation and, apparently, not about quantum coherence at all. Let me assure the reader that it has not been the intention of me or my coorganizer Wojciech Zurek to engage intentionally in false advertising in the title of this conference. In fact, it is my view, and, I hope, a dominant view in this field, that quantum computation has everything to do with quantum coherence and decoherence. Indeed, I think of quantum computation as a very ambitious program for the exploitation of quantum coherence. Many of us at this meeting believe that quantum computers will be, first and foremost, the best tools that we have ever invented for probing the fundamental properties of quantum coherence. It is thus that I justify the legitimacy of what will be found in this volume, all arXiv:quant-ph/9705009v1 7 May 1997 under the heading of quantum coherence.
    [Show full text]
  • Lecture 12 Binary Adder-Subtractor.Pdf
    Objectives: 1. Half Adder. 2. Full Adder. 3. Binary Adder. 4. Binary Subtractor. 5. Binary Adder-Subtractor. 1. Half Adder Half Adder: is a combinational circuit that performs the addition of two bits, this circuit needs two binary inputs and two binary outputs. Inputs Outputs The simplified Boolean function from the truth table: 0 0 0 0 0 1 0 1 (Using sum of product form) 1 0 0 1 1 1 1 0 Where is the sum and is the carry. Truth table (Using XOR and AND Gates) X X Y Y X Y S S C C Implementation of Half Adder using equation (1) Implementation of Half Adder using equation (2) The implementation of half adder using exclusive–OR and an AND gates is used to show that two half adders can be used to construct a full adder. The inputs to the XOR gate are also the inputs to the AND gate. 2. Full Adder Full Adder is a combinational circuit that performs the addition of three bits (two significant bits and previous carry). It consists of three inputs and two outputs, two inputs are the bits to be added, the third input represents the carry form the previous position. The full adder is usually a component in a cascade of adders, which add 8, 16, etc, binary numbers. Inputs Outputs The output is equal to 1 when only one input is equal to 1 or when all 0 0 0 0 0 three inputs are equal to 1. 0 0 1 1 0 The output has a carry 1 if 0 1 0 1 0 two or three inputs are equal to 1.
    [Show full text]