VT-d and FreeBSD Константин Белоусов
[email protected] 21 сентября 2013 г. Revision : 1:11 Константин Белоусов
[email protected] VT-d and FreeBSD PCIe Example PCI Express Topology – Root & Switch CPU Bus CPU Root RCRB Bus 0 Root Complex Memory Virtual Virtual Virtual PCI PCI PCI Bridge Bridge Bridge PCIe PCIe PCIe PCIe PCIe PCIe Switch PCI Express Links Endpoint Endpoint PCIe Bridge To PCIe PCIe PCI/PCI-X Switch Virtual PCIe Legacy PCI Endpoint Endpoint PCI/PCI-X Bridge Virtual Virtual Virtual PCI PCI PCI Legend Bridge Bridge Bridge PCI Express Device Downstream Port PCI Express Device Upstream Port PCI-SIG Developers Conference Copyright © 2007, PCI-SIG, All Rights Reserved 8 Константин Белоусов
[email protected] VT-d and FreeBSD PCIe TLP - Transaction Layer Packets I/O Host access to device (BARs) Device access to memory (DMA) Peer to peer GPU RDMA over Infiniband Nvidia Optimus Messaging: Interrupts, Errors Configuration I/O. Константин Белоусов
[email protected] VT-d and FreeBSD Device DMA engines Features and Limitations Scatter/Gather: number of segments DMA engine restrictions Address width Dead bits (alignment) Segment length Streaming Coherence (Snoop) Traffic Prioritization Константин Белоусов
[email protected] VT-d and FreeBSD I ntroduction—Intel® Virtualization Technology for Directed I / O 1 Introduction This document describes the Intel® Virtualization Technology for Directed I/O (“Intel® VT for Directed I/O”); specifically, it describes the components supporting I/O virtualization as it applies to platforms that useVT-d Intel® processors and core logic chipsets complying with Intel® platform specifications. Figure 1-1 illustrates the general platform topology.