Qseven Design Guide Version

Qseven® Design Guide

Guidelines for designing Qseven® carrier boards

Version 2.0 of March 5, 2015

Note that some content of this specification may be legally protected by patents rights not held by SGeT. SGeT is not obligated to identify the parts of this specification that require licensing or other legitimization. SGeT specifications prospective are advisory only. Users of the SGeT are responsible for protecting themselves against liability for infringement of patents.

All content and information within this document are subject to change without prior notice.

SGeT provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. SGeT assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user’s guide. In no event shall SGeT be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information contained herein or the use thereof.

Revision Date (dd.mm.yy) Author Revision History 0.1 02.02.09 Qseven® Consortium Initial Draft 0.2 16.02.09 Qseven® Consortium Updates throughout document. 0.3 19.02.09 Qseven® Consortium English proofreading. 0.4 26.06.09 Qseven® Consortium Added changes requested by the consortium members and updated schematics (SP30E90001_VC3) 0.5 09.07.09 Qseven® Consortium Added PCB footprint of Qseven® module and MXM connector 0.6 04.08.09 Qseven® Consortium Added changes requested by the consortium members 0.7 21.08.09 Qseven® Consortium Created release candidate. 0.8 16.09.09 Qseven® Consortium Updated to current schematics (SP31E90001). Changed component height value for carrier board components located under Qseven® module. Added Figure 2-1. 0.9 Qseven® Consortium Changed naming convention of pin 91 from USB_HOST_PRES# to USB_CC, pin 92 from USB_HC_SEL to USB_ID in order to be compliant with OTG specification. Changed name USB_HOST_PRES# to USB_CC, USB_HC_SEL to USB_ID and changed the signal descriptions in Fehler: Referenz nicht gefunden for these signals. Updated signal names in pinout table Fehler: Referenz nicht gefunden. Updated signal descriptions in section “3.1 Signal Descriptions.” Added section USB Client Considerations and Fehler: Referenz nicht gefunden. Changed values in LAN Trace Routing Guidelines Fehler: Referenz nicht gefunden. Changed the values for Trace width (W) and Spacing between differential pairs (intra-pair) (S) in Fehler: Referenz nicht gefunden,Fehler: Referenz nicht gefunden, Fehler: Referenz nicht gefunden,Fehler: Referenz nicht gefunden and Fehler: Referenz nicht gefunden. 1.0 18.04.11 Qseven® Consortium Updated SDIO example schematics Fehler: Referenz nicht gefunden. Added CAN section Fehler: Referenz nicht gefunden and SPI section 3.16 . Updated SDVO Trace Routing Guidelines Fehler: Referenz nicht gefunden. Added USB Client section 3.7.2.3 . Added note regarding GP I2C bus. Added indication regarding power protection. Updated level shifter in figure Fehler: Referenz nicht gefunden. 1.0 SGeT 2013-05-04 SGeT e.V. Added SGeT Copyright page. Updated disclaimers and header/footer layout following SGeT Guidelines. Changed Links to www.sget.org . Updated copyright Notice and Trademarks 1.2 alpha 2013-09-09 SGeT e.V Full rework – Updated everything to Rev 1.2 including Schematics to current 1.2 Reference Board 1.2 2014-02-09 SGeT e.V Reworked graphics figures to reduce pdf size and enhance readability – no changes in text or graphics content 2.0 r.c. 2015-02-24 SGeT e.V Introduced new Chapter structure Rework for 2.0: Changed contents and adapted Schematics to match the new 2.0 Reference Board. 2.7 mm height between Qseven Module and carrier board no longer specified with 2.0; only 5.0 mm is permitted. Added PCIe lane multiplexer. Replaced Express Card with UART as defined in Specification V. 2.0

Qseven Design Guide Page 3 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Revision Date (dd.mm.yy) Author Revision History Added USB3.0 SuperSpeed Removed SVDO Graphics chapter. Added eDP Graphics chapter. Updated connector pinning following Errandum to Spcification. Updated connector signals to new TMDS/DP scheme. Updated Layout rules sections. Final cleanup: Request for Release 2.0 2015-03-05 SGET e.V. Last cleanup and Release

This document provides information for designing a custom system carrier board for Qseven® modules. This document includes reference schematics for the external circuitry required to implement the various Qseven® peripheral functions. It also explains how to extend the supported buses and how to add additional peripherals and expansion slots to a Qseven® based system.

This design guide is not a specification. It contains additional detail information but does not replace the Qseven® specification. It's strongly recommended to use the latest Qseven® specification and the module vendor's product manuals as reference material.

Disclaimer The information contained within this Qseven® Design Guide, including but not limited to any product specification, is subject to change without notice. The SGeT e.V. provides no warranty with regard to this Qseven® Design Guide or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. The SGeT e.V. assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the Qseven® interface specification. In no event shall the SGeT e.V. be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this Qseven ® interface specification or any other information contained herein or the use thereof.

The typical application circuits described in this document may not be suitable for all applications. In particular, additional components may need to be added to these circuits in order to meet specific ESD, EMC or safety isolation requirements. Such regulatory requirements and the techniques for meeting them vary by industry and are beyond the scope of this document.

Intended Audience This Qseven® Design Guide is intended for technically qualified personnel. It is not intended for general audiences.

Symbols The following symbols may be used in this specification:

Warning

Warnings indicate conditions that, if not observed, can cause personal injury.

Caution

Cautions warn the user about how to prevent damage to hardware or loss of data.

Note

Notes call attention to important information that should be observed.

Qseven Design Guide Page 5 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Copyright Notice Copyright © 2008-2014, SGeT e.V. . All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from the SGeT e.V..

The SGeT e.V. has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied “as-is”.

Trademarks Intel and Pentium are registered trademarks of Intel Corporation. ExpressCard is a registered trademark of Personal Computer Memory Card International Association (PCMCIA). PCI Express is a registered trademark of Peripheral Component Interconnect Special Interest Group (PCI-SIG). All product names and logos are property of their owners.

Lead-Free Designs (RoHS) All Qseven® designs shall be created from lead-free components in order to be RoHS compliant.

Qseven® Logo Usage The Qseven® logo is freely available for members of the SGeT e.V.. The logo can only be applied to products that are fully compliant to the specification of the Qseven® standard.

The SGeT e.V. reserves the right to take legal action against any party that fails to comply with the rules stated above for Qseven® logo usage.

High resolution formats are available at the members area www.sget.org.

Qseven® Name Usage The Qseven® name is freely available for members of the SGeT e.V.. The logo can only be applied to products that are fully compliant to the specification of the Qseven® standard.

The SGeT e.V. reserves the right to take legal action against any party that fails to comply with the rules stated above for Qseven® name usage.

Electrostatic Sensitive Device All electronic parts described in this design guide are electrostatic sensitive devices and are packaged accordingly. Do not open or handle a carrier board or module except at an electrostatic-free workstation. Additionally, do not ship or store electronic devices near strong electrostatic, electromagnetic, magnetic, or radioactive fields unless the device is contained within its original manufacturer's packaging.

• May - Indicates flexibility of choice with no implied recommendation or requirement.

• Shall - Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.

• Should - Indicates a strong recommendation but not a mandatory requirement. Designers should give strong consideration to such recommendations but there is still a choice in implementation.

Qseven® Concept The Qseven® concept is an off-the-shelf, multi vendor, Single-Board-Computer (SBC) that integrates all the core components of a typical PC and is mounted onto an application specific carrier board. Qseven® modules have a standardized form factor of 70mm x 70mm (Qseven) or 70mmm x 40mm (µQseven) and have specified pinouts based on the high speed MXM 2 system connector which are standardized regardless of the vendor. The Qseven® module provides the functional requirements for an embedded application. These functions include, but are not limited to, graphics, audio, mass storage, network and multiple USB ports. A single ruggedized MXM 2 connector provides the carrier board interface to carry all the I/O signals to and from the Qseven® module. This MXM connector is a well known and proven high speed signal interface connector that is commonly used for high speed PCI Express graphics cards in notebooks.

Carrier board designers can utilize as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a densely packed solution, which results in a more reliable product while simplifying system integration. Most importantly, Qseven® applications are scalable, which means once a product has been created there is the ability to diversify the product range through the use of different performance class Qseven® modules. Simply unplug one module and replace it with another, no redesign is necessary.

Qseven® offers the newest I/O technologies on this minimum size form factors.

Term Description PCI Express (PCIe) Peripheral Component Interface Express. Next-generation high speed serialized I/O bus PCI Express Lane One PCI Express Lane is a set of 4 signals that contains two differential lines for Transmitter and two differential lines for Receiver. Clocking information is embedded into the data stream. x1, x2, x4, x8, x16 x1 refers to one PCI Express Lane of basic bandwidth; x2 to a collection of two PCI Express Lanes; etc.. Also referred to as x1, x2, x4, x8 and x16 link. DDC Display Data Channel is an I²C bus interface between a display and a graphics adapter. DVI Digital Visual Interface is a video interface standard developed by the Digital Display Working Group (DDWG). MXM Mobile PCI Express Module a standard for mobile modular graphics cards avaiable in different revisions. Revision 2 is used for Qseven. GBE Gigabit Ethernet USB Universal Serial Bus OTG On The Go – USB extension for automated switching between USB host and client mode. SATA Serial AT Attachment: serial interface standard for hard disks. HDA High Definition Audio HDMI High Definition Multimedia Interface. HDMI supports standard, enhanced, or high-definition video, plus multi-channel digital audio on a single cable. SDIO Secure Digital Input Output TMDS Transition Minimized Differential Signaling. TMDS is a signaling interface defined by Silicon Image that is used for DVI and HDMI. LPC Low Pin-Count Interface: a low speed interface used for peripheral circuits such as Super I/O controllers, which typically combine legacy-device support into a single IC. SMB System Management Bus LVDS Low-Voltage Differential Signaling ACPI Advanced Control Programmable Interface RoHS Restriction on Hazardous Substances: The Directive on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment 2002/95/EC. N.C. Not connected N.A. Not available T.B.D. To be determined

Schematics Naming Conventions

Voltage Reference Description VCC12V 12 volt input power rail. VCC5V 5 volt input power rail. VCC3V3 3.3 volt input power rail. VCC5V_A 5 volt input power rail during standby. VCC3V3_A 3.3 volt input power rail during standby. VCC3_RTC +2.0V to +3.3V CMOS battery power

1 Customer Feedback...... 15 2 Qseven® Specification Overview...... 16 2.1 Qseven® Feature Overview...... 16 2.2 Qseven® Mechanical Characteristics...... 17 2.3 Mechanical Dimensions...... 19 2.3.1 Module Outlines...... 19 2.3.1.1 Qseven® Module Outlines...... 19 2.3.1.2 µQseven Module Outlines...... 20 2.3.2 MXM Connector ...... 21 2.3.2.1 MXM 2 Connector Dimensions...... 22 2.3.2.2 MXM 2 Connector Footprint ...... 23 2.3.2.3 Qseven® Module and MXM Connector PCB Footprint ...... 23 3 Carrier Board Design compliant to Qseven Specification 2.0...... 24 3.1 Concept Overview...... 25 3.2 Connector Pin Assignments...... 27 3.2.1 Signal Descriptions...... 32 3.3 PCI Express ...... 33 3.3.1 PCI Express Interface Signals...... 33 3.3.2 PCI Express Implementation Guidelines...... 34 3.3.2.1 PCI Express Reference Clock...... 34 3.3.2.2 PCI Express Reset...... 36 3.3.2.3 PCI Express Lane Configurations And Multiplexing...... 36 3.3.2.4 PCI Express x1, x4 and x16 Connectors ...... 38 3.3.2.5 PCI Express Power Requirements...... 42 3.3.2.6 PCI Express Mini Card 2.0...... 43 3.3.2.7 PCI Express Switch ...... 46 3.3.3 Routing Considerations for PCI Express...... 46 3.4 UART...... 47 3.4.1 UART Interface Signals...... 47 3.4.2 UART Implementation example...... 47 3.5 Gigabit Ethernet LAN...... 48 3.5.1 Gigabit Ethernet Signals...... 48 3.5.2 LAN Implementation Guidelines...... 48 3.5.2.1 LAN Magnetics Modules...... 49 3.5.2.2 LAN Component Placement...... 49 3.5.2.3 LAN Ground Plane Separation...... 49 3.5.2.4 LAN Link Activity and Speed LED...... 50 3.5.2.5 LAN Reference Schematics...... 50 3.5.3 Routing Considerations for LAN...... 50 3.6 Serial ATA Interface...... 51 3.6.1 Serial ATA Interface Signals...... 51 3.6.2 Serial ATA Implementation Example...... 51 3.6.3 Routing Considerations for Serial ATA...... 54 3.7 USB Interface...... 55 3.7.1 USB Interface Signals...... 55 3.7.2 USB Implementation Guidelines...... 57 3.7.2.1 Mixed USB2.0/3.0 Distribution...... 57 3.7.2.2 USB 2.0 Reference Schematics...... 58 3.7.2.3 USB 3.0 Reference Schematics...... 58 3.7.2.4 USB Overcurrent Protection...... 59

Qseven Design Guide Page 9 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.7.2.5 EMI/ESD Protection ...... 60 3.7.2.6 USB Client Considerations...... 60 3.7.3 Routing Considerations for USB...... 61 3.8 SDIO Interface...... 62 3.8.1 SDIO Interface Signals Definition...... 62 3.8.2 SDIO Card Implementation Example...... 63 3.9 High Definition Audio / AC97 / I²S Audio Signals...... 64 3.9.1 High Definition Audio / AC97 / I²S Audio Signals Definitions...... 64 3.9.2 High Definition Audio / AC97 / I²S Guidelines / Examples...... 65 3.9.2.1 HDA Implementation Example...... 65 3.9.2.2 I²S Implementation Example...... 65 3.9.2.3 AC97 Implementation Example...... 68 3.9.3 HDA / AC97 / I2S Placement and Routing Guidelines...... 69 3.10 LVDS Flat Panel Signals...... 70 3.10.1 LVDS Flat Panel Interface Signals...... 70 3.10.2 LVDS Implementation Guidelines...... 71 3.10.2.1 Connector and Cable Considerations...... 71 3.10.2.2 Display Timing Configuration...... 72 3.10.2.3 Backlight Control...... 73 3.10.3 Routing Considerations for LVDS...... 74 3.11 Embedded DisplayPort (eDP)...... 75 3.11.1 eDP Interface Signals...... 75 3.11.2 eDP Implementation Guidelines...... 76 3.11.2.1 Connector and Cable Considerations...... 76 3.11.2.2 Display Timing ...... 78 3.11.2.3 eDP Backlight and Panel Voltage Control...... 79 3.11.3 Routing Considerations for eDP...... 79 3.12 DisplayPort Interface ...... 80 3.12.1 DisplayPort Interface Signals (from Module)...... 80 3.12.1.1 DisplayPort Connector Signals...... 81 3.12.2 DP++ to DVI or HDMI Transmitter Reference Circuitry...... 82 3.12.2.1 DP++ Transmitter Reference Circuitry...... 83 3.13 HDMI Interface Signals (from Module)...... 84 3.13.1 HDMI Implementation...... 84 3.13.1.1 HDMI Connector Signals...... 85 3.13.2 Passive HDMI/DVI Transmitter Reference Circuitry...... 86 3.14 LPC Interface Signals ...... 87 3.14.1 LPC Bus Clock Signal...... 87 3.14.1.1 Routing Considerations for LPC Clock...... 88 3.14.2 LPC Reset Signal...... 88 3.14.3 LPC Super I/O Support...... 88 3.14.3.1 LPC Super I/O with Nuvoton W83627DHG...... 89 3.14.3.2 Boot Up Configuration for Nuvoton W83627DHG...... 90 3.14.3.3 LPC Super I/O with SMSC SCH3114...... 91 3.14.3.4 LPC Boot Up Configuration for SMSC SCH3114...... 91 3.14.3.5 LPC Super I/O with EXAR X28V384...... 92 3.14.3.6 LPC Boot Up Configuration for EXAR X28V384...... 92 3.14.3.7 LPC RS232 Serial Port Reference Circuitry...... 93 3.14.3.8 LPC configurable RS232 Serial Port Reference Circuitry...... 93 3.14.3.9 LPC PS2 Keyboard Port Reference Circuitry...... 93 3.14.4 LPC Firmware Hub...... 94 3.15 CAN Bus Interface Signals...... 95 3.16 SPI Interface Signals...... 96 3.17 Input Power...... 97

Qseven Design Guide Page 10 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.17.1 Single Source Power Supply...... 99 3.17.2 ATX Power Supply...... 100 3.17.2.1 ATX Power Connector...... 100 3.17.3 RTC Battery...... 102 3.17.3.1 RTC Battery Reference Circuitry...... 102 3.17.3.2 RTC Battery Lifetime...... 102 3.18 Power Control Signals...... 103 3.18.1 Power Good Input Signal PWGIN...... 103 3.18.2 Power Button Signal PWRBTN#...... 103 3.18.3 Power Up Control...... 104 3.18.4 ATX Power Up Control...... 104 3.19 Power Management Signals...... 106 3.20 I²C Bus...... 108 3.20.1 I²C Implementation Example...... 108 3.21 Miscellaneous Signals...... 109 3.21.1 Watchdog Control Signals...... 109 3.21.2 PC Speaker Output...... 110 3.21.3 External BIOS Flash Signal BIOS_DISABLE...... 110 3.22 Thermal Management Signals...... 110 3.23 Fan Control Implementation...... 111 3.23.1 Fan Control Reference Schematics...... 111 4 Layout and Design Constraints...... 112 4.1 Microstrip or Stripline...... 112 4.2 Printed Circuit Board Stackup Example...... 112 4.3 General Considerations for High-Speed Differential Interfaces...... 114 4.4 PCI Express Trace Routing Guidelines...... 117 4.5 USB Trace Routing Guidelines...... 119 4.6 TMDS Trace Routing Guidelines...... 121 4.7 Display Port Trace Routing Guidelines...... 122 4.8 LAN Trace Routing Guidelines...... 123 4.9 Serial ATA Trace Routing Guidelines...... 124 4.10 LVDS Trace Routing Guidelines...... 125 5 Industry Specifications...... 126

Qseven Design Guide Page 11 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Tables Table 2-1 Qseven® Supported Features...... 16 Table 2-2 MXM Connector...... 21 Table 3-1 Connector Pinout Description...... 27 Table 3-2 Signal Tables Terminology Descriptions...... 32 Table 3-3 Signal Definition PCI Express...... 33 Table 3-4 PCI Express x1, x4 and x16 Connector Pinout and Signal Description...... 40 Table 3-5 PCI Express Connector Power Requirements...... 43 Table 3-6 PCIe Power Decoupling Requirements...... 43 Table 3-7 PCI Express Mini Card 2.0 Control Signal Descriptions...... 43 Table 3-8 PCI Express Mini Card 2.0 Connector Pinout...... 45 Table 3-9 Signal Definition of UART...... 47 Table 3-10 Signal Definition Ethernet Signals...... 48 Table 3-11 Recommended LAN Magnetic Modules...... 49 Table 3-12 Signal Definition SATA...... 51 Table 3-13 Serial ATA Data Connector Pinout and Signal Description...... 52 Table 3-14 Serial ATA Power Connector Pinout and Signal Description...... 53 Table 3-15 mSATA Connector Pinout and Signal Description...... 53 Table 3-16 Signal Definition USB...... 55 Table 3-17 USB 2.0 Host Dual Type-A Connector Pinout ...... 58 Table 3-18 USB 3.0 Type A Connector Pinout ...... 58 Table 3-19 USB 3.0 microAB Host/Client Connector Pinout ...... 59 Table 3-20 Signal Definition SDIO...... 62 Table 3-21 Signal Definition HDA...... 64 Table 3-22 LVDS Signals...... 70 Table 3-23 Embedded DisplayPort Signals...... 75 Table 3-24 Pinout Embedded DisplayPort Connector (eDP) 30 Pin on Baseboard...... 76 Table 3-25 Pinout Embedded DisplayPort Connector (eDP) 40 Pin on Baseboard...... 77 Table 3-26 Signal Definition DisplayPort...... 80 Table 3-27 Pinout DisplayPort Connector...... 81 Table 3-28 Signal Definition HDMI...... 84 Table 3-29 Pinout HDMI Connector...... 85 Table 3-30 Signal Definition LPC...... 87 Table 3-31 Signal Definition CAN Bus...... 95 Table 3-32 Signal Definition SPI Interface...... 96 Table 3-33 Signal Definition Input Power...... 98 Table 3-34 ATX Connector 24 PIN...... 100 Table 3-35 ATX Connector 20 Pin...... 101 Table 3-36 +12V Power Connector 4 Pin...... 101 Table 3-37 Signal Definition Power Control...... 103 Table 3-38 System States S0-S5 Definitions...... 106 Table 3-39 Signal Definition Power Management...... 107 Table 3-40 I²C bus Signals...... 108 Table 3-41 Miscellaneous Signals...... 109 Table 3-42 Signal Definition Thermal Management...... 110 Table 3-43 Signal Definition Fan Control...... 111 Table 4-1 PCI Express Gen1/2(/3) Trace Routing Guidelines...... 117 Table 4-2 USB 2.0 Trace Routing Guidelines...... 119 Table 4-3 USB 3.0 SuperSpeed Trace Routing Guidelines...... 120 Table 4-4 TMDS Trace Routing Guidelines...... 121 Table 4-5 DisplayPort Trace Routing Guidelines...... 122 Table 4-6 LAN Trace Routing Guidelines...... 123 Table 4-7 Serial ATA Trace Routing Guidelines...... 124 Table 4-8 LVDS Trace Routing Guidelines...... 125

Figures Figure 2-1 Bottom Side Qseven® Module and Carrier Board Component Heights...... 17 Figure 2-2 Overall Height including Heatspreader of the Qseven® Module...... 18 Figure 2-3 Mechanical Dimensions of the Qseven® Module...... 19 Figure 2-4 Mechanical Dimensions of the µQseven Module...... 20 Figure 2-5 MXM 2 Connector...... 22 Figure 2-6 Carrier Board PCB Footprint for the MXM Connector...... 23 Figure 2-7 PCB footprint for the Qseven® Module inserted in the MXM carrier board connector...... 23 Figure 3-1 Qseven V2.0 Reference Carrier Board overview...... 25 Figure 3-2 USB and PCI express distributions...... 26 Figure 3-3 Qseven® Connector Schematics...... 31 Figure 3-4 PCI Express Termination Default Configurations...... 34 Figure 3-5 PCI Express Clock Buffer Example...... 35 Figure 3-6 PCI Express Reset Buffer Example...... 36 Figure 3-7 PCI Express Lanes Multiplexer...... 37 Figure 3-8 PCI Express x1 Connector...... 38 Figure 3-9 PCI Express x16 Connector...... 39 Figure 3-10 PCI Express Mini Card 2.0 and Socket...... 44 Figure 3-11 PCI Express Mini Card Reference Circuitry...... 46 Figure 3-12 UART Reference Circuitry...... 47 Figure 3-13 LAN Ground Plane Separation...... 50 Figure 3-14 GbE Schematic Example ...... 50 Figure 3-15 Example Serial ATA Implementation (Data and Power)...... 52 Figure 3-16 Example for a Serial ATA / mSATA Switch implementation...... 52 Figure 3-17 Example for USB 2.0 / 3.0 distribution...... 57 Figure 3-18 USB 2.0 Reference Circuit...... 58 Figure 3-19 USB 3.0 Reference Circuit...... 58 Figure 3-20 Current Limiter Circuitry ...... 59 Figure 3-21 USB Client Connect Protection...... 61 Figure 3-22 Example for SDIO Card Implementation...... 63 Figure 3-23 HDA Codec Reference Schematics...... 65 Figure 3-24 I²S Codec Reference Schematics...... 66 Figure 3-25 External I²S Audio Card Connectors Reference Schematics ...... 67 Figure 3-26 AC97 Codec Reference Schematics...... 68 Figure 3-27 LVDS Connector...... 72 Figure 3-28 LVDS I²C EEPROM...... 73 Figure 3-29 LVDS Backlight and Panel Supply Voltage Control Circuitry...... 73 Figure 3-30 eDP Connector and HPD Signal Inverter Schematics...... 78 Figure 3-31 eDP Backlight and Panel Voltage Control...... 79 Figure 3-32 DisplayPort Connector...... 81 Figure 3-33 DP++ to DVI/HDMI Transmitter Reference Circuitry using an active level shifter...... 82 Figure 3-34 DP++ to DP Transmitter Reference Circuitry...... 83 Figure 3-35 Pictures of a DP++ to DVI Level shifter...... 83 Figure 3-36 HDMI Connector...... 85 Figure 3-37 Passive HDMI to DVI/HDMI Transmitter Reference Circuitry...... 86 Figure 3-38 LPC Clock Buffer Reference Circuitry...... 88 Figure 3-39 LPC Super I/O Nuvoton W83627DHG Reference Circuitry ...... 89 Figure 3-40 Nuvoton W83627DHG Boot Strap Configuration...... 90 Figure 3-41 LPC Super I/O SMSC SCH3114 Reference Circuitry...... 91 Figure 3-42 SMSC SCH3114 Boot Strap Configuration...... 91

Figure 3-43 LPC Super I/O EXAR X28V34 Reference Circuit...... 92 Figure 3-44 EXAR X28V384 Boot Strap Configuration...... 92

Qseven Design Guide Page 13 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Figure 3-45 COM Port Reference Circuit (RS-232)...... 93 Figure 3-46 COM Port Reference Circuit (RS-232/485/422)...... 93 Figure 3-47 PS2 Keyboard Port Reference Circuit ...... 93 Figure 3-48 LPC Firmware Hub Reference Circuitry...... 94 Figure 3-49 CAN Bus Reference Circuitry...... 95 Figure 3-50 SPI Interface Connector Reference Circuitry...... 96 Figure 3-51 SPI Flash Reference Circuitry...... 96 Figure 3-52 Coded Power Connector for Reverse Polarity Protection...... 97 Figure 3-53 Reverse Polarity Protection Circuit...... 98 Figure 3-54 Power Enable Circuit for 5V_Always...... 99 Figure 3-55 Power Regulator Circuit for 5V_Always...... 99 Figure 3-56 Power Regulator Circuit for 5V_Switched...... 99 Figure 3-57 Schematic of 24 Pin ATX Power Connector...... 101 Figure 3-58 RTC Battery Circuitry with Serial Schottky Diode...... 102 Figure 3-59 PWGIN Generation Circuit...... 103 Figure 3-60 Power Button Implementation Example...... 103 Figure 3-61 Power Up Control Circuitry...... 104 Figure 3-62 ATX Power Up Control Circuitry...... 105 Figure 3-63 I²C Implementation Example...... 108 Figure 3-64 PC Speaker Implementation Example...... 110 Figure 3-65 Fan speed control circuitry...... 111 Figure 4-1 4 Layer PCB Microstrip Routing...... 113 Figure 4-2 6 Layer PCB Stripline and Microstrip Routing...... 113 Figure 4-3 Layout Considerations...... 115 Figure 4-4 Impedance calculation example in ADS...... 116

The Qseven® Design Guide has been created to help customers design Qseven® compliant carrier boards. It should be used in conjunction with the Qseven® Specification as well as any other relevant information with regards to the implementation of the interfaces mentioned within this document.

The guidelines set forth in this document have been carefully thought out by engineers of the SGeT e.V. and are considered to be the most important factors when designing a Qseven® carrier board. The SGeT e.V. is committed to helping customers who are designing Qseven® compliant carrier boards by sharing our expertise and providing the best possible support and documentation. Therefore, we welcome any suggestions our valued customers may have with regards to additional information that should be included in this Qseven® Design Guide. Additionally, we encourage any feedback about the contents of this document with regards to clarity and understanding.

If you have any suggestions about additional content, or any questions about the existing content, please contact the SGeT e.V. via email at [email protected].

2.1 Qseven® Feature Overview The Qseven® V2.0 Specification defines mandatory and optional features for both supported platform architectures. Table 2-1 shows the minimum and maximum required configuration of the feature set.

Table 2-1 Qseven® Supported Features

System I/O Interface ARM/RISC Based X86 Based Minimum Maximum Minimum Configuration Configuration Configuration PCI Express lanes 0 1 (x1 link) 4 Serial ATA channels 0 0 2 USB 2.0 ports 3 4 8 USB 3.0 ports 0 0 2 USB OTG 0 0 1 LVDS channels 0 0 Dual Channel 24bit embedded DisplayPort 0 0 2 DisplayPort, 0 0 1 TMDS High Definition Audio / AC'97 / 0 0 1 I2S Ethernet 10/100 Mbit/Gigabit 0 0 1 (Gigabit Ethernet) UART 0 0 1 Low Pin Count bus 0 0 1 Secure Digital I/O 8-bit 0 0 1 for SD/MMC cards System Management Bus 0 1 1 I²C Bus 1 1 1 SPI Bus 0 0 1 CAN Bus 0 0 1 Watchdog Trigger 1 1 1 Power Button 1 1 1 Power Good 1 1 1 Reset Button 1 1 1 LID Button 0 0 1 Sleep Button 0 0 1 Suspend To RAM (S3 mode) 0 0 1 Wake 0 0 1 Battery low alarm 0 0 1 Thermal control 0 0 1 FAN control 0 0 1

Qseven Design Guide Page 16 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 2.2 Qseven® Mechanical Characteristics The Qseven® module, including the heatspreader plate, PCB thickness and bottom components, is up to approximately 12mm thick.

Edge-fingers on the module are referenced to the PCB slot center with an overall PCB thickness of 1.2mm ±0.1mm measured across the fingers including the plating and/or metalization on both sides. A bevel is optional but the edge shall be free of burrs and shall not have sharp edges.

The components located on the top side of the module are up to 5.5mm high. Components mounted on the backside of the Qseven® module (in the space between the bottom surface of the module PCB and the top surface of the carrier board PCB) shall have a height of 2.5mm ±0.1 (dimension ‘B’ in Figure 2-1).

Carrier board component placement below the Qseven® module is only permitted when using a MXM 2 connector with a resulting height between carrier board and Qseven ® module of 5.0mm (dimension ‘A’ in Figure 2-1) and no carrier board component shall exceed a height of 2.2mm ±0.1 (dimension ‘C’ in Figure 2-1). Using carrier board topside components up to 2.2mm allows a gap of 0.3mm between carrier board topside components and the Qseven® module bottom side components. This may not be sufficient in some situations. In carrier board applications in which vibration or board flex is a concern, then the carrier board component height should be restricted to a value less than 2.2mm that yields a clearance that is sufficient for the application. Refer to Table 2-2 regarding MXM 2 connector specifications.

Figure 2-1 Bottom Side Qseven® Module and Carrier Board Component Heights

All measurements are in millimeters

The heatspreader offered for Qseven® modules acts as a thermal coupling device and is not a heat sink. Heat dissipation devices such as a heat sink with fan or heat pipe may need to be connected to the heatspreader. The dissipation of heat will vary between different CPU boards. Refer to the Qseven® module's user's guide for heatspreader dimensions and specifications.

The standoffs for the heatspreader and carrier board must not exceed 5.6mm overall external diameter. This ensures that the standoff contact area does not exceed the defined mounting hole footprint on the Qseven® module. The screw that is to be used for mounting must be a metric thread M2.5 DIN7985 / ISO7045.

Qseven Design Guide Page 17 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Qseven® modules are defined to feature ultra low power CPU and chipset solutions with an ultra low “Thermal Design Power” (TDP). Furthermore, the modules power consumption should not exceed 12W.

Figure 2-2 Overall Height including Heatspreader of the Qseven® Module

2.3.1 Module Outlines 2.3.1.1 Qseven® Module Outlines

Figure 2-3 Mechanical Dimensions of the Qseven® Module

The Qseven® PCB cooling plate shown in Figure 2-3 is to be used as a cooling interface between the Qseven® module and the application specific cooling solution.

Note

The Qseven® PCB cooling plate should be connected directly to the GND plane of the carrier board to ensure that the heat from the module can be properly dissipated.

Figure 2-4 Mechanical Dimensions of the µQseven Module

Note

If one carrier board design is used for both µQseven and Qseven ®, the standoffs of the smaller µQseven module will collide with the Qseven® module. To support both outlines, these standoffs of the µQseven module should be removed when full sized Qseven® modules are used.

Qseven Design Guide Page 20 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 2.3.2 MXM Connector The Qseven® carrier board utilizes a 230-pin card-edge connector to connect the Qseven® module. Originally, this card-edge connector was designed for MXM graphics modules that are used for PCI Express capable notebook graphics cards. The card-edge connector is following the MXM specification and therefore this connector type is also known as a MXM connector.

The MXM edge connector is the result of an extensive collaborative design effort with the industry's leading notebook manufacturers. This collaboration has produced a robust, low-cost edge connector that is capable of handling high-speed serialized signals.

The MXM connector accommodates various connector heights for different carrier board applications needs.

Table 2-2 MXM Connector

Manufacturer Part Number Specification Resulting height Overall height of Remarks between carrier the MXM Connector board and Qseven® module Foxconn AS0B32x-S78N-xH AS0B32x-S78N-xH 5.0mm 7.8mm 7.8mm oh Aces 88882-2Dxx 88882-2Dxx 5.0mm 7.5mm 7.5mm oh Nexus 5240HB75R 5240HB75R 5.0mm 7.5mm 7.5mm oh Yamaichi BEC05230S9xFRE BEC05230S9xFRE 5.0mm 7.8mm 7.8mm oh DC DC

Note

The connectors mentioned in Table 2-1 are only a partial list of what is offered by the manufacturers. For more information about additional variants contact the manufacturer and observe potential footprint changes.

All measurements are in millimeters.

Note:

Dimensions will vary according to the vendors solutions.

All measurements are in millimeters and mils ( in brackets).

Note

Please verify the footprint of the selected connector.

2.3.2.3 Qseven® Module and MXM Connector PCB Footprint Figure 2-7 PCB footprint for the Qseven® Module inserted in the MXM carrier board connector

All measurements are in millimeters

With the introduction of USB 3.0 in Version 2.0 of the Qseven Standard there are a lot of different configurations possible. There may be up to two USB 3.0 ports present and/or alternatively up to 8 USB 2.0 ports, each of them either to be placed on module or carrier board. Also various graphics configurations and two different processor technology platforms are supported.

This design guide is not intended to handle all details of all possible configurations. It shows proven examples which have been implemented and tested with the Qseven V2.0 Reference Carrier Board designed and manufactured by SECO. This is one of many possible configurations supporting a variety of options for both technology platforms. Schematic examples in this Design Guide refer to the implementation of this Reference Carrier Board unless otherwise stated.

Qseven Design Guide Page 24 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.1 Concept Overview The concept of the Qseven V2.0 Reference Carrier Board is laid out in Figure 3-1, 'Figure 3-2 shows the details of the USB and PCI express signal distributions. .A mini PCI express card interface is supported as well as various USB2.0/3.0 configurations. Switches and multiplexers allow the configuration to adapt the Qseven V2.0 Reference Carrier Board to work with the provided interfaces on the respective modules.

Figure 3-1 Qseven V2.0 Reference Carrier Board overview

mSATA +12 V

SATASATALCD LVDS BLT

SD/MMC

SPI REGULATORSVOLTAGE SO8 SOCKET

SWITCH S D t i SATA V L b

8 t i / b 4 1

4 0 A O 2 A

I T l T D A a A S S u

S RTC BATT D

I2C EEPROM I2C SPEAKER SO8 Socket

BUTTONS Qseven Module COM0 POSTCODE FAN

LPC LPC CONNECTOR

FEATURE LPC SUPER IO

A XR28 E B D G H

LPC SUPER IO W83627DHG

SWITCH R O

AUDIO T C E N N O

C PCIe and USB Distribution on next page

HDA AUDIO 6 1

CODEC x ETH EXPRESS E

ALC886 CARD I C

2x COM P 2x COM O

3x V D

AUDIO S -

JACK X E

HDMI/DP

as implemented on the Qseven V2.0 Reference Carrier Board (with multiplexers).

USB 3.0 TypeA

PCIe X4 or USB 3.0 X16 USB0 Micro AB PCIe0

USB1 PCIe1 PCIe0 USB2 SW mPCIe MUX with SIM PCIe2 PCIe X1 USB3 PCIe X1 PCIe3 USB4 Quad USB 2.0 USB MUX TypeA PCIe X1 USB5

USB6 USB MUX Setup switch USB7

Qseven module Qseven module

2x5 pin header

There are 115 edge fingers on the top and bottom side of the Qseven® module that mate with the MXM connector. Table 3-1 lists the pin assignments for all 230 edge fingers.

Table 3-1 Connector Pinout Description

Pin Signal Modul Pin direction Pin Signal Modul Pin direction 1 GND Power 2 GND Power 3 GBE_MDI3- High-Speed I/O 4 GBE_MDI2- High-Speed I/O 5 GBE_MDI3+ High-Speed I/O 6 GBE_MDI2+ High-Speed I/O 7 GBE_LINK100# Output 8 GBE_LINK1000# Output 9 GBE_MDI1- High-Speed I/O 10 GBE_MDI0- High-Speed I/O 11 GBE_MDI1+ High-Speed I/O 12 GBE_MDI0+ High-Speed I/O 13 GBE_LINK# Output 14 GBE_ACT# Output 15 GBE_CTREF Output (Analog) 16 SUS_S5# Output 17 WAKE# Input 18 SUS_S3# Output 19 SUS_STAT# Output 20 PWRBTN# Input 21 SLP_BTN# Input 22 LID_BTN# Input 23 GND Power 24 GND Power KEY KEY 25 GND Power 26 PWGIN Input (5V) 27 BATLOW# Input 28 RSTBTN# Input 29 SATA0_TX+ High-Speed Output 30 SATA1_TX+ High-Speed Output 31 SATA0_TX- High-Speed Output 32 SATA1_TX- High-Speed Output 33 SATA_ACT# Open Drain 34 GND Power 35 SATA0_RX+ High-Speed Input 36 SATA1_RX+ High-Speed Input 37 SATA0_RX- High-Speed Input 38 SATA1_RX- High-Speed Input 39 GND Power 40 GND Power 41 BIOS_DISABLE# / Input 42 SDIO_CLK# Output BOOT_ALT# 43 SDIO_CD# Input/Output 44 SDIO_LED Output 45 SDIO_CMD Input/Output 46 SDIO_WP Input 47 SDIO_PWR# Output 48 SDIO_DAT1 Input/Output 49 SDIO_DAT0 Input/Output 50 SDIO_DAT3 Input/Output 51 SDIO_DAT2 Input/Output 52 SDIO_DAT5 Input/Output 53 SDIO_DAT4 Input/Output 54 SDIO_DAT7 Input/Output 55 SDIO_DAT6 Input/Output 56 USB_DRIVE_VBUS Output 57 GND Power 58 GND Power 59 HDA_SYNC / Output 60 SMB_CLK / Open Drain Output AC97_SYNC / GP1_I2C_CLK I2S_WS 61 HDA_RST# / Output 62 SMB_DAT / Open Drain AC97_RST# / GP1_I2C_DAT Input/Output I2S_RST#

Qseven Design Guide Page 27 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Pin Signal Modul Pin direction Pin Signal Modul Pin direction 63 HDA_BCLK / Output 64 SMB_ALERT# Input AC97_BCLK / I2S_CLK 65 HDA_SDI / Input 66 GP0_I2C_CLK Open Drain Output AC97_SDI / I2S_SDI 67 HDA_SDO / Output 68 GP0_I2C_DAT Open Drain AC97_SDO / Input/Output I2S_SDO 69 THRM# Input 70 WDTRIG# Input 71 THRMTRIP# Output 72 WDOUT Output 73 GND Power 74 GND Power 75 USB_P7- / High-Speed I/O 76 USB_P6- / High-Speed I/O USB_SSTX0- USB_SSRX0- 77 USB_P7+ / High-Speed I/O 78 USB_P6+ / High-Speed I/O USB_SSTX0+ USB_SSRX0+ 79 USB_6_7_OC# Input 80 USB_4_5_OC# Input 81 USB_P5- / High-Speed I/O 82 USB_P4- / High-Speed I/O USB_SSTX1- USB_SSRX1- 83 USB_P5+ / High-Speed I/O 84 USB_P4+ / High-Speed I/O USB_SSTX1+ USB_SSRX1+ 85 USB_2_3_OC# Input 86 USB_0_1_OC# Input 87 USB_P3- High-Speed I/O 88 USB_P2- High-Speed I/O 89 USB_P3+ High-Speed I/O 90 USB_P2+ High-Speed I/O 91 USB_VBUS Input (5V) 92 USB_ID Input 93 USB_P1- High-Speed I/O 94 USB_P0- High-Speed I/O 95 USB_P1+ High-Speed I/O 96 USB_P0+ High-Speed I/O 97 GND Power 98 GND Power 99 eDP0_TX0+ / High-Speed Output 100 eDP1_TX0+ / High-Speed Output LVDS_A0+ LVDS_B0+ 101 eDP0_TX0- / High-Speed Output 102 eDP1_TX0- / High-Speed Output LVDS_A0- LVDS_B0- 103 eDP0_TX1+ / High-Speed Output 104 eDP1_TX1+ / High-Speed Output LVDS_A1+ LVDS_B1+ 105 eDP0_TX1- / High-Speed Output 106 eDP1_TX1- / High-Speed Output LVDS_A1- LVDS_B1- 107 eDP0_TX2+ / High-Speed Output 108 eDP1_TX2+ / High-Speed Output LVDS_A2+ LVDS_B2+ 109 eDP0_TX2- / High-Speed Output 110 eDP1_TX2- / High-Speed Output LVDS_A2- LVDS_B2- 111 LVDS_PPEN Output 112 LVDS_BLEN Output 113 eDP0_TX3+ / High-Speed Output 114 eDP1_TX3+ / High-Speed Output LVDS_A3+ LVDS_B3+ 115 eDP0_TX3- / High-Speed Output 116 eDP1_TX3- / High-Speed Output LVDS_A3- LVDS_B3- 117 GND Power 118 GND Power 119 eDP0_AUX+ / High-Speed I/O 120 eDP1_AUX+ / High-Speed I/O LVDS_A_CLK+ LVDS_B_CLK+ 121 eDP0_AUX- / High-Speed I/O 122 eDP1_AUX- / High-Speed I/O LVDS_A_CLK- LVDS_B_CLK-

Qseven Design Guide Page 28 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Pin Signal Modul Pin direction Pin Signal Modul Pin direction 123 LVDS_BLT_CTRL Output 124 GP_1-Wire_Bus Input/Output /GP_PWM_OUT0 125 GP2_I2C_DAT / Open Drain 126 eDP0_HPD# / Open Drain LVDS_DID_DAT Input/Output LVDS_BLC_DAT Input/Output 127 GP2_I2C_CLK / Open Drain Output 128 eDP1_HPD# / Open Drain LVDS_DID_CLK LVDS_BLC_CLK Input/Output 129 CAN0_TX Output 130 CAN0_RX Input 131 DP_LANE3+ / High-Speed Output 132 RSVD (Differential N.C. TMDS_CLK+ Pair) 133 DP_LANE3- / High-Speed Output 134 RSVD (Differential N.C. TMDS_CLK- Pair) 135 GND Power 136 GND Power 137 DP_LANE1+ / High-Speed Output 138 DP_AUX+ High-Speed I/O TMDS_LANE1+ 139 DP_LANE1- / High-Speed Output 140 DP_AUX- High-Speed I/O TMDS_LANE1- 141 GND Power 142 GND Power 143 DP_LANE2+ / High-Speed Output 144 RSVD (Differential N.C. TMDS_LANE0+ Pair) 145 DP_LANE2- / High-Speed Output 146 RSVD (Differential N.C. TMDS_LANE0- Pair) 147 GND Power 148 GND Power 149 DP_LANE0+ / High-Speed Output 150 HDMI_CTRL_DAT Open Drain TMDS_LANE2+ Input/Output 151 DP_LANE0- / High-Speed Output 152 HDMI_CTRL_CLK Open Drain Output TMDS_LANE2- 153 DP_HDMI_HPD# Input 154 DP_HPD# Input 155 PCIE_CLK_REF+ High-Speed Output 156 PCIE_WAKE# Input 157 PCIE_CLK_REF- High-Speed Output 158 PCIE_RST# Output 159 GND Power 160 GND Power 161 PCIE3_TX+ High-Speed Output 162 PCIE3_RX+ High-Speed Input 163 PCIE3_TX- High-Speed Output 164 PCIE3_RX- High-Speed Input 165 GND Power 166 GND Power 167 PCIE2_TX+ High-Speed Output 168 PCIE2_RX+ High-Speed Input 169 PCIE2_TX- High-Speed Output 170 PCIE2_RX- High-Speed Input 171 UART0_TX Output 172 UART0_RTS# Output 173 PCIE1_TX+ High-Speed Output 174 PCIE1_RX+ High-Speed Input 175 PCIE1_TX- High-Speed Output 176 PCIE1_RX- High-Speed Input 177 UART0_RX Input 178 UART0_CTS# Input 179 PCIE0_TX+ High-Speed Output 180 PCIE0_RX+ High-Speed Input 181 PCIE0_TX- High-Speed Output 182 PCIE0_RX- High-Speed Input 183 GND Power 184 GND Power 185 LPC_AD0 / GPIO0 Input/Output 186 LPC_AD1 / GPIO1 Input/Output 187 LPC_AD2 / GPIO2 Input/Output 188 LPC_AD3 / GPIO3 Input/Output 189 LPC_CLK / GPIO4 Input/Output 190 LPC_FRAME# / Input/Output GPIO5 191 SERIRQ / GPIO6 Input/Output 192 LPC_LDRQ# / Input/Output GPIO7

Qseven Design Guide Page 29 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Pin Signal Modul Pin direction Pin Signal Modul Pin direction 193 VCC_RTC Power (3V) 194 SPKR / Output GP_PWM_OUT2 195 FAN_TACHOIN Input 196 FAN_PWMOUT / Output /GP_TIMER_IN GP_PWM_OUT1 197 GND Power 198 GND Power 199 SPI_MOSI Output 200 SPI_CS0# Output 201 SPI_MISO Input 202 SPI_CS1# Output 203 SPI_SCK Output 204 MFG_NC4 N.C. 205 VCC_5V_SB Power (5V) 206 VCC_5V_SB Power (5V) 207 MFG_NC0 N.C. 208 MFG_NC2 N.C. 209 MFG_NC1 N.C. 210 MFG_NC3 N.C. 211 VCC Power (5V) 212 VCC Power (5V) 213 VCC Power (5V) 214 VCC Power (5V) 215 VCC Power (5V) 216 VCC Power (5V) 217 VCC Power (5V) 218 VCC Power (5V) 219 VCC Power (5V) 220 VCC Power (5V) 221 VCC Power (5V) 222 VCC Power (5V) 223 VCC Power (5V) 224 VCC Power (5V) 225 VCC Power (5V) 226 VCC Power (5V) 227 VCC Power (5V) 228 VCC Power (5V) 229 VCC Power (5V) 230 VCC Power (5V)

CN1A 1 2 3 GND GND 4 GBE_MDI3-[19] GBE_MDI2- [19] 5 GBE_MDI3- GBE0_MDI2- 6 GBE_MDI3+[19] GBE_MDI2+ [19] 7 GBE_MDI3+ GBE0_MDI2+ 8 GBE_LINK100#[19] GBE_LINK1000# [19] 9 GBE_LINK100# GBE0_LINK1000# 10 GBE_MDI1-[19] GBE_MDI0- [19] 11 GBE_MDI1- GBE0_MDI0- 12 GBE_MDI1+[19] GBE_MDI0+ [19] 13 GBE_MDI1+ GBE0_MDI0+ 14 GBE_LINK#[19] GBE_ACT# [19] 15 GBE_LINK# GBE0_ACT# 16 GBE_CTREF[19] 17 GBE_CTREF SUS_S5# 18 WAKE#[6] 19 WAKE# SUS_S3# 20 PWRBTN# [6,18] 21 SUS_STAT# PWRBTN# 22 SLP_BTN#[18] LIDBTN# [18] 23 SLP_BTN# LID_BTN# 24 GND GND SUS_S5# SUS_STAT# SUS_S3# 25 26 PWGIN [6,21] 27 GND PWGIN 28 BATLOW#[6] RSTBTN# [6,18,22] 29 BATLOW# RSTBTN# 30 SATA0_TX+[5] SATA1_TX+ [6] 31 SATA0_TX+ SATA1_TX+ 32 SATA0_TX-[5] SATA1_TX- [6] 33 SATA0_TX- SATA1_TX- 34 SATA_ACT#[4] 35 SATA_ACT# GND 36 SATA0_RX+[5] 37 SATA0_RX+ SATA1_RX+ 38 SATA1_RX+ [6] SATA0_RX-[5] SATA1_RX- [6] 39 SATA0_RX- SATA1_RX- 40 41 GND GND 42 BOOT_ALT#[6] SDIO_CLK [18] 43 BIOS_DISABLE# / BOOT_ALT# SDIO_CLK# 44 SDIO_CD#[18] SDIO_LED [18] 45 SDIO_CD# SDIO_LED 46 SDIO_CMD[18] SDIO_WP [18] 47 SDIO_CMD SDIO_WP 48 SDIO_PWR#[18] SDIO_DAT1 [18] 49 SDIO_PWR# SDIO_DAT1 50 SDIO_DAT0[18] SDIO_DAT3 [18] 51 SDIO_DAT0 SDIO_DAT3 52 SDIO_DAT2[18] SDIO_DAT5 [18] 53 SDIO_DAT2 SDIO_DAT5 54 SDIO_DAT4[18] SDIO_DAT7 [18] 55 SDIO_DAT4 SDIO_DAT7 56 SDIO_DAT6[18] USB_DRIVE_VBUS [16] 57 SDIO_DAT6 USB_DRIVE_VBUS 58 59 GND GND 60 HDA_SYNC/I2S_WS[7] SMB_CLK [4,6,7,8,9,10] 61 HDA_SYNC/AC97_SYNC/I2S_WS SMB_CLK/GP1_I2C_CLK 62 HDA_RST#/I2S_RST#[7] SMB_DAT [4,6,7,8,9,10] 63 HDA_RST#/AC97_RST#/I2S_RST# SMB_DAT/GP1_I2C_DAT 64 HDA_BITCLK/I2S_CLK[7] SMB_ALERT# [6] 65 HDA_BITCLK /AC97_BCLK/I2S_CLK SMB_ALERT# 66 HDA_SDI/I2S_SDI[7] I2C_CLK [6,7] 67 HDA_SDI/AC97_SDI/I2S_SDI GP0_I2C_CLK 68 HDA_SDO/I2S_SDO[7] I2C_DAT [6,7] 69 HDA_SDO/AC97_SDO/I2S_SDO GP0_I2C_DAT 70 THRM#[6] WDTRIG# [6] 71 THRM# WDTRIG# 72 THRMTRIP#[6] WDOUT [6] 73 THRMTRIP# WDOUT 74 75 GND GND 76 USB_P7-/USB_SSTX0-[17] USB_P6-/USB_SSRX0- [17] 77 USBP7-/USB_SSTX0- USBP6-/USB_SSRX0- 78 USB_P7+/USB_SSTX0+[17] USB_P6+/USB_SSRX0+ [17] 79 USBP7+/USB_SSTX0+ USBP6+//USB_SSRX0+ 80 USB_6_7_OC#[16] USB_4_5_OC# [17] 81 USB_6_7_OC# USB_4_5_OC# 82 USB_P5-/USB_SSTX1-[17] USB_P4-/USB_SSRX1- [17] 83 USBP5-/USB_SSTX1- USBP4-/USB_SSRX1- 84 USB_P5+/USB_SSTX1+[17] USB_P4+/USB_SSRX1+ [17] 85 USBP5+/USB_SSTX1+ USBP4+/USB_SSRX1+ 86 USB_2_3_OC#[17] USB_0_1_OC# [16] 87 USB_2_3_OC# USB_0_1_OC# 88 USB_P3-[17] USB_P2- [5] 89 USBP3- USBP2- 90 USB_P3+[17] USB_P2+ [5] 91 USBP3+ USBP2+ 92 USB_VBUS[16] USB1_ID [16] 93 USB_VBUS USB_ID 94 USB_P1-[16] USB_P0- [16] 95 USBP1- USBP0- 96 USB_P1+[16] USB_P0+ [16] 97 USBP1+ USBP0+ 98 99 GND GND 100 eDP0_TX0+/LVDS_A0+[12] eDP1_TX0+/LVDS_B0+ [12] 101 eDP0_TX0+/LVDS_A0+ eDP1_TX0+/LVDS_B0+ 102 eDP0_TX0-/LVDS_A0-[12] eDP1_TX0-/LVDS_B0- [12] 103 eDP0_TX0-/LVDS_A0- eDP1_TX0-/LVDS_B0- 104 eDP0_TX1+/LVDS_A1+[12] eDP1_TX1+/LVDS_B1+ [12] 105 eDP0_TX1+/LVDS_A1+ eDP1_TX1+/LVDS_B1+ 106 eDP0_TX1-/LVDS_A1-[12] eDP1_TX1-/LVDS_B1- [12] 107 eDP0_TX1-/LVDS_A1- eDP1_TX1-/LVDS_B1- 108 eDP0_TX2+/LVDS_A2+[12] eDP1_TX2+/LVDS_B2+ [12] 109 eDP0_TX2+/LVDS_A2+ eDP1_TX2+/LVDS_B2+ 110 eDP0_TX2-/LVDS_A2-[12] eDP1_TX2-/LVDS_B2- [12] 111 eDP0_TX2-/LVDS_A2- eDP1_TX2-/LVDS_B2- 112 LVDS_PPEN[12] LVDS_BLEN [12] 113 LVDS_PPEN LVDS_BLEN 114 eDP0_TX3+/LVDS_A3+[12] eDP1_TX3+/LVDS_B3+ [12] 115 eDP0_TX3+/LVDS_A3+ eDP1_TX3+/LVDS_B3+ 116 eDP0_TX3-/LVDS_A3-[12] eDP1_TX3-/LVDS_B3- [12] 117 eDP0_TX3-/LVDS_A3- eDP1_TX3-/LVDS_B3- 118 119 GND GND 120 eDP0_AUX+/LVDS_A_CLK+[12] eDP1_AUX+/LVDS_B_CLK+ [12] 121 eDP0_AUX+/LVDS_A_CLK+ eDP1_AUX+/LVDS_B_CLK+ 122 eDP0_AUX-/LVDS_A_CLK-[12] eDP1_AUX-/LVDS_B_CLK- [12] 123 eDP0_AUX-/LVDS_A_CLK eDP1_AUX-/LVDS_B_CLK- 124 GP_1-Wire_Bus [6] 125 LVDS_BLT_CTRL GP_1-Wire_Bus 126 LVDS_DID_DAT[6,12] eDP0_HPD# [12] 127 LVDS_DID_DAT/GP2_I2C_DAT LVDS_BLC_DAT/eDP0_HPD# 128 LVDS_DID_CLK[6,12] LVDS_DID_CLK/GP2_I2C_CLK LVDS_BLC_CLK/eDP1_HPD# eDP1_HPD# [12] LVDS_BLT_CTRL/PWM0 BECHS -0.5-230-S9-*F-R-EDC CN1B 129 130 CAN_TX[13] CAN_RX [13] 131 CAN_TX CAN_RX 132 DP_LANE3+/TMDS_CLK+[11] RSVD_132 [11] 133 DP_LANE3+/TMDS_CLK+ RSVD (Differential) 134 DP_LANE3-/TMDS_CLK-[11] RSVD_134 [11] 135 DP_LANE3-/TMDS_CLK RSVD (Differential) 136 137 GND GND 138 DP_LANE1+/TMDS_LANE1+[11] DP_AUXp [11] 139 DP_LANE1+/TMDS_LANE1+ DP_AUX+ 140 DP_LANE1-/TMDS_LANE1-[11] DP_AUXn [11] 141 DP_LANE1-/TMDS_LANE1- DP_AUX- 142 143 GND GND 144 DP_LANE2+/TMDS_LANE0+[11] RSVD_144 [11] 145 DP_LANE2+/TMDS_LANE0 RSVD (Differential) 146 DP_LANE2-/TMDS_LANE0-[11] RSVD_146 [11] 147 DP_LANE2-/TMDS_LANE0- RSVD (Differential) 148 149 GND GND 150 DP_LANE0+/TMDS_LANE2+[11] HDMI_CTRL_DAT [11] 151 DP_LANE0+/TMDS_LANE2+ HDMI_CTRL_DAT 152 DP_LANE0-/TMDS_LANE2-[11] HDMI_CTRL_CLK [11] 153 DP_LANE0-/TMDS_LANE2- HDMI_CTRL_CLK 154 DP_HDMI_HPD#[11] DP_HPD# [11] 155 HDMI_HPD# DP_HPD# 156 PCIE_CLK_REF+[4] PCIE_WAKE# [8,9,10] 157 PCIE_CLK_REF+ PCIE_WAKE# 158 PCIE_CLK_REF-[4] PLT_RST# [4] 159 PCIE_CLK_REF- PLT_RST# 160 161 GND GND 162 PCIE3_TX+[5] PCIE3_RX+ [5] 163 PCIE3_TX+ PCIE3_RX+ 164 PCIE3_TX-[5] PCIE3_RX- [5] 165 PCIE3_TX- PCIE3_RX- 166 167 GND GND 168 PCIE2_TX+[5] PCIE2_RX+ [5] 169 PCIE2_TX+ PCIE2_RX+ 170 PCIE2_TX-[5] PCIE2_RX- [5] 171 PCIE2_TX- PCIE2_RX- 172 UART_TX[22] UART_RTS# [22] 173 UART0_TX UART0_RTS# 174 PCIE1_TX+[5] PCIE1_RX+ [5] 175 PCIE1_TX+ PCIE1_RX+ 176 PCIE1_TX-[5] PCIE1_RX- [5] 177 PCIE1_TX- PCIE1_RX- 178 UART_RX[22] UART_CTS# [22] 179 UART0_RX UART0_CTS# 180 PCIE0_TX+[5] PCIE0_RX+ [5] 181 PCIE0_TX+ PCIE0_RX+ 182 PCIE0_TX-[5] PCIE0_RX- [5] 183 PCIE0_TX- PCIE0_RX- 184 185 GND GND 186 LPC_AD0[6,13,14,15] LPC_AD1 [6,13,14,15] 187 LPC_AD0/GPIO0 LPC_AD1/GPIO1 188 LPC_AD2[6,13,14,15] LPC_AD3 [6,13,14,15] 189 LPC_AD2/GPIO2 LPC_AD3/GPIO3 190 LPC_FRAME# [6,13,14,15] 191 LPC_CLK/GPIO4 LPC_FRAME#/GPIO5 192 SERIRQ[6,14,15] LPC_LDRQ# [6,14] 193 SERIRQ/GPIO6 LPC_LDRQ#/GPIO7 194 VCC_RTC[18] 195 VCC_RTC SPKR / GP_PWM_OUT2 196 197 FAN_TACHOIN/GP_TIMER_IN FAN_PWMOUT 198 199 GND GND 200 SPI_MOSI[6] SPI_CS0# [6] 201 SPI_MOSI SPI_CS0# 202 SPI_MISO[6] SPI_CS1# SPI_CS1# [6] +5V_SB_Q7 203 SPI_MISO 204 +5V_SB_Q7 SPI_SCK[6] JTAG_TRST# [22] 205 SPI_SCK MFG_NC4/JTAG_TRST# 206 207 VCC_5V_SB VCC_5V_SB 208 JTAG_TCK[22] MFG_NC2 [22] 209 MFG_NC0/JTAG_TCK MFG_NC2/JTAG_TDI/DBG_RX 210 MFG_NC1[22] JTAG_TMS [22] 211 MFG_NC1/JTAG_TDO/DBG_TX MFG_NC3/JTAG_TMS 212 VCC VCC SPKR/PWM2 213 214 FAN_PWMOUT/PWM1 215 VCC VCC 216 LPC_CLK 217 VCC VCC 218 FAN_TACHOIN/TIMER_IN 219 VCC VCC 220 221 VCC VCC 222 223 VCC VCC 224 225 VCC VCC 226 +5V_S_Q7 227 VCC VCC 228 +5V_S_Q7 229 VCC VCC 230 VCC VCC BECHS -0.5-230-S9-*F-R-EDC

Qseven Design Guide Page 31 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.2.1 Signal Descriptions The following section describes the signals on Qseven MXM connector that are provided over the edge-fingers of the Qseven® module. Refer to the Qseven Specification for more details. The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at a high voltage level. Differential pairs are indicated by trailing '+' and '-' signs for the positive or negative signal. All required pull-ups or pull-down resistors shall be implemented on the Qseven® module. This ensures that none of the signals that are not used will be left floating. Termination of all signals will be always on the module unless explicitly otherwise noted. Please note Figure 3-2 “PCI Express Termination default Configurations” in chapter 3.3. The following terminology is used to describe the signals types in the I/O columns for the tables located below.

Table 3-2 Signal Tables Terminology Descriptions

Term Description I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I 3.3V Module Input 3.3V tolerant I 5V Module Input 5V tolerant I/O 3.3VSB Bi-directional 3.3V tolerant active during suspend and running state.

IOL Module Output low current. The IOL is the maximum output low current the module must be able to drive to an external circuitry.

IIL Module Input low current. The IIL is the maximum input low current that must be provided to the Qseven® module via external circuitry in order to guarantee a proper logic low level of the signal. O 3.3V Module Output 3.3V signal level O 5V Module Output 5V signal level OD Module Open drain output OC Open collector P Power input/output PP Push Pull PDS Pull-down strap REF Module Reference voltage output. May be sourced from a module power plane. DDC Display Data Channel PCIE In compliance with PCI Express Base Specification, Revision 1.0a USB In compliance with the Universal Serial Bus Specification, Revision 2.0 GBE In compliance with IEEE 802.3ab 1000Base-T Gigabit Ethernet SATA In compliance with Serial ATA specification, Revision 1.0a LVDS Low-Voltage Differential Signaling differential pair signals. In compliance with the LVDS Owner's Manual 4.0. TMDS Transition Minimized Differential Signaling differential pair signals. In compliance with the Digital Visual Interface (DVI) Specification 1.0. CMOS Logic input or output.

3.3.1 PCI Express Interface Signals PCI Express provides a scalable, high-speed, serial I/O point-to-point bus connection. A PCI Express lane consists of dual simplex channels, each implemented as a low-voltage differentially driven transmit pair and receive pair. They are used for simultaneous transmission in each direction. The bandwidth of a PCI Express link can be scaled by adding signal pairs to form multiple lanes between two devices. The Qseven® modules can optionally provide configurations with x1 and x4 link widths. Each single lane has a raw data transfer rate of 2.5Gbps @ 1.25GHz. The PCI Express interface of the Qseven® module consists of a minimum of 0 [ARM] resp. 1 [x86] and up to 4 lanes, each with a receive and transmit differential signal pair designated from PCIE0_RX (+ and -) to PCIE3_RX (+ and -) and correspondingly from PCIE0_TX (+ and -) to PCIE3_TX (+ and -). According to the PCI Express specification, these four lanes can be configured as several PCI Express x1 links or to a combined x4 link. These configuration possibilities are based on the Qseven® module's chipset capabilities. Refer to the vendor specific Qseven® module documentation for the module that you are using for additional information about this subject. Table 3-3 Signal Definition PCI Express

Signal Pin# Description I/O Type IOL/IIIL I/O PCIE0_RX+ 180 PCI Express channel 0, Receive Input differential pair. PCIE I PCIE0_RX- 182 PCIE0_TX+ 179 PCI Express channel 0, Transmit Output differential pair. PCIE O PCIE0_TX- 181 PCIE1_RX+ 174 PCI Express channel 1, Receive Input differential pair. PCIE I PCIE1_RX- 176 PCIE1_TX+ 173 PCI Express channel 1, Transmit Output differential pair. PCIE O PCIE1_TX- 175 PCIE2_RX+ 168 PCI Express channel 2, Receive Input differential pair. PCIE I PCIE2_RX- 170 PCIE2_TX+ 167 PCI Express channel 2, Transmit Output differential pair. PCIE O PCIE2_TX- 169 PCIE3_RX+ 162 PCI Express channel 3, Receive Input differential pair. PCIE I PCIE3_RX- 164 PCIE3_TX+ 161 PCI Express channel 3, Transmit Output differential pair. PCIE O PCIE3_TX- 163 PCIE_CLK_REF+ 155 PCI Express Reference Clock for Lanes 0 to 3. PCIE O PCIE_CLK_REF- 157 PCIE_WAKE# 156 PCI Express Wake Event: Sideband wake signal asserted CMOS 3.3V ≥ 5 mA I by components requesting wakeup. Suspend PCIE_RST# 158 Reset Signal for external devices. CMOS 3.3V max. 1 mA O

Note There are a maximum of 4 PCI Express TX and RX differential pairs supported on the Qseven® module standard. Depending on the features supported by the Qseven® module and the core logic chipset used, these lines may be used to form x1 or x4 PCI Express links. The documentation for the Qseven® module shall clearly identify, which PCI Express link configuration or configurations (in the case that these can be programmed in the core logic chipset) are supported.

Qseven Design Guide Page 33 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.3.2 PCI Express Implementation Guidelines All required pull-ups or pull-down resistors shall be implemented on the Qseven® module. This ensures that none of the signals that are not used will be left floating. Figure 3-4 shows the two standard configurations: “Slot” and “Device Down”.

Figure 3-4 PCI Express Termination Default Configurations

a) Slot Configuration

b) Device Down Configuration

3.3.2.1 PCI Express Reference Clock PCI Express does not specify the external clock source for PCI Express devices. It only provides a 100MHz differential Serial Reference Clock (SRC), which can be used by the internal PLL of the PCI Express device to generate the required 1.25GHz clock. The corresponding Serial Reference Clock signals 'PCI_CLK_REF+' and 'PCI_CLK_REF-' can be found on the Qseven® module connector on pins 155 and 157. In an application where more than one PCI Express slot or device is needed, the differential Serial Reference Clock signal must be replicated by using a buffer. Figure 3-3 shows an example implementing the ICS9DB833 PCI Express from Integrated Circuit Systems (ICS) (http://www.idt.com).

Qseven Design Guide Page 34 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. This PCIe compliant clock buffer provides eight Serial Reference Clock outputs including clock request functionality. This circuit is also used on the Qseven® 2.0 evaluation carrier board.

The PCI Express architecture has specified the clock signal to be embedded in the serial data stream for synchronization of the two devices. For carrier board designs that implement PCI Express connectors for external add-in card devices, the SRC is required on the connector interface. External add-in cards may utilize this SRC differential signal pair to reduce jitter for maintaining maximum data transfer rate. For detailed information about this subject refer to chapter 2.1 of the 'PCI Express™ Card Electromechanical Specification Revision 1.1'.

Figure 3-5 PCI Express Clock Buffer Example

+3.3V_S

U48 R12 +3.3V_S +3.3V_S 2 1 27 PD# R21 R-4K7 C374 C375 C376 C377 C378 C371 C372 C373 3 VDD CKPWRGD_PDB 8 VDD 26 R-10K 1 6 SMB_DAT 3,6,7,8,9,10 CC-100n CC-100n CC-100n CC-100n CC-100n CC-100n CC-100n CC-100n 13 VDD SDATA 25 Q1A 16 VDD SCLK 2N7002DW 21 VDD 7 24 VDD NC +3.3V_S 28 VDD VDD 23 DIFF5 R10

22 5 DIFF5# 20 33 DIFF4 19 PEG_CLK+ 8 R-10K 4 3 GND DIFF4# PEG_CLK- 8 SMB_CLK 3,6,7,8,9,10 18 Q1B 29 DIFF3 17 mPCIE_CLK+ 10 PCIE_CLK_REF+3 2N7002DW 30 DIFFIN DIFF3# mPCIE_CLK- 10 PCIE_CLK_REF-3 DIFFIN# 14 DIFF2 15 PCIE_CLK_0+ 9 31 DIFF2# PCIE_CLK_0- 9 32 OE0 11 2 OE1 DIFF1 12 PCIE_CLK_2+ 9 4 OE2 DIFF1# PCIE_CLK_2- 9 5 OE3 9 R388 R-1K 6 OE4 DIFF0 10 PCIE_CLK_1+ 9 OE5 DIFF0# PCIE_CLK_1- 9

Si53156 +3.3V_S

R389 6

Q28A R-10K 2 2N7002DW CK_REQ_1#9 1

+3.3V_S

R390 3

Q28B R-10K 5 2N7002DW CK_REQ_2#9 4

+3.3V_S

R391 6

Q29A R-10K 2 2N7002DW CK_REQ_0#9 1

+3.3V_S

R392 3

Q29B R-10K 5 2N7002DW CK_REQ_mPCIE#10 4

+3.3V_S

R393 6

Q30A R-10K 2 2N7002DW CK_REQ_PEG#8 1

Note

Termination of all signals will be always on the module unless explicitly otherwise noted. Please note Figure 3-4 “PCI Express Termination default Configurations”.

Qseven Design Guide Page 35 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.3.2.2 PCI Express Reset The Qseven® module provides one PCI Express Reset signal on pin 158 of the Qseven® connector(referenced as PLT_RST#) in the example schematics. It is recommended to use a buffer to replicate the Reset signal on the carrier board when more than one PCI Express slot or device is needed. Figure 3-6 shows a possible implementation example.

Figure 3-6 PCI Express Reset Buffer Example

+3.3V_S U4 C395 CC-100n 8 4 VCC GND

1 7 PLT_RST#3 R379 1A 1Y LPC_CONN_RST# 6 3 5 2A 2Y LPC_RST# 14 6 2 R-100K 3A 3Y CPLD_RST# 13

SN74LVC3G34DCURG4

+3.3V_S U6 C396 CC-100n 8 4 VCC GND

1 7 1A 1Y LPC_RST_XR28V384 14 3 5 2A 2Y mPCIe_RST# 10 6 2 3A 3Y PEG_RST# 8

SN74LVC3G34DCURG4

+3.3V_S U59 C397 CC-100n 8 4 VCC GND

1 7 SATA_ACT#3 1A 1Y SATA_ACT#_BF 18 3 5 2A 2Y SDVO_CON_RST# 11 6 2 3A 3Y LVDS_RST# 12

SN74LVC3G34DCURG4

+3.3V_S U60 C398 CC-100n 8 4 VCC GND

1 7 1A 1Y PCIe_0_RST# 9 3 5 2A 2Y PCIe_1_RST# 9 6 2 3A 3Y PCIe_2_RST# 9

SN74LVC3G34DCURG4

3.3.2.3 PCI Express Lane Configurations And Multiplexing The lane configuration possibilities of the PCI Express interface of a Qseven® module is dependent on the module's chipset. If an application requires an x4 PCI Express link, it may be necessary to implement a hardware strap onto the carrier board in order to tell the module's chipset to switch the PCI Express lanes 0-3 from quad x1 to single x4 mode. The configuration possibilities and implementation requirements may differ depending on the module's chipset. Refer to the Qseven module's user's guide for additional information about this subject.

To provide maximum configuration flexibility the Qseven® V2.0 Reference Carrier Board is using a multiplexer for management and configuration of the four PCI Express lanes from the module.

PlaceP near component coupling capacitor +3.3V_S

C40 C41 C42 C43 C44 C45 C46 C47

CC-100n CC-100n CC-100n CC-100n CC-100n CC-100n CC-100n CC-100n 9 1 6 1 4 9 1 U5 9 1 2 2 3 3 3 4 C C C C C C C C C C C C C C C C V V V V V V V V

4 PCIE_TX_1- 9 2 AOUTB- 3 PCIE2_TX-3 PCIE_TX_1+ 9 1 AIN- AOUTB+ PCIE2_TX+3 AIN+ 8 PCIE_RX_1- 9 6 BOUTB- 7 PCIE_RX_1+ 9 PCIE2_RX-3 5 BIN- BOUTB+ PCIE2_RX+3 BIN+ 13 PCIE_TX_2- 9 11 COUTB- 12 PCIE3_TX-3 PCIE_TX_2+ 9 10 CIN- COUTB+ PCIE3_TX+3 CIN+ 17 PCIE_RX_2- 9 15 DOUTB- 16 PCIE_RX_2+ 9 PCIE3_RX-3 14 DIN- DOUTB+ PCIE3_RX+3 DIN+ 23 PEG3_RX- 8 DOUTA- 24 DOUTA+ PEG3_RX+ 8 27 PEG3_TX- 8 20 COUTA- 28 PEG3_TX+ 8 40 XSD23 COUTA+ XSD01 32 PEG2_RX- 8 BOUTA - 33 BOUTA+ PEG2_RX+ 8 36 PEG2_TX- 8 AOUTA- 37 AOUTA+ PEG2_TX+ 8 SEL 30 SEL D N G _ D D D D D D D D N N N N N N N A G G G G G G G P +3.3V_S CBTL04083B 8 2 5 9 5 8 2 3 1 2 2 2 3 3 4 4

R55

P2 JP1 R-10K SHORTING_PLUG 1 SEL

2 set no jumper for PCIe x1 (default) Place near component coupling capacitor JP-2X1 set jumper 1-2 for PEG +3.3V_S

C53 C54 C55 C56 C57 C58 C59 C60

CC-100n CC-100n CC-100n CC-100n CC-100n CC-100n CC-100n CC-100n 9 1 6 1 4 9 1 U7 9 1 2 2 3 3 3 4 C C C C C C C C C C C C C C C C V V V V V V V V

4 mPCIE_TX- 10 2 AOUTB- 3 PCIE0_TX-3 mPCIE_TX+ 10 1 AIN- AOUTB+ PCIE0_TX+3 AIN+ 8 mPCIE_RX- 10 6 BOUTB- 7 mPCIE_RX+ 10 PCIE0_RX-3 5 BIN- BOUTB+ PCIE0_RX+3 BIN+ 13 PCIE_TX_0- 9 11 COUTB- 12 PCIE1_TX-3 PCIE_TX_0+ 9 10 CIN- COUTB+ PCIE1_TX+3 CIN+ 17 PCIE_RX_0- 9 15 DOUTB- 16 PCIE_RX_0+ 9 PCIE1_RX-3 14 DIN- DOUTB+ PCIE1_RX+3 DIN+ 23 PEG1_RX- 8 DOUTA- 24 DOUTA+ PEG1_RX+ 8 27 PEG1_TX- 8 20 COUTA- 28 PEG1_TX+ 8 40 XSD23 COUTA+ XSD01 32 PEG0_RX- 8 BOUTA - 33 BOUTA+ PEG0_RX+ 8 36 PEG0_TX- 8 AOUTA- 37 AOUTA+ PEG0_TX+ 8 SEL 30 SEL D N G _ D D D D D D D D N N N N N N N A G G G G G G G P CBTL04083B 8 2 5 9 5 8 2 3 1 2 2 2 3 3 4 4

Qseven Design Guide Page 37 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.3.2.4 PCI Express x1, x4 and x16 Connectors Figure 3-8 illustrates the pinout definition for the standard x1 PCI Express connector as it has been implemented on the Qseven V2.0 Reference Carrier Board. It utilizes PCI Express lane 0.

Figure 3-8 PCI Express x1 Connector

+12V_S

+3.3V_A +3.3V_S

CN15 R106 B1 A1 +12V PRSNT#1 B2 A2 R-0 B3 +12V +12V A3 B4 RSVD0 +12V A4 GND GND SMB_CLK[3,4,6,8,10,13] SMB_CLK B5 A5 SMB_DAT B6 SMCLK JTAG2 A6 SMB_DAT[3,4,6,8,10,13] B7 SMDAT JTAG3 A7 B8 GND JTAG4 A8 B9 +3.3V JTAG5 A9 B10 JTAG1 +3.3V A10 B11 3.3Vaux +3.3V A11 PCIE_WAKE#[3,8,10] WAKE# PWRGD PCIe_0_RST# [4]

B12 A12 B13 RSVD1 GND A13 PCIE_CLK_0+ [4] B14 GND REFCLK+ A14 PCIE_CLK_0- [4] PCIE_TX_0+[5] B15 HSOp(0) REFCLK- A15 PCIE_TX_0-[5] B16 HSOn(0) GND A16 B17 GND HSIp(0) A17 PCIE_RX_0+ [5] CK_REQ_0#[4] PRSNT#2 HSIn(0) PCIE_RX_0- [5]

B18 1 2 A18

GND X X GND PCIE_X1 1 2 X X

+12V_S

C361 C121 C122 C123 C124 C125 C126 C127

CE-220u/35V CC-100n/25V CC-100n/25V CC-100n/25V CC-100n/25V CC-100n/25V CC-100n/25V CC-100n/25V

Note

No crossing of TX and RX to socket. Crossing of TX and RX only when PCIe Device is soldered down on the board

Figure 3-9 illustrates the pinout definition for the standard x16 PCI Express connector as it has has been implemented on the Qseven® V2.0 evaluation carrier board. It utilizes PCI Express lanes 0 to 3.

+12V_S +3.3V_S +12V_S +3.3V_A CN14 R101 R-0 A1 B1 +3.3V_S A2 PRSNT1# +12V1 B2 A3 +12V4 +12V2 B3 +3.3V_S A4 +12V5 +12V3 B4 R102 R-4K7 A5 GND6 GND1 B5 SMB_CLK [3,4,6,9,10,13] R104 R-4K7 A6 JTAG2 SMCLK B6 SMB_DAT [3,4,6,9,10,13] A7 JTAG3 SMDAT B7 R103 R-4K7 A8 JTAG4 GND2 B8 A9 JTAG5 +3.3V1 B9 R105 R-4K7 A10 +3.3V2 JTAG1 B10 A11 +3.3V3 3.3VAUX B11 PEG_RST#[4] PWRGD WAKE# PCIE_WAKE# [3,9,10] Key A12 B12 A13 GND7 RSVD2 B13 PEG_CLK+[4] A14 REFCLK+ GND3 B14 PEG_CLK-[4] PEG0_TX+ [5] A15 REFCLK- HSOP_0 B15 PEG0_TX- [5] A16 GND8 HSON_0 B16 PEG0_RX+[5] A17 HSIP_0 GND4 B17 PEG0_RX-[5] A18 HSIN_0 PRSNT2# B18 A19 GND9 GND5 B19 PEG1_TX+ [5] A20 RSVD5 HSOP_1 B20 PEG1_TX- [5] A21 GND16 HSON_1 B21 PEG1_RX+[5] A22 HSIP_1 GND10 B22 PEG1_RX-[5] A23 HSIN_1 GND11 B23 PEG2_TX+ [5] A24 GND17 HSOP_2 B24 PEG2_TX- [5] A25 GND18 HSON_2 B25 PEG2_RX+[5] A26 HSIP_2 GND12 B26 PEG2_RX-[5] A27 HSIN_2 GND13 B27 PEG3_TX+ [5] A28 GND19 HSOP_3 B28 PEG3_TX- [5] A29 GND20 HSON_3 B29 PEG3_RX+[5] A30 HSIP_3 GND14 B30 PEG3_RX-[5] A31 HSIN_3 RSVD3 B31 A32 GND21 PRSNT2#1 B32 CK_REQ_PEG# [4] A33 RSVD6 GND15 B33 A34 RSVD7 HSOP_4 B34 A35 GND30 HSON_4 B35 A36 HSIP_4 GND22 B36 A37 HSIN_4 GND23 B37 A38 GND31 HSOP_5 B38 A39 GND32 HSON_5 B39 A40 HSIP_5 GND24 B40 A41 HSIN_5 GND25 B41 A42 GND33 HSOP_6 B42 A43 GND34 HSON_6 B43 A44 HSIP_6 GND26 B44 A45 HSIN_6 GND27 B45 A46 GND35 HSOP_7 B46 A47 GND36 HSON_7 B47 A48 HSIP_7 GND28 B48 A49 HSIN_7 PRSNT2#2 B49 A50 GND37 GND29 B50 A51 RSVD8 HSOP_8 B51 +3.3V_A A52 GND54 HSON_8 B52 A53 HSIP_8 GND38 B53 A54 HSIN_8 GND39 B54 GND55 HSOP_9 A55 B55 C103 C104 C105 C106 A56 GND56 HSON_9 B56 HSIP_9 GND40 A57 B57 CC-10u/6.3V CC-10u/6.3V CC-100n CC-100n A58 HSIN_9 GND41 B58 A59 GND57 HSOP_10 B59 A60 GND58 HSON_10 B60 A61 HSIP_10 GND42 B61 A62 HSIN_10 GND43 B62 A63 GND59 HSOP_11 B63 +3.3V_S A64 GND60 HSON_11 B64 A65 HSIP_11 GND44 B65 A66 HSIN_11 GND45 B66 A67 GND61 HSOP_12 B67 C107 C108 C109 C110 A68 GND62 HSON_12 B68 A69 HSIP_12 GND46 B69 CC-47u/10V CC-47u/10V CC-100n CC-100n A70 HSIN_12 GND47 B70 A71 GND63 HSOP_13 B71 A72 GND64 HSON_13 B72 A73 HSIP_13 GND48 B73 HSIN_13 GND49 A74 B74 +12V_S A75 GND65 HSOP_14 B75 A76 GND66 HSON_14 B76 A77 HSIP_14 GND50 B77 HSIN_14 GND51 A78 B78 C111 C112 C113 C114 C115 C116 A79 GND67 HSOP_15 B79 A80 GND68 HSON_15 B80 1 2 CC-22u/25V CC-22u/25V CC-22u/25V CC-22u/25V CC-100n/25V CC-100n/25V HSIP_15 GND52 A81 E E B81 L HSIN_15 L PRSNT2#3 O A82 O B82

GND69 H H RSVD4 2-1612163-4 2 1 E E L L O O H H

PCIeX x16 Note

No crossing of TX and RX to socket. Crossing of TX and RX only when PCIe Device is soldered down on the board

Signal fields in Table 3-4 that do not have any light grey shading describe the pinout for the PCI Express x1 slot (1 PCI Express Lane) and the signal fields marked with light grey indicate the additional signals needed on a PCI Express x4 connector (4 PCI Express Lanes), the fields marked with bold face characters indicate the additional signals required on a PCI Express x16 connector.

Pin Signal Description Pin Signal Description 1B +12V 12V power 1A PRSNT1#* Hot-Plug presence detected 2B +12V 12V power 2A +12V 12V power 3B +12V 12V power 3A +12V 12V power 4B GND Ground 4A GND Ground 5B SMB_CLK* SMBus Clock 5A JTAG2* TCK - Boundary Scan Test Clock 6B SMB_DAT* SMBus Data 6A JTAG3* TDI – Boundary Scan Test Data Input 7B GND Ground 7A JTAG4* TDO - Boundary Scan Test Data Output 8B +3.3V 3.3V power 8A JTAG5* TMS - Boundary Scan Test Mode Select 9B JTAG1* TRST# - Boundary Scan Test 9A +3.3V 3.3V power Reset 10B +3.3Vaux* 3.3V auxiliary power 10A +3.3V 3.3V power 11B PCIE_WAKE#* Link Reactivation 11A PCIE_RST#* Reset Mechanical Key 12B RSVD Reserved 12A GND Ground 13B GND Ground 13A PCIE_CLK_R Reference Clock differential pair EF+* positive signal 14B PCIE0_TX+ Transmitter differential pair 14A PCIE_CLK_R Reference Clock differential pair positive signal, Lane 0 EF-* negative signal 15B PCIE0_TX- Transmitter differential pair 15A GND Ground negative signal, Lane 0 16B GND Ground 16A PCIE0_RX+ Receiver differential pair positive signal, Lane 0 17B PRSNT2#* Hot-Plug presence detected 17A PCIE0_RX- Receiver differential pair negative signal, Lane 0 18B GND Ground 18A GND Ground 19B PCIE1_TX+ Transmitter differential pair 19A RSVD Reserved positive signal, Lane 1 20B PCIE1_TX- Transmitter differential pair 20A GND Ground negative signal, Lane 1 21B GND Ground 21A PCIE1_RX+ Receiver differential pair positive signal, Lane 1 22B GND Ground 22A PCIE1_RX- Receiver differential pair negative signal, Lane 1 23B PCIE2_TX+ Transmitter differential pair 23A GND Ground positive signal, Lane 2 24B PCIE2_TX- Transmitter differential pair 24A GND Ground negative signal, Lane 2 25B GND Ground 25A PCIE2_RX+ Receiver differential pair positive signal, Lane 2 26B GND Ground 26A PCIE2_RX- Receiver differential pair negative signal, Lane 2 27B PCIE3_TX+ Transmitter differential pair 27A GND Ground positive signal, Lane 3

Qseven Design Guide Page 40 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Pin Signal Description Pin Signal Description 28B PCIE3_TX- Transmitter differential pair 28A GND Ground negative signal, Lane 3 29B GND Ground 29A PCIE3_RX+ Receiver differential pair positive signal, Lane 3 30B RSVD Reserved 30A PCIE3_RX- Receiver differential pair negative signal, Lane 3 31B PRSTN2#1* Hot-Plug presence detected 31A GND Ground 32B GND Ground 32A RSVD Reserved 33B n/c Not Connected 33A RSVD Reserved 34B n/c Not Connected 34A GND Ground 35B GND Ground 35A n/c Not Connected 36B GND Ground 36A n/c Not Connected 37B n/c Not Connected 37A GND Ground 38B n/c Not Connected 38A GND Ground 39B GND Ground 39A n/c Not Connected 40B GND Ground 40A n/c Not Connected 41B n/c Not Connected 41A GND Ground 42B n/c Not Connected 42A GND Ground 43B GND Ground 43A n/c Not Connected 44B GND Ground 44A n/c Not Connected 45B n/c Not Connected 45A GND Ground 46B n/c Not Connected 46A GND Ground 47B GND Ground 47A n/c Not Connected 48B PRSTN2#2* Hot-Plug presence detected 48A n/c Not Connected 49B GND Ground 49A GND Ground 50B n/c Not Connected 50A RSVD Reserved 51B n/c Not Connected 51A GND Ground 52B GND Ground 52A n/c Not Connected 53B GND Ground 53A n/c Not Connected 54B n/c Not Connected 54A GND Ground 55B n/c Not Connected 55A GND Ground 56B GND Ground 56A n/c Not Connected 57B GND Ground 57A n/c Not Connected 58B n/c Not Connected 58A GND Ground 59B n/c Not Connected 59A GND Ground 60B GND Ground 60A n/c Not Connected 61B GND Ground 61A n/c Not Connected 62B n/c Not Connected 62A GND Ground 63B n/c Not Connected 63A GND Ground 64B GND Ground 64A n/c Not Connected 65B GND Ground 65A n/c Not Connected 66B n/c Not Connected 66A GND Ground

Qseven Design Guide Page 41 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Pin Signal Description Pin Signal Description 67B n/c Not Connected 67A GND Ground 68B GND Ground 68A n/c Not Connected 69B GND Ground 69A n/c Not Connected 70B n/c Not Connected 70A GND Ground 71B n/c Not Connected 71A GND Ground 72B GND Ground 72A n/c Not Connected 73B GND Ground 73A n/c Not Connected 74B n/c Not Connected 74A GND Ground 75B n/c Not Connected 75A GND Ground 76B GND Ground 76A n/c Not Connected 77B GND Ground 77A n/c Not Connected 78B n/c Not Connected 78A GND Ground 79B n/c Not Connected 79A GND Ground 80B GND Ground 80A n/c Not Connected 81B PRSTN2#3* Hot-Plug presence detected 81A n/c Not Connected 82B RSVD Reserved 82A GND Ground

Note

* Auxiliary signals. These signals are not required by the PCI Express Architecture.

3.3.2.5 PCI Express Power Requirements To utilize the full functionality of PCI Express devices on the Qseven® carrier board, some additional supply voltages may be necessary beside the standard supply voltages (see table 3-5).

When an external PCI Express Mini Card device will be implemented on the carrier board, an additional 1.5V supply voltage is required by the appropriate card sockets. The voltage regulator must be designed to meet the power requirements of the connected devices.

Note

Refer to the reference schematics of the Qseven® evaluation carrier board for an example of how to implement a 1.5V voltage regulator.

The PCI Express specification defines maximum power requirements for the different PCI Express connectors and/or devices. The power supply for the carrier board must be designed to meet these maximum power requirements. Table 3-5 shows the maximum current consumption defined for the different types of PCI Express connectors.

Power Rail PCIe x1, x4 or x8 PCIe x16 PCIe Mini Card 2.0 Connector Connector Connector 12V 2.1A @ 1000uF bulk 5.5A @ 2000uF bulk 3.3V 3.0A @ 1000uF bulk 3.0A @ 1000uF bulk 3.3V Standby 375mA @ 150uF bulk 375mA @ 150uF bulk Aux 1.1A / 2.75A (peak) 1.5V 500mA

Implementing PCI Express connectors on the carrier board requires distinctive decoupling of the connector supply voltages to reduce possible voltage drops and to provide an AC return path in a manner consistent with high-speed signaling techniques. Decoupling capacitors should be placed as close as possible to the power pins of the connectors. Table 3-6 shows the minimum requirements for power decoupling of the different power pin types of each PCI Express connector type.

Table 3-6 PCIe Power Decoupling Requirements

Power Pin Type PCIe x1, x4 or x8 PCIe x16 PCIe Mini Card 2.0 Connector Connector Connector 12V 1x 22µF, 2x 100nF 4x 22uF, 2x 100nF 3.3V 1x 22uF, 2x 100nF 1x 100uF, 2x 100nF 3.3V Standby 1x 22uF, 1x 100nF 1x 22uF, 1x 100nF Aux 1.5V 3x 100nF

3.3.2.6 PCI Express Mini Card 2.0 The PCI Express Mini Card 2.0 add-in card is a small size unique form factor optimized for mobile computing platforms equipped with communication applications such as Wireless LAN. A small footprint connector can be implemented on the carrier board providing the ability to insert different removable PCI Express Mini Cards. Using this approach gives the flexibility to mount an upgradeable, standardized PCI Express Mini Card 2.0 device to the carrier board without the additional expenditure of a redesign.

In addition to a PCI Express x1 link and a USB 2.0 link, the PCI Express Mini Card 2.0 interface utilizes the following control and reset signals, which are provided by the Qseven® module.

Table 3-7 PCI Express Mini Card 2.0 Control Signal Descriptions

Signal Pin Description I/O Comment SMB_CLK / 60 System Management Bus Clock Signal I/O 3.3V PU resistors shall be located on GP1_I2C_CLK OD CMOS the CPU Module SMB_DAT / 62 System Management Bus Data Signal I/O 3.3V PU resistors shall be located on GP1_I2C_DAT OD CMOS the CPU Module

Qseven Design Guide Page 43 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. The reference circuit for PCI Express Mini Card 2.0 adaptation displayed in Figure 3-11 uses the following signals that are generated on the Qseven® evaluation carrier board.

Signal Description I/O PCIE_RST#_5 PCI Express Bus Reset I 3.3V This signal originates from the PCI Standby Express reset buffer shown in Figure CMOS 3-6 'PCI Express Reset Buffer Circuitry' PCIECLK_OE5# Request for PCI Express Serial Reference I 3.3V This signal originates from the clock Clock. For more details see section 'PCI CMOS buffer shown in Figure 3-5 'PCI Express Reference Clock' for details. Express Clock Buffer Circuitry'.

Figure 3-10 PCI Express Mini Card 2.0 and Socket

Note

Compatible half-sized cards are available from a variety of vendors

A potential source for this PCI Express Mini Card 2.0 carrier board connector is: AMP/Tyco HARD TRAY ASSY MINI PCI EXPRESS CONNECTOR 52 POS Article No. 1717831-1.

Pin Signal Description Pin Signal Description 1 WAKE# Request that the host interface return 2 +3.3V Primary voltage source, 3.3V. to full operation and respond to PCIe. 3 RSVD Reserved 4 GND Ground 5 RSVD Reserved 6 +1.5V Secondary voltage source, 1.5V. 7 CLKREQ# Reference clock request signal. 8 UIM_PWR Power source for User Identity Modules (UIM). 9 GND Ground 10 UIM_DATA Data signal for UIM. 11 REFCLK- Reference Clock differential pair 12 UIM_CLK Clock signal for UIM. negative signal. 13 REFCLK+ Reference Clock differential pair 14 UIM_RESET Reset signal for UIM. positive signal. 15 GND Ground 16 UIM_VPP Variable supply voltage for UIM. Mechanical Key 17 RSVD Reserved for future second User 18 GND Ground Identity Modules interface (UIM_C8). 19 RSVD Reserved for future second User 20 W_DISABLE Used by the system to disable Identity Module interface (UIM_C4). radio operation on add-in cards that implement radio frequency application. 21 GND Ground 22 PERST# PCI Express Reset 23 PCIEx_RX- Receiver differential pair negative 24 3.3Vaux Auxiliary voltage source, 3.3V. signal, Lane x. 25 PCIEx_RX+ Receiver differential pair positive 26 GND Ground signal, Lane x. 27 GND Ground 28 +1.5V Secondary voltage source, 1.5V. 29 GND Ground 30 SMB_CLK System Management Bus Clock. 31 PCIEx_TX- Transmitter differential pair negative 32 SMB_DATA System Management Bus Data. signal, Lane x. 33 PCIEx_TX+ Transmitter differential pair positive 34 GND Ground Signal, Lane x. 35 GND Ground 36 USB_D- USB Serial Data Interface differential pair, negative signal. 37 GND Ground 38 USB_D+ USB Serial Data Interface differential pair, positive signal. 39 3.3Vaux Auxiliary voltage source, 3.3V. 40 GND Ground 41 3.3Vaux Auxiliary voltage source, 3.3V. 42 LED_WWAN# LED status indicator signals provided by the system. 43 GND Ground 44 LED_WLAN# LED status indicator signals provided by the system. 45 RSVD Reserved for future second PCIe lane. 46 LED_WPAN# LED status indicator signals provided by the system. 47 RSVD Reserved for future second PCIe lane. 48 +1.5V Secondary voltage source, 1.5V. 49 RSVD Reserved for future second PCIe lane. 50 GND Ground 51 RSVD Reserved for future second PCIe lane. 52 +3.3V Primary voltage source, 3.3V.

Qseven Design Guide Page 45 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Figure 3-11 displays an example of how a PCI Express Mini Card 2.0 socket can be connected to a Qseven® carrier board. The same solution has been implemented on the Qseven® V2.0 evaluation carrier board. It utilizes USB Port 2 and PCI Express lane 0 (via the PCIe Multiplexer shown in Figure 3-7).

Figure 3-11 PCI Express Mini Card Reference Circuitry PCI EXPRESS MINI CARD 2.0

+3.3V_A

+1.5V_S CN18 53 55

52 51 50 49 48 47 +3.3V_A MINIPCIE_LED46 46 45 R527 R-0/X MINIPCIE_LED44 44 43 MINIPCIE_LED42 42 41 L105 40 39 USB_P2_mPCIE+5 38 37 36 35 USB_P2_mPCIE-5 TR-DLW21HN900SQ2 34 33 mPCIE_TX+ 5 32 31 SMB_DAT3,4,6,7,8,9 mPCIE_TX- 5 R528 R-0/X SMB_CLK3,4,6,7,8,9 30 29 28 27 26 25 24 23 mPCIE_RX+ 5 22 21 mPCIE_RX- 5 mPCIe_RST#4 20 19 18 17 JP6 1 W_DISABLE_N UIM_VPP 16 15 2 UIM_RESET 14 13 mPCIE_CLK+ 4 P9 UIM_CLK 12 11 JP-2X1 mPCIE_CLK- 4 SHORTING_PLUG UIM_DATA 10 9 UIM_PWR 8 7 6 5 CK_REQ_mPCIE# 4 4 3 set no jumper for RF operation allowed (default) 2 1 set jumper 1-2 for no RF operation allowed PCIE_WAKE# 3,8,9 54 56 UIM_PWR AAA-PCI-047-K01 C422 R529 CC-10n CN52

1 8 R-4K7 UIM_RESET 2 C1/VCC AS 7 UIM_DATA UIM_CLK 3 C2/RST C7/IO 6 UIM_VPP C423 4 C3/CLK C6/VPP 5 R530 AS C5/GND C426 CC-10 C424 C425 7312S0815X19 CC-10n CC-10 CC-10 R-1K 1 2 +3.3V_A +3.3V_A +3.3V_A 3 4 5 R116 R117 R118 6

R-330 R-330 R-330 SIZE = 0603 SIZE = 0603 SIZE = 0603

LED_MINIPCIE42 LED_MINIPCIE44 LED_MINIPCIE46

D3 D4 D5 SML-LX1206IC-TR SML-LX1206IC-TR SML-LX1206IC-TR

MINIPCIE_LED42 MINIPCIE_LED44 MINIPCIE_LED46 XMINICARD_HOLDER

3.3.2.7 PCI Express Switch In applications where additional PCI Express lanes other than those provided by the Qseven® module are needed, a PCI Express Switch on the Qseven® carrier board can be used to expand the number of available PCI Express lanes. Note:

The current Qseven® V2.0 evaluation carrier board is using a multiplexer (shown in Figure 3-7) and not a switch for lane expansion.

If you are looking for an example of a PCI Express Switch please refer to the Qseven V1.2 Design Guide, chapter 3.3.7 .The example shown there is the implementation on the Qseven® V1.2 evaluation carrier board using a 5 Lane 5 Port PCI Express Switch PEX8505AA25BIG from PLX Technology (http://www.plxtech.com).

3.3.3 Routing Considerations for PCI Express See section 4 of this document for trace routing guidelines and the Qseven® specification for more information about this subject.

3.4.1 UART Interface Signals Table 3-9 Signal Definition of UART

Signal Description I/O Type IOL/IIL I/O UART0_TX Serial Data Transmitter CMOS 3.3V max 1 mA O UART0_RX Serial Data Receiver CMOS 3.3V ≥ 5 mA I UART0_CTS# Handshake signal, ready to send data CMOS 3.3V ≥ 5 mA I UART0_RTS# Handshake signal, ready to receive data CMOS 3.3V max. 1 mA O

3.4.2 UART Implementation example Figure 3-12 shows a reference circuitry for a serial COM0 Interface as implemented on the Qseven V2.0 reference carrier board.

Figure 3-12 UART Reference Circuitry

ADM3310EARUZ U39 CN26B 6 1 Qseven UART 21 C351 C1+ V+ C348 +3.3V_S 10 CC-100n 24 3 CC-100n 15 2 C1- VCC C347 RXD_232 11 C350 C2+ RTS_232 16 27 CC-100n TXD_232 12 CC-100n 4 GND C349 CTS_232 17 28 C2- 13 C352 C3+ 25 CC-100n 18 V- 5 14 CC-100n 26 EN 23 C3- SHDN 22 7 22 RTS_232 SH_CN2613 UART_RTS#3 8 T1IN T1OUT 21 5511-09M/M02RCZ 9 T2IN T2OUT 20 TXD_232 UART_TX3 R410 10 T3IN T3OUT 19 CTS_232 UART_CTS#3 11 R1OUT R1IN 18 12 R2OUT R2IN 17 13 R3OUT R3IN 16 R-0 14 R4OUT R4IN 15 RXD_232 UART_RX3 R5OUT R5IN SIZE = 0805

Qseven Design Guide Page 47 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.5 Gigabit Ethernet LAN Qseven® modules provide at least one 10/100/1000BaseT Gigabit Ethernet LAN port compliant with the IEEE 802.3ab specification.

3.5.1 Gigabit Ethernet Signals The LAN interface of the Qseven® module consists of 4 pairs of low voltage differential pair signals designated from 'GBE_MDI0' (+ and -) to 'GBE_MDI3' (+ and -) plus additional control signals for link activity indicators. These signals can be used to connect a 10/100/1000BaseT RJ45 connector with integrated or external isolation magnetics to the carrier board.

Table 3-10 Signal Definition Ethernet Signals

Signal Pin# Description I/O Type IOL/IIL I/O GBE_MDI0+ 12 Media Dependent Interface (MDI) differential pair 0. The MDI GB_LAN I/O GBE_MDI0- 10 can operate in 1000, 100, and 10Mbit/sec modes. This signal pair is used for all modes. GBE_MDI1+ 11 Media Dependent Interface (MDI) differential pair 1. The MDI GB_LAN I/O GBE_MDI1- 9 can operate in 1000, 100, and 10Mbit/sec modes. This signal pair is used for all modes. GBE_MDI2+ 6 Media Dependent Interface (MDI) differential pair 2. The MDI GB_LAN I/O GBE_MDI2- 4 can operate in 1000, 100, and 10Mbit/sec modes. This signal pair is only used for 1000Mbit/sec Gigabit Ethernet mode. GBE_MDI3+ 5 Media Dependent Interface (MDI) differential pair 3. The MDI GB_LAN I/O GBE_MDI3- 3 can operate in 1000, 100, and 10Mbit/sec modes. This signal pair is only used for 1000Mbit/sec Gigabit Ethernet mode. GBE_CTREF 15 Reference voltage for carrier board Ethernet channel 0 REF O magnetics center tap. The reference voltage is determined by the requirements of the module's PHY and may be as low as 0V and as high as 3.3V. The reference voltage output should be current limited on the module. In a situation in which the reference is shorted to ground, the current must be limited to 250mA or less. GBE_LINK# 13 Ethernet controller link indicator, active low. CMOS max 10 mA O 3.3V PP GBE_LINK100# 7 Ethernet controller 100Mbit/sec link indicator, active low. CMOS max 10 mA O 3.3V PP GBE_LINK1000# 8 Ethernet controller 1000Mbit/sec link indicator, active low. CMOS max 10 mA O 3.3V PP GBE_ACT# 14 Ethernet controller activity indicator, active low. CMOS max 10 mA O 3.3V PP

3.5.2 LAN Implementation Guidelines The most critical component in the LAN interface is the isolation magnetics connected directly to the MDI differential pair signals of the Qseven® module. It should be carefully qualified for Return Loss, Insertion Loss, Open Circuit Inductance, Common Mode Rejection and Crosstalk Isolation to pass the IEEE conformance tests and EMI tests.

Even if a Qseven® module complies with the basic specifications set forth for IEEE certification, it's still possible that the overall system could fail IEEE testing because of a poor quality or unsuitable external isolation magnetics module and/or improper PCB layout of the carrier board.

Qseven Design Guide Page 48 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.5.2.1 LAN Magnetics Modules 1000Base-T Ethernet magnetics modules are similar to those designed solely for 10/100 BaseTx Ethernet, except that there are four MDI differential signal pairs instead of two. 1000Base-T magnetics modules have a center tap pin that is connected to the reference voltage output 'GBE_CTREF' of the Qseven® module, which biases the controller's output buffers. Magnetics with four center tap pins may have better characteristics than those with one or two center tap pins. Depending on the PHY manufacturer some PHYs may require, that each differential pair center tap pin is connected separately via a capacitor to ground. In this case the PHY center tap pins are not connected together.The isolation magnetics can be integrated in a RJ45 jack, which also provides activity and speed LED indicators. Alternatively, they can be designed as discrete magnetics modules, which will be connected to a pure RJ45 jack. Table 3-11 lists recommended magnetics modules and RJ45 jacks for usage on a carrier board design.

Table 3-11 Recommended LAN Magnetic Modules

Manufacturers Part Number Technology Comments Pulse Engineering H5007 10/100/1000BaseT Discrete magnetics module Pulse Engineering JK0-0036 10/100/1000BaseT RJ45 jack with integrated magnetics and activity LEDs Bel Fuse S558-5999–P3 10/100/1000BaseT Discrete magnetics module Pulse JW0A1P01R-E 10/100/1000BaseT RJ45 jack with integrated magnetics and USB jacks Foxconn UB11123-J51 10/100/1000BaseT RJ45 jack with integrated magnetics and USB jacks For optimum performance consult module manufacturers for magnetics recommendations and schematics

3.5.2.2 LAN Component Placement When using RJ45 connectors without integrated magnetics, the discrete magnetics module has to be placed as close as possible to the RJ45 connector. The distance between the magnetics module and RJ45 connector must be less than 1 inch. This distance requirement must be observed during the carrier board layout when implementing LAN. Due to the insertion loss budget of Qseven®, the overall trace length of the MDI signal pairs on the carrier board should be less than 4 inches. Signal attenuation could cause data transfer problems for traces longer than 4 inches.

3.5.2.3 LAN Ground Plane Separation Isolated separation between the analog ground plane and digital ground plane is recommended. If this is not implemented properly then bad ground plane partitioning could cause serious EMI emissions and degrade analog performance due to ground bounce noise.

The plane area underneath the magnetic module should be left empty. This free area is to keep transformer induced noise away from the power and system ground planes.

The isolated ground, also called chassis ground, connects directly to the fully shielded RJ45 connector. For better isolation it is also important to maintain a gap between chassis ground and system ground that is wider than 60mils. For ESD protection, a 3kV high voltage capability capacitor is recommended to connect to this chassis ground.

3.5.2.4 LAN Link Activity and Speed LED The Qseven® module has four 3.3V push/pull outputs to directly drive activity, speed indication and link status LEDs. The 3.3V standby voltage should be used as LED supply voltage so that the link activity can be viewed during system standby state. Since LEDs are likely to be integrated into a RJ45 connector with integrated magnetics module, the LED traces need to be routed away from potential sources of EMI noise. Consider adding a filtering capacitor per LED for extremely noisy situations. The suggested value for this capacitor is 470pF.

3.5.2.5 LAN Reference Schematics Figure 3-14 GbE Schematic Example

U30 1 24 GBE_CTREF3 2 CH-D 23 ETHERNET CN39 2-406549-8 +3.3V_A 3 22 13 R386 R-330 GBE_MDI0+3 1 SIZE = 0603 GBE_MDI0-3 4 21 2 14 GBE_ACT# 3 5 CH-C 20 3 GBE_MDI1+3 4 GBE_MDI1-3 5 6 GBE_MDI2+3 6 19 7 15 R387 R-330 GBE_MDI2-3 8 SIZE = 0603 7 18 16 GBE_MDI3+3 GBE_LINK# 3 8 CH-B 17 GBE_MDI3-3 2 9 0 1 1 1 1

9 16

10 15 11 CH-A 14 LINK 1Gb/s

R396 R-330 D34 SML-LX1206YC-TR 12 13 +3.3V_A GBE_LINK1000# 3

749020013 R394 R-330 D33 SML-LX1206GC-TR C274 C275 C276 C277 +3.3V_A GBE_LINK100# 3 C283 CC-100n/50V CC-100n CC-100n CC-100n CC-100n LINK 100 Mb/s C284 CC-100n/50V R310 R311 R312 R313

R-75 R-75 R-75 R-75 SIZE = 0603 SIZE = 0603 SIZE = 0603 SIZE = 0603 C285 CC-10n/50V

C288 CC-10n/50V C282 CC-1n/2KV R409 R-0/X SIZE = 0805 Note:

Depending on the PHY manufacturer some PHYs may require that each differential pair center tap pin is connected separately via a capacitor to ground. In this case the PHY center tap pins are not connected together.

3.5.3 Routing Considerations for LAN See section 4 of this document for trace routing guidelines and the Qseven® specification for more information about this subject.

Qseven Design Guide Page 50 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.6 Serial ATA Interface Serial ATA (SATA) is a serial interface for connecting storage devices (mainly hard disks) and was defined to replace the old parallel ATA interface. Serial ATA uses a point-to-point serial connection between the system and the storage device. The first generation of standard Serial ATA provides a maximum effective data transfer rate of 150MB/s per port. With the second generation SATA II, an effective transfer rate of up to 300MB/s per port is possible. Serial ATA is completely software transparent to the IDE interface while providing a lower pin count and higher performance.

3.6.1 Serial ATA Interface Signals

Qseven® modules can provide up to 2 Serial ATA channels, each with a receive and transmit differential signal pair designated from 'SATA0_RX' (+ and -) to 'SATA1_RX' (+ and -) and correspondingly from 'SATA0_TX' (+ and -) to 'SATA1_TX' (+ and -). The appropriate signals can be found on the Qseven® module connector.

Table 3-12 Signal Definition SATA

Signal Pin# Description I/O Type IOL/IIL I/O SATA0_RX+ 35 Serial ATA channel 0, Receive Input differential pair. SATA I SATA0_RX- 37 SATA0_TX+ 29 Serial ATA channel 0, Transmit Output differential pair. SATA O SATA0_TX- 31 SATA1_RX+ 36 Serial ATA channel 1, Receive Input differential pair. SATA I SATA1_RX- 38 SATA1_TX+ 30 Serial ATA channel 1, Transmit Output differential pair. SATA O SATA1_TX- 32 SATA_ACT# 33 Serial ATA Led. Open collector output pin driven during OC 3.3V max. O SATA command activity. 10mA

3.6.2 Serial ATA Implementation Example

Figure 3-15 shows an example implementation of Serial ATA hard drive Interfaces on the Qseven® V2.0 carrier board. In this example Serial ATA channel 1 of the Qseven® module is used directly and channel 0 uses a SATA switch to switch alternatively to an mSATA connector. The Serial ATA hard drive can be powered directly or by a Serial ATA power connector implemented on the carrier board.

CN9 CN11 SATA 0 SATA 1 G1 G1 G1 G1 S1 GND 1 S2 SATA1_TX+[3] TX+ 2 GND S3 SATA1_TX-[3] TX- STD_SATA0_TX+[5] 3 TX+ S4 STD_SATA0_TX-[5] TX- S5 GND 4 SATA1_RX-[3] RX- 5 GND S6 SATA1_RX+[3] RX+ STD_SATA0_RX-[5] 6 RX- S7 GND STD_SATA0_RX+[5] 7 RX+ GND G2 G2 G2 G2

+5V_S P1 P2 3.3V WATM-07ABN4B2B8UW P3 3.3V P4 3.3V CN10 P5 GND +5V_S P6 GND +12V_S P7 GND 1 P8 5V 5V C74 P9 C76 C77 C78 P10 5V 2 P11 GND CC-100n CC-100n CC-100n CC-100n +12V_S P12 GND P13 GND 3 P14 12V +5V_S CFG = A0 CFG = A0 CFG = A0 P15 12V C79 C80 C81 12V 4 G3 C75 CC-100n/25V CC-100n/25V CC-100n/25V G3

CC-100n 4070I-04 CFG = A0 CFG = A0 CFG = A0 87779-1001 CFG = A0

CN8 mSATA G2 +3.3V_S 51 52 mSATA_DET#[5] 49 50 C71 C69 C67 47 48 +3.3V_S 45 46 CC-100n CC-100n CC-100n 43 44 C70 C68 41 42

39 E 40 A CC-100n CC-100n 37 J 38 35 36 +3.3V_S 33 34 mSATA0_TX+[5] R68 31 32 mSATA0_TX-[5] 29 30 27 28 25 26 mSATA0_RX-[5] 23 24 R-330 mSATA0_RX+[5] 21 22 D2 C72 C73 19 20 17 18 CC-10u/6.3V CC-10u/6.3V +3.3V_S 15 16 R69 LED_RED 6 13 14 +3.3V_S 11 12 Q2A 9 10 2N7002DW R70 R-10K 2 7 8 3 Package = 5 5 6 3 4

Q2B 1 1 2 2N7002DW mSATA_DET# R-10K 5 Package = 5 G1

4 AAA-PCI-049-K01

Figure 3-16 Example for a Serial ATA / mSATA Switch implementation

+3.3V_S

C48 C49 C50 C51 C52

CC-100n CC-100n CC-100n CC-100n CC-100n

U45 0 6 1 CBTL02043B 2 1 1 D D D D D D V V V 2 18 SATA0_RX+[3] mSATA0_RX+ [6] 3 A0_P B0_P 17 SATA0_RX-[3] A0_N B0_N mSATA0_RX- [6]

4 STD_SATA0_RX+ [6] C0_P 5 C0_N STD_SATA0_RX- [6]

6 14 SATA0_TX+[3] mSATA0_TX+[6] 7 A1_P B1_P 13 SATA0_TX-[3] A1_N B1_N mSATA0_TX-[6]

8 STD_SATA0_TX+[6] C1_P 9 C1_N STD_SATA0_TX- [6]

12 +3.3V_S SEL

19 R56 XSD D D D D N N N R-2K2 A G G G P 1 0 5 1 mSATA_DET# [6] 1 1 2

Table 3-13 Serial ATA Data Connector Pinout and Signal Description

Pin Signal Description Pin Signal Description 1 GND Ground 5 RX- Receiver differential pair negative signal 2 TX+ Transmitter differential pair positive signal 6 RX+ Receiver differential pair positive signal 3 TX- Transmitter differential pair negative signal 7 GND Ground 4 GND Ground

Pins Signal Description Pins Signal Description 1 +3.3V 3.3V power supply 10 GND Ground 2 11 3 12 4 GND Ground 13 +12V 12V power supply 5 14 6 15 7 +5V 5V power supply 8 9

Table 3-15 mSATA Connector Pinout and Signal Description

Pin Signal Description Pin Signal Description 1 RSVD Reserved 2 +3.3V 3.3V.power supply 3 RSVD Reserved 4 GND Ground 5 RSVD Reserved 6 n/c 1.5V secondary voltage source* 7 RSVD Reserved 8 RSVD Reserved 9 GND Ground 10 RSVD Reserved 11 RSVD Reserved 12 RSVD Reserved 13 RSVD Reserved 14 RSVD Reserved 15 GND Ground 16 RSVD Reserved Mechanical Key 17 RSVD Reserved 18 GND Ground 19 RSVD Reserved 20 RSVD Reserved 21 GND Ground 22 RSVD Reserved 23 RX+ Receiver differential pair positive signal 24 3.3Vaux 3.3V.power supply 25 RX- Receiver differential pair negative signal 26 GND Ground 27 GND Ground 28 n/c 1.5V secondary voltage source* 29 GND Ground 30 n/c System Management Bus Clock. 31 TX- Transmitter differential pair negative signal 32 n/c System Management Bus Data. 33 TX+ Transmitter differential pair positive Signal 34 GND Ground 35 GND Ground 36 RSVD Reserved 37 GND Ground 38 RSVD Reserved 39 +3.3V 3.3V.power supply 40 GND Ground 41 +3.3V 3.3V.power supply 42 RSVD Reserved 43 RSVD Reserved 44 RSVD Reserved 45 RSVD Reserved 46 RSVD Reserved 47 RSVD Reserved 48 n/c 1.5V secondary voltage source* 49 RSVD Reserved 50 GND Ground 51 DET mSATA device presence detection 52 +3.3V Primary voltage source, 3.3V

* There is no 1.5V power rail used in the Qseven V2.0 reference carrier board

mSATA (Mini Serial ATA, not to be confused with micro Serial ATA) is using a standard PCI express mini card connector, however the pinout is different.

3.6.3 Routing Considerations for Serial ATA See section 4 of this document for trace routing guidelines and the Qseven® specification for more information about this subject.

Qseven Design Guide Page 54 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.7 USB Interface The Universal Serial Bus interface of the Qseven® module is compliant to USB 1.1 as well as USB 2.0 and USB 3.0 specification. Qseven® specifies a minimum configuration of 3 USB 2.0 host ports for ARM architectures respectively 4 USB 2.0 ports for Intel architectures up to a maximum of 8 ports on both platforms. The number of USB 3.0 ports may vary from 0 to 2 ports on both platforms.

Note

Depending on the Qseven® module' used, some USB ports may not support USB 1.1 , USB 2.0 or USB 3.0.

3.7.1 USB Interface Signals USB Port1 can be optionally configured as a USB client port

Table 3-16 Signal Definition USB

Signal Pin# Description I/O Type IOL/IIL I/O USB_P0+ 96 Universal Serial Bus Port 0 differential pair + USB I/O USB_P0- 94 Universal Serial Bus Port 0 differential pair - USB I/O USB_P1+ 95 Universal Serial Bus Port 1 differential pair + USB I/O This port may be optionally used as USB client port (+) USB_P1- 93 Universal Serial Bus Port 1 differential pair - USB I/O This port may be optionally used as USB client port (-) USB_P2+ 90 Universal Serial Bus Port 2 differential pair + USB I/O USB_P2- 88 Universal Serial Bus Port 2 differential pair - USB I/O USB_P3+ 89 Universal Serial Bus Port 3 differential pair + USB I/O USB_P3- 87 Universal Serial Bus Port 3 differential pair - USB I/O USB_P4+ / 84 Universal Serial Bus Port 4 differential pair + / USB / I/O USB_SSRX1+ USB SuperSpeed Channel 1 receive data + USB SuperSpeed I USB_P4- / 82 Universal Serial Bus Port 4 differential pair - / USB / I/O USB_SSRX1- USB SuperSpeed Channel 1 receive data - USB SuperSpeed I USB_P5+ / 83 Universal Serial Bus Port 5 differential pair + / USB / I/O USB_SS_TX1+ USB SuperSpeed Channel 1 transmit data - USB SuperSpeed O USB_P5- / 81 Universal Serial Bus Port 5 differential pair - / USB / I/O USB_SS_TX1- USB SuperSpeed Channel 1 transmit data - USB SuperSpeed O USB_P6+ / 78 Universal Serial Bus Port 6 differential pair + / USB / I/O USB_SS_TX0+ USB SuperSpeed Channel 0 receive data + USB SuperSpeed USB_P6- / 76 Universal Serial Bus Port 6 differential pair - / USB / I/O USB_SS_RX0- USB SuperSpeed Channel 0 receive data - USB SuperSpeed I USB_P7+ / 77 Universal Serial Bus Port 7 differential pair + / USB / I/O USB_SS_TX0+ USB SuperSpeed Channel 0 transmit data + USB SuperSpeed O USB_P7- / 75 Universal Serial Bus Port 7 differential pair - / USB / I/O USB_SS_TX0- USB SuperSpeed Channel 0 transmit data - USB SuperSpeed O USB_0_1_OC# 86 Over current detect input 1. This pin is used to monitor CMOS ≥ 5 mA I the USB power over current of the USB Ports 0 and 1. 3.3V Suspend USB_2_3_OC# 85 Over current detect input 2. This pin is used to monitor CMOS ≥ 5 mA I the USB power over current of the USB Ports 2 and 3. 3.3V Suspend USB_4_5_OC# 80 Over current detect input 3. This pin is used to monitor CMOS ≥ 5 mA I the USB power over current of the USB Ports 4 and 5. 3.3V Suspend

Qseven Design Guide Page 55 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Signal Pin# Description I/O Type IOL/IIL I/O USB_6_7_OC# 79 Over current detect input 4. This pin is used to monitor CMOS ≥ 5 mA I the USB power over current of the USB Ports 6 and 7. 3.3V Suspend USB_VBUS 91 USB VBUS pin. CMOS 5.0V <=2.5mA I  5V tolerant (B-device)  VBUS resistance has to be placed on the module  VBUS capacitance has to be placed on the carrier board USB_ID 92 USB ID pin. Analogue O Configures the mode of the USB Port 1. The resistance of this pin measured to ground is used to determine whether USB Port 1 is going to be used as USB Client to enable/ disable USB Client support. Please check the USB-OTG Reference of your chip manufacturer for further details. USB_OTG_PEN 56 USB Power enable pin for USB Port 1 CMOS 3.3V I Enables the Power for the USB-OTG port on the carrier board.

Qseven Design Guide Page 56 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.7.2 USB Implementation Guidelines 3.7.2.1 Mixed USB2.0/3.0 Distribution The Qseven V2.0 standard enables a variety of possible implementations for USB 2.0 and/or USB 3.0 implementations. It's also ready for USB on-the-go (USB-OTG) implementations. In addition to the switches used in the Qseven V2.0 Reference Carrier Board another method to keep maximum configuration flexibility for evaluation carrier boards is to use zero ohm resistors to switch between 2.0 and 3.0 usage of the USB signals coming from the module. For signal integrity reasons fixed solutions or zero ohm resistors are preferred for custom production boards, especially when utilizing USB 3.0.

Figure 3-17 Example for USB 2.0 / 3.0 distribution

Please refer also to Figure 3-2 USB and PCI express distributions of the final Qseven V2.0 Reference Board.

+5V_A L75 FB-BLM18KG471SN1 CN30 C233 C234 9 11 R232 R-0/X R233 R-0/X 1 5

2 L76 L77 CC-10u/10V CC-100n U22 AP2142A USB_P2_DB-[5] 2 6 USB_P3- [3] EN_VBUS# 3 7 3 7 N 8 EN1 I OUT1 C235 USB_P2_DB+[5] 4 8 USB_P3+ [3] TR-DLW21HN900SQ2 TR-DLW21HN900SQ2 OC1 d 10 12 a R234 R-0/X C236 C237 R235 R-0/X P

4 . CT-47u/10V D

EN2 p N 5 x 6 USB DoubleConnector

USB_2_3_OC#[3] G E CC-100n CC-100n OC2 OUT2 L78 FB-BLM18KG471SN1 C240 1 9

CT-47u/10V +5V_A D11 5 1 3 4 2 6

IP4221CZ6-S

L81 FB-BLM18KG471SN1 CFG = B0

This example shows an USB2.0 implementation without USB switches/multiplexers as shown in Figure 3-17. It uses dual USB 2.0 connectors for the USB ports 2, 3, and 4, 5.

Table 3-17 USB 2.0 Host Dual Type-A Connector Pinout

Signal Pin Description I/O Comment VCC 1 +5V Power Supply P 5V D- 2 Universal Serial Bus Data, I/O USB negative differential signal. D+ 3 Universal Serial Bus Data, I/O USB positive differential signal. GND 4 Ground P 3.7.2.3 USB 3.0 Reference Schematics Figure 3-19 USB 3.0 Reference Circuit

+5V_A

C238 C239

CC-10u/10V CC-100n CFG = E0 CFG = E0

U232 AP2142A L79 FB-BLM18KG471SN1 EN_VBUS# 3 7 C241 CFG = E0 C242 N 8 EN1 I OUT1

OC1 d CT-47u/10V CC-100n a P

4 . CFG = E0 CFG = E0 D

EN2 p N 5 x 6

USB_6_7_OC#[3] G E OC2 OUT2 L80 FB-BLM18KG471SN1 CFG = E0 C243 CFG = E0 C244 1 9

CT-47u/10V CC-100n CFG = E0 CFG = E0 NO STUB!!! provide for 3-patch sharing

+5V_A D12 USB 3.0 host USB_P6-/USB_SSRX0-[3] 5 1 +5V_A USB_P6+/USB_SSRX0+[3] 3 U24 4 R237 R236 R238 R239 1 6 L82 FB-BLM18KG471SN1 Standard A-Type 2 6 C246 C245 IN OUT C247 5 IP4221CZ6-S CC-10u/10V CC-100n ILIM R240 R241 CT-47u/10V CFG = E0 CN32 CFG = E0 connector R-0 R-0 R-0 R-0 1 2 CN31 692121030100 CFG = E1CFG = E1CFG = E0CFG = E0 R242 R-0/X R243 R-0/X R244 R-0/X 4 L84 3 4 L85 USB_0_1_OC#[3,16] 5 L83 EN_VBUS# 3 FAULT 2 R-28K7/1 R-52K3/1 1 CFG = E0 CFG = E0 EN GND CFG = E0 CFG = E0 CFG = E1 5 6 R245 R-0/X 6 TPS2552DBV TR-DLW21HN900SQ2 TR-DLW21HN900SQ2 L86 2 TR-DLW21HN900SQ2 R250 USB_P0-[3] R247 R-0/X 7 8 R248 R-0/X R251 7 R246 R-0/X 3 R249 R-0/X USB_P0+[3] 10 TR-DLW21HN900SQ2 8 L87 R253 R-0 R252 R-0/X 4 CFG = E1 C248 CFG = E1 L88 2213S-10G-E9 R-0 R-0 9 R254 R-0 CFG = E0CFG = E0 D13 IP4283CZ10-TBA TR-DLW21HN900SQ2 CFG = E1 FB-BLM18KG471SN1 CC-100n 10 1 R255 R-0/X 1 2

G G 9 2 USB_P7-/USB_SSTX0- [3] CFG = E1 7 4 USB_P7+/USB_SSTX0+ [3] +5V_A D14 6 5 5 1 L89 FB-BLM18KG471SN1 3 L90 FB-BLM18KG471SN1 3 8 CFG = E1 4 2 6 USB1_ID[3] CLIENT_P1+ R256 R-0/X IP4221CZ6-S CLIENT_P1- L91 CFG = B1 R257 R-0 CFG = B1 USB_P4-/USB_SSRX1- [3,16] USB_VBUS USB_VBUS[3] C249 C250 R258 R-0 CFG = B1 USB_P4+/USB_SSRX1+ [3,16] TR-DLW21HN900SQ2 CC-100n CC-10u/10V R259 R-0/X R261 R-0/X 0

R260 R-0/X 1 2 3 4 5 6 7 8 9 1 L93 CFG = B1 R262 R-0 CFG = B1 USB_P5-/USB_SSTX1- [3,16] L92 - USB_P1-[3] - - + + + S D D D I X X

D R263 R-0 CFG = B1 X _ X D U N USB_P5+/USB_SSTX1+ [3,16] T R T D R B D15 IP4283CZ10-TBA TR-DLW21HN900SQ2 G S S S

USB_P1+[3] S V N S S 10 1 TR-DLW21HN900SQ2 S R264 R-0/X S R265 R-0/X G 9 2 7 4 KMMX-AB10-SMT1SB30TR NO STUB!!! provide for 3-patch sharing CN33 6 5

CFG = B1 USB 3.0 Host/Client 3 8 Micro AB-Type connector This example shows a USB 3.0 implementation with zero ohm resistors instead of switches/multiplexers for configuration. It uses a USB 3.0 Type A Host connector for the the channel 0 USB 3.0 host and a USB 3.0 microAB connector for the second host channel 1 and alternatively the USB 2.0 Client Port 1.

Table 3-18 USB 3.0 Type A Connector Pinout

Qseven Design Guide Page 58 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Signal Pin Description I/O Comment VBUS 1 +5V Power Supply Power 5V D- 2 Universal Serial Bus Data, I/O USB negative differential signal. D+ 3 Universal Serial Bus Data, I/O USB positive differential signal. GND 4 Ground GND StdA_SSRX- 5 High Speed Input - I StdA_SSRX+ 6 High Speed Input + I GND Drain 7 Reference Ground GND StdA_SSTX- 8 High Speed Output - O StdA_SSTX+ 9 High Speed Output - O Shield G1 Connector Shell GND Shield G2 Connector Shell GND

Table 3-19 USB 3.0 microAB Host/Client Connector Pinout Signal Pin Description I/O Comment VBUS 1 +5V Power Supply Power 5V D- 2 Universal Serial Bus Data, I/O USB negative differential signal. D+ 3 Universal Serial Bus Data, I/O USB positive differential signal. OTG ID 4 OTG ID for identifying lines USB_ID signal from module GND 5 Ground GND StdA_SSRX- 6 High Speed Input - I StdA_SSRX+ 7 High Speed Input + I GND Drain 8 Reference Ground GND StdA_SSTX- 9 High Speed Output - O StdA_SSTX+ 10 High Speed Output - O

Note:

Depending on the module used there are two methods for switching between host and client mode for USB Port 1:

1. OTG (on-the-go) and 2. manual selection.

OTG switches automatically in a runtime environment, manual selection can be realized using Bios setup

3.7.2.4 USB Overcurrent Protection Figure 3-20 Current Limiter Circuitry

+5V_A U26 1 6 L99 FB-BLM18KG471SN1 C260 C259 IN OUT C444 C446 C445 C257 R275 5 CC-100n CC-10u/10V ILIM R278 R538 CC-47u/10V CC-47u/10V CC-47u/10V CC-100n

R-100K USB_0_1_OC# 4 3 FAULT 2 R-49K9 R-68K EN GND 3 Q36 TPS2552DBV +5V_A 2 USB3.0_OTG_EN R539 2N7002 1

+3.3V_A R-10K R540 3 Q37

2 R-100K/X USB_DRIVE_VBUS [3] R276 2N7002 1

R-100K

The USB Specification describes power distribution over the USB port, which supplies power for USB devices that are directly connected to the carrier board. Therefore, the host must implement over-current protection on the ports for safety reasons. Should the aggregate current drawn by the downstream ports exceed a permitted value, the overcurrent protection circuit removes power from all affected downstream ports. The overcurrent limiting mechanism must be resettable without user mechanical intervention. For more detailed information about this subject refer to the 'Universal Serial Bus Specifications Revision 2.0', which can be found at http://www.usb.org.

Over-current protection for USB ports can be implemented by using power distribution switches on the carrier board that monitor the USB port power lines. Power distribution switches usually have a soft-start circuitry that minimizes inrush current in applications where highly capacitive loads are employed. Transient faults are internally filtered. Additionally, they offer a fault status output that is asserted during over-current and thermal shutdown conditions. These outputs should be connected to the corresponding Qseven® module's USB over-current sense signals.

Simple resettable PolySwitch devices are capable of fulfilling the requirements of USB over-current protection and therefore can be used as a replacement for power distribution switches.

3.7.2.5 EMI/ESD Protection To improve the EMI behavior of the USB interface, a design should include common mode chokes, which have to be placed as close as possible to the USB connector signal pins. Common mode chokes can provide required noise attenuation but they also distort the signal quality of full-speed and high-speed signaling. Therefore, common mode chokes should be chosen carefully to meet the requirements of the EMI noise filtering while retaining the integrity of the USB signals on the carrier board design.

To protect the USB host interface of the module from over-voltage caused by electrostatic discharge (ESD) and electrical fast transients (EFT), it is highly recommended to use low capacitance steering diodes and transient voltage suppression diodes that must be implemented on the carrier board (for example SR05 RailClamp®' surge rated diode arrays from Semtech, http://semtech.com).

3.7.2.6 USB Client Considerations Precautions at the carrier board level must be taken to protect against voltage spikes

Qseven Design Guide Page 60 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. and ESD to ensure robust operation of the host detection circuitry after multiple connect/disconnect events. A clamping diode may be used to minimize ESD, and a bulk capacitor should be placed on +5V USB client rail to avoid excessive voltage spikes.

Level Shifter removed for Qseven Specification 2.0 – please check for compatibility with old 1.2 designs

Figure 3-21 USB Client Connect Protection

NOTE:

In the errata sheet 1 for the Qseven Specification Rev 2.0 the USB_CC signal is redefined to be the USB_VBUS signal. So there is no level shifter circuit needed on the USB_CC signal. The module's USB_VBUS input is directly connected to the +5V Vbus Signal on the connector on the carrier board.

3.7.3 Routing Considerations for USB

See section 4 of this document for trace routing guidelines and the Qseven® specification for more information about this subject.

Qseven Design Guide Page 61 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.8 SDIO Interface SDIO (Secure Digital I/O) provides an easy to implement solution for high-speed data I/O combined with low power consumption. SDIO cards are fully compatible with SD memory cards. This includes mechanical, electrical, power, signaling and software compatibility. SDIO hosts are able to drive SD cards and MMC (MultiMediaCards) as well as SDIO cards that provide functions such as Ethernet or WLAN, GPS receivers, Bluetooth, modems etc.

The Qseven® specification defines one optional 8-bit SDIO interface on the module.

3.8.1 SDIO Interface Signals Definition Table 3-20 Signal Definition SDIO

Signal Pin# Description I/O Type IOL/IIL I/O SDIO_CD# 43 SDIO Card Detect. This signal indicates when a SDIO/MMC CMOS 3.3V I/O card is present. SDIO_CLK 42 SDIO Clock. With each cycle of this signal a one-bit transfer CMOS 3.3V O on the command and each data line occurs. This signal has maximum frequency of 48 MHz. SDIO_CMD 45 SDIO Command/Response. This signal is used for card CMOS 3.3V I/O initialization and for command transfers. During initialization OD/PP mode this signal is open drain. During command transfer this signal is in push-pull mode. SDIO_LED 44 SDIO LED. Used to drive an external LED to indicate when CMOS 3.3V max 1 O transfers occur on the bus. mA SDIO_WP 46 SDIO Write Protect. This signal denotes the state of the CMOS 3.3V I/O write-protect tab on SD cards.

SDIO_PWR# 47 SDIO Power Enable. This signal is used to enable the power CMOS 3.3V O being supplied to a SD/MMC card device. SDIO_DAT0-7 48 to SDIO Data lines. These signals operate in push-pull mode. CMOS 3.3V I/O 55 PP

Note

If the SDIO presence LED is located on the carrier board a pulldown resistor is required on the carrier board

The example below shows an SDIO interface as implemented in the Qseven V2.0 reference carrier board.

Figure 3-22 Example for SDIO Card Implementation

Q13 SI2333CDS +3.3V_S +3.3V_SD 1 3 C265 C266

CC-100n CC-100n 2

R292 R-2K2

+5V_A 6

Q14A 2N7002DW R293 R-2K2 SDIO_PWR 2 R291 R-330 R290 R-330 +3.3V_S Package = 6 +3.3V_SD +3.3V_SD D28 3 1 Q14B 2N7002DW 5 Q11 SDIO_PWR#[3] Package = 6 2N7002 SDIO_ACT# LED_RED SDIO_PWR# 4

Q12 2N7002 +3.3V_SD D26 +3.3V_SD D27 SDIO_LED[3] 5 1 5 1 3 3 4 4 2 6 2 6

IP4221CZ6-S IP4221CZ6-S

SDIO_ACT# SD/MMC 13 R287 SDIO_DAT0[3] 14 SD_DATA0 R-0 SDIO_DAT1[3] 1 SD_DATA1 SDIO_DAT2[3] 2 SD_DATA2 SDIO_DAT3[3] 3 SD_DATA3 SDIO_DAT4[3] 5 SD_DATA4 D24 SDIO_DAT5[3] 10 SD_DATA5 SDIO_DAT6[3] 12 SD_DAAT6 SDIO_DAT7[3] 4 SD_DATA7 SDIO_CMD[3] 9 CMD HDD_ACT# [6] SDIO_CLK[3] 6 CLK SDIO_CD#[3] 15 SDCD SDIO_WP[3] SDWP +3.3V_SD 8 SATA_ACT#_BF C267 7 VDD BAT54A/SOT +3.3V_SD D29 11 VSS 5 1 CC-100n 16 VSS2 3 GND 4 CN36 2 6

IP4221CZ6-S

Qseven Design Guide Page 63 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.9 High Definition Audio / AC97 / I²S Audio Signals Since Version 2.0Qseven® modules support either High Definition Audio (HDA), AC'97 or I²S for implementing audio functionality.

3.9.1 High Definition Audio / AC97 / I²S Audio Signals Definitions Table 3-21 Signal Definition HDA

Signal Pin# Description I/O Type IOL/IIL I/O HDA_RST# 61 HD Audio/AC'97/I²S Codec Reset. CMOS O 3.3V HDA_SYNC 59 Serial Bus Synchronization. CMOS O 3.3V HDA_BITCLK 63 HD Audio/AC'97/I²S 24 MHz Serial Bit Clock from Codec. CMOS O 3.3V HDA_SDO 67 HD Audio/AC'97/I²S Serial Data Output to Codec. CMOS O 3.3V HDA_SDI 65 HD Audio/AC'97/I²S Serial Data Input from Codec. CMOS I/O 3.3V

Note

I/O Orientation: Input denotes a signal flow to the module and output denotes a signal flow from the module.

The High Definition Audio interface found on the Qseven® module complies with Intel® High Definition Audio Specification 1.0.

HD Audio is primarily intended for use with x86 products. ARM based products normally do not provide any HDA. Please see Section 3.9.2.2 for I²S Implementation and Section 3.9.2.3 for AC97 implementation examples.

Qseven Design Guide Page 64 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.9.2 High Definition Audio / AC97 / I²S Guidelines / Examples 3.9.2.1 HDA Implementation Example The example in Figure 3-23 shows the implementation of the Realtek ALC 886 HDA Codec (http://www.realtek.com.tw). This HDA Codec is used on the Qseven® V2.0 evaluation carrier board.

Figure 3-23 HDA Codec Reference Schematics

+5V_A

L33 SIDESURR-JD R133 R-5K1 MIC1-VREFO-R CEN-JD R134 R-10K MIC1-VREFO-L FB-BLM18KG471SN1 +5V_HDA

C173 C174 FRONT-L FRONT-R C172 CC-100n CC-10u/10V CC-10u/10V GND_HDA

6 5 4 3 2 1 0 9 8 7 6 5 GND_HDA

3 3 3 3 3 3 3 2 2 2 2 2 ALC886-GR U13 L L L 1 1 F B R R O O O - -

- - S D O E F F F T e O T O S V s D R E E E U F U F n V V V C R R R E O e E O A - A D V V V - R S - - - R T T 2 2 1 V V N -

37 N 24

- LINE1-R E E C 1 I 1 PIN37-VREFO-R O LINE1-R O N N C I I C R M I R I L L F

38 F 23

+5V_HDA M LINE1-L AVDD2 M LINE1-L C176 C177 SURR-L 39 22 MIC1-R SURR-OUT-L MIC1-R CC-10u/10V CC-100n R144 R-20K 40 21 MIC1-L JDREF MIC1-L SURR-R 41 20 SURR-OUT-R CD-R 42 19 AVSS2 CD-GND CEN 43 18 GND_HDA CEN CD-L LFE 44 17 GND_HDA LFE MIC2-R SIDESURR-L 45 16 SIDESURR-OUT-L MIC2-L R154 SIDESURR-R 46 15 Analog SIDESURR-OUT-R LINE2-R S/PDIF-IN 47 14 Digital SPDIFI/EAPD LINE2-L R-0 S/PDIF-OUT 48 T 13 R147 R-5K1 FRONT-JD

SPDIFO U Sense A N O I O P - - # K I - 1 T

2 E R149 R-10K LINE1-JD A A L 0 1 D D S T T E S C E C O O - I I D S A A S S D B N T P P V V V V E D I D Y C R152 R-20K MIC1-JD D G G D S B D S D S R P R153 R-39K2 SURR-JD 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 +3.3V_S Analog L41 FB-BLM18KG471SN1 C192 C193 C191 C195 Digital C189 CC-1u/10V R157 R-10K HD_SPKR CC-100n CC-10u/6.3V CC-100n CC-10u/6.3V R159 C194

CC-100n R-1K CN23 +3.3V_S 3 S/PDIF-OUT +5V_S DRIVE IN 2 IC VCC 1 C202 GND HD_SDOUT C199 C200 2F11TC1 CC-100n HD_RST# HD_SYNC CC-100n CC-10u/6.3V R161 R-22 HD_SDIN R162 R-22 HD_BITCLK CN51 C201 1 +5V_S CC-18 2 C399 3 S/PDIF-IN CC-100n 103669-2

CN21 CN22 ABA-JAK-028-K08 ABA-JAK-028-K07

CEN C164 CC-10u/10V L29 FB-BLM15AG601SN1 32 LINE1-L C181 CC-4u7/10V R143 R-1K L37 FB-BLM15AG601SN1 32 R129 R-75 CEN-JD 33 LINE1-JD 33 34 ORANGE 34 LFE C165 CC-10u/10V L30 FB-BLM15AG601SN1 35 LINE1-R C182 CC-4u7/10V R145 R-1K L38 FB-BLM15AG601SN1 35 BLUE R130 R-75 R131 R132 C166 C167 C183 C184 CC-100 CC-100 CC-100 R-22K R-22K CC-100

GND_HDA GND_HDA GND_HDA

SURR-L C168 CC-10u/10V L31 FB-BLM15AG601SN1 22 FRONT-L C185+ CE-100u/10 R146 R-75 L39 FB-BLM15AG601SN1 22 R135 R-75 SURR-JD 23 FRONT-JD 23 24 BLACK 24 SURR-R C169 CC-10u/10V L32 FB-BLM15AG601SN1 25 FRONT-R C186+ CE-100u/10 R148 R-75 L40 FB-BLM15AG601SN1 25 LIME R136 R-75 R137 R138 R150 R151 C187 C188 C170 C171 CC-100 CC-100 CC-100 CC-100 R-22K R-22K R-22K R-22K

GND_HDA GND_HDA GND_HDA GND_HDA MIC1-VREFO-R R155 R-2K2 MIC1-VREFO-L R156 R-2K2

SIDESURR-R C175 CC-10u/10V L34 FB-BLM15AG601SN1 2 MIC1-R C190 CC-4u7/10V R158 R-1K L42 FB-BLM15AG601SN1 2 R139 R-75 SIDESURR-JD 3 MIC1-JD 3 4 GREY 4 SIDESURR-L C178 CC-10u/10V L35 FB-BLM15AG601SN1 5 MIC1-L C196 CC-4u7/10V R160 R-1K L43 FB-BLM15AG601SN1 5 PINK R140 R-75 1 1 R142 R141 C197 C198 C179 C180 CC-100 CC-100 1 2 3 4 2 3 1 4

CC-100 CC-100 G G G G G G G G R-22K R-22K

GND_HDA GND_HDA GND_HDA 3.9.2.2 I²S Implementation Example

The Qseven® V2.0 evaluation carrier board supports an onboard HDA solution and an Audio card interface only. The following I2S Codec Reference schematic has been verified with an external I2S Audio card, available as an option with the reference platform.

The example in Figure 3-24 shows the implementation with a Freescale SGTL5000 I2S Codec (http://www.freescale.com). This HDA Codec has been verified with the Qseven® V2.0 evaluation carrier board.

Figure 3-24 I²S Codec Reference Schematics

+V3.3S

Asynchronous SYS_MCLK input (PLL active) C3 C4 C10uS05V16X C100nS03V50X

FB1 +V3.3S FB120R0A6S03 Q1 VCC_Q24M 4 1 VCC CTRL R9 C6 R1%33RS03 C100nS03V50X CLK_24M I2S_SYS_MCLK 2 GND OUT 3 Q24MV3SB

R10 R1%10kS03 I2S_RST#(2) C8 np

I2S_CPFLT GND_AUD I2S_LRCLK(2) Do Not Stuff I2S_SCLK(2)

U1 4 3 2 1 0 9 8 7 3 2 2 2 2 2 1 1 1 3 USGTL5000 5 4 3 T K K K D O I L L L L C C C A D F C C C N N N P P D S R M D _ V C L _ N _ S S G 2 S I Y 2 I S I2S_MIC_BIAS I2S_SDIN(2) 25 I2S_DOUT MIC_BIAS 16 I2S_MIC I2S_SDOUT(2) 26 I2S_DIN MIC 15 I2S_LIN_L I2C_SDA(2) 27 CTRL_DATA LINEIN_L 14 I2S_LIN_R 28 NC6 LINEIN_R 13 I2S_LOUT_L I2C_SCL(2) 29 CTRL_CLK LINEOUT_L 12 C13 I2S_VDDD 30 11 I2S_LOUT_R C100nS03V50X VDDD LINEOUT_R I2S_VAG 31 CTRL_ADR0_CS VAG 10 32 9 CTRL_MODE NC2 C14

+V3.3S D C100nS03V50X N G 1 2 D A R V L D D N 1 _ _ D _ N N P C P P D G

G H G H V H A N GND_AUD R12 R13 1 2 3 4 5 6 7 8 Do Not Stuff Do Not Stuff np np

I2S_ADR_CS GND_AUD GND_AUD I2S_MODE

I2S_HP_L R14 R15 R1%0R0S03 R1%0R0S03 +V3.3S_AVDD FB3 +V3.3S FB4 FB120R0A6S03 FB120R0A6S03

C16 C17 Place near C100nS03V50X C10uS05V16X I2S_HP_R to codec GND_AUD GND_AUD GND_AUD

XAUDJACKHD_TH_S_BLUE LINE-IN LOOPBACK GND_AUD

X6 I2S_LOUT_L_C I2S_LOUT_R_C 1 1 2 2 I2S_LIN_L_C 3 4 I2S_LIN_R_C I2S_LIN_L_JACK 3 4 I2S_LIN_R_JACK 5 5 6 6

XST2x3S P5 P6 Jumper Set 1-3, 2-4 ... Loopback enabled MJMPR254 MJMPR254 3-5, 4-6 ... Lin-In Jack enabled

X4 I2S_LOUT_L C5 C1u0S03V16X I2S_LOUT_L_C 2 3 4 I2S_LOUT_R C7 C1u0S03V16X I2S_LOUT_R_C 5

XAUDJACKHD_TH_S_LIME LINE-OUT

GND_AUD

X5 I2S_HP_L C9 C100uS10V6X I2S_HP_L_JACK 1 HP_L GND1 4 I2S_HP_R_JACK 2 5 I2S_HP_R C10 C100uS10V6X I2S_MIC_JACK HP_R GND2 3 MIC X4W AYAUDIOJACK

FB2 Headphone, MIC FB120R0A6S03 I2S_MIC C11 C100nS03V50X I2S_MIC_C GND_AUD

I2S_MIC_BIAS R11 R1%2k2S03

C12 C100nS03V50X

GND_AUD

Figure 3-25 External I²S Audio Card Connectors Reference Schematics

+V12

B1 12V_B1 PRSNT1# A1 B2 12V_B2 12V_A2 A2 +V12 B3 12V_B3 12V_A3 A3 B4 GND_B4 GND_A4 A4 I2C_SCL(3) B5 SMCLK HDA_BCLK A5 I2S_SCLK (3) I2C_SDA(3) B6 SMDAT HDA_SDOUT A6 I2S_SDOUT (3) +V3.3S B7 GND_B7 HDA_SDIN A7 I2S_SDIN (3) B8 3.3V_B8 HDA_SYNC A8 I2S_LRCLK (3) I2S_RST#(3) B9 HDA_RST# 3.3V_A9 A9 +V3.3S B10 3.3VAUX 3.3V_A10 A10 B11 WAKE# PWRGD A11 KEY B12 SPKR GND_A12 A12 B13 GND_B13 RVSD_A13 A13 B14 A14 X2 RVSD_B14 RVSD_A14 B15 RVSD_B15 GND_8 A15 1 B16 A16 1 HDA_SEL_SLT# GND_B16 RVSD_A16 2 2 B17 PRSNT2# RVSD_A17 A17 3 3 B18 GND_B18 GND_A18 A18 XST1x3S R8 Do Not Stuff P4 PACC2LA0

MJMPR254 1-2: SDIN from baseboard 2-3: SDIN from ACC2 card (default)

•

The Qseven® V2.0 evaluation carrier board supports an onboard HDA solution and an Audio card interface only. The following AC97 Codec Reference schematic has not been verified with this board.

The example in Figure 3-26 shows the implementation of the VIA technologies VT 1613 AC97 Codec Chip (http://www.via.com.tw) as used on the Qseven® V1.2 evaluation carrier board.

There are two options for digital input/output: Option 1 supports coaxial S/PDIF input/output. Option 2 supports optical S/PDIF (Toslink) input/output.

Figure 3-26 AC97 Codec Reference Schematics FRONT_OUT

CN1B

HP_OUT_L 1 2 22 R8 330 C21 1uF CD_L + CE1220uF R100 FB5 120ohm@100MHz 23 CD_IN 24 G3

HP_OUT_R 1 2 25 G4 C22 R9 + CE2220uF R120 FB6 GREEN CD_IN1 2700pF 100K 120ohm@100MHz 1 2 C23 1uF CD_GND C26 C27 P21-110-0007 3 Please near to codec (U1) 1000pF 1000pF 4

A151804-5 GND_AUD C24 R11 2700pF 100K R13 330 C25 1uF CD_R MIC1_IN AUX-IN VREF_OUT1 R164.7K Please near to codec (U1) R194.7K AUX_IN_1 1 R14 330 C28 1uF AUX_IN_L CN1A 2 MIC1_L C3210uF R20330 FB7 2 3 120ohm@100MHz 3 4 R15 330 C29 1uF AUX_IN_R 4 G1 MIC2_R C3310uF R21330 FB8 5 G2 PINK A151804-5 120ohm@100MHz 1 C30 R17 C31 R18 2700pF 100K 2700pF 100K C34 C35 P21-110-0007 Please near to codec (U1) 1000pF 1000pF

GND_AUD GND_AUD

R22 10K C36 1uF PC_BEEP Q7_SPKR LINE1_IN R23 C37 10K 100pF

CN1C LINE_IN_L C3810uF R24330 FB9 32 33 SYNC 120ohm@100MHz AC97_SYNC 34 G5 SDIN AC97_SDI SDOUT LINE_IN_R C3910uF R25330 FB10 35 BLUE AC97_SDO RST 120ohm@100MHz AC97_RST# BIT_CLK AC97_BCLK C40 C41 P21-110-0007 Please near to codec (U1) 1000pF 1000pF

C42 C43 C44 R26 C45 C46 GND_AUD 22pF 22pF 22pF 10K 22pF 22pF

AFILT2 +5V AFILT1 VREF_OUT1 OPTION-1 VREF L14.7uH

SPDIF1 C100.1uF 1 SPDIF_IN C110.01uF 2

+3.3V +3.3VCODEC 6 5 4 3 2 1 0 9 8 7 U1 +5VAUD +5V 3 3 3 3 3 3 3 3 2 2 2 1 25

FB1 L 7 8 2 1 1 FB2 SPDIF R C N D I _

DVCC1 T T T AVCC1 _ C C E 120ohm@100MHz 9 N 38 120ohm@100MHz L L T U M T N N I I DVCC2 S AVCC2 / U V 2 F F U O I

C7 C8 C9 O C12 C13 C14 X A A F O

_ / +5V _ E U

E E 4 A R 26 10uF 0.1uF 0.01uF C 0.01uF 0.1uF 10uF SPDIF2 N V V N

DGND1 I AGND1 N 7 I 42 FB3 C150.1uF 1 L DGND2 L AGND2 120ohm@100MHz SPDIF_OUT 2 37 GND_AUD 3 NC1 R1 HP_OUT_L 39 24 LINE_IN_R 4.7K SPDIF 40 HP_OUT_L / NC LINE_IN_R 23 LINE_IN_L HP_OUT_R 41 NC2 LINE_IN_L 22 MIC2_R HP_OUT_R / NC MIC2 / NC 21 MIC1_L 43 MIC1 20 CD_R 44 NC3 CD_R 19 CD_GND 45 NC4 CD_GND 18 CD_L 46 GPIO0 / SDATA_OUT1 CD_L 17 SPDIF_IN 47 XTL_SEL / SDA NC5 16 SPDIF_OUT 48 EAPD/SPDIF_IN / SCL NC6 15 AUX_IN_R SPDIF_OUT AUX_R OPTION-2

K 14 AUX_IN_L K L K C AUX_L

L 13 L C N

C SPDIF_OUT T PHONE / NC S C 12 PC_BEEP /

U M R

/ SPDIF_IN

N PC_BEEP / NC

L T O I / K

_ _ # U / L

T A N A I O C T T C E _ _ _ A A S N L L +3.3V T E I D T T D Y

X X S B S S R C16 0.01uF 5 4

2 3 5 6 8 0 1 TORX141P TOTX141P VT1613_LQFP48 1 1

VREF_OUT1 C1 10uF 5 4 C 1 3 C

N Vout In N C2 0.1uF R2 22 RST 2 FB4 2 R3 22 SYNC GND 4.7uH VCC AFILT1 C3 270pF SDIN X1 R4 22 3 1 1 2 R5 22 BIT_CLK 4 Vcc GND 5 AFILT2 C4 270pF SDOUT C C R6 22 N N C18 24.576MHz C17 R7 0.1uF VREF C5 10uF 4 5 0.1uF 4.7K C19 C20 C6 0.1uF 22pF 22pF

GND_AUD

Qseven Design Guide Page 68 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.9.3 HDA / AC97 / I2S Placement and Routing Guidelines The implementation of proper component placement and routing techniques will help to ensure that the maximum performance available from the codec is achieved. Routing techniques that should be observed include properly isolating the codec, associated audio circuitry, analog power supplies, and analog ground planes from the rest of the carrier board. This includes split planes and the proper routing of signals not associated with the audio section.

The following is a list of basic recommendations:

• Traces must be routed with a target impedance of 55Ω with an allowed tolerance of ± 15%.

• Ground return paths for the analog signals must be given special consideration.

• Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split lines. Locate the analog and digital signals as far as possible from each other.

• Partition the carrier board with all analog components grouped together in one area and all digital components in another.

• Keep digital signal traces, especially the clock, as far as possible from the analog input and voltage reference pins.

• Provide separate analog and digital ground planes with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane. The split between planes must be a minimum of 0.05 inch wide.

• Route analog power and signal traces over the analog ground plane.

• Route digital power and signal traces over the digital ground plane.

• Position the bypassing and decoupling capacitors close to the IC pins, or position the capacitors for the shortest connections to pins, with wide traces to reduce impedance.

• Do not completely isolate the analog/audio ground plane from the rest of the carrier board ground plane. Provide a single point (0.25 inch to 0.5 inch wide) where the analog/isolated ground plane connects to the main ground plane. The split between planes must be a minimum of 0.05 inch wide.

• Any signals entering or leaving the analog area must cross the ground split in the area where the analog ground is attached to the main carrier board ground. That is, no signal should cross the split/gap between the ground planes, which would cause a ground loop, thereby greatly increasing EMI emissions and degrading the analog and digital signal quality.

Qseven Design Guide Page 69 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.10 LVDS Flat Panel Signals The Qseven® 2.0 specification defines a LVDS flat panel interface that optionally supports up to two 24-bit LVDS channels. It permits dual pixel, two channel data transmission between the host and flat panel display. Each LVDS channel consists of up to five LVDS signal pairs transmitting a serial bit stream directly to a LVDS flat panel or to an external LVDS receiver. Additional control signals, as well as a dedicated I²C bus interface, are specified to control flat panel attributes. This dedicated I²C bus can be used to connect an external I²C EEPROM containing the specific timing data of the flat panel display.

Note 1. Some LVDS Signal Pins share signals with eDP since Version 2.0 2. eDP is a new standard for internal display interfaces.

3.10.1 LVDS Flat Panel Interface Signals Table 3-22 LVDS Signals

Signal Shared with Pin Description I/O Type IOL/IIL I/O # (Signal) LVDS_PPEN 111 Controls panel power enable. CMOS 3.3V max 1mA O LVDS_BLEN 112 Controls panel backlight enable. CMOS 3.3V max 1mA O LVDS_BLT_CTRL GP_PWM_OUT0 123 Primary functionality is to control the panel CMOS 3.3V O backlight brightness via pulse width modulation (PWM). When not in use for this purpose it can be used as General Purpose PWM Output. LVDS_A0+ eDP0_TX0+ 99 LVDS primary channel LVDS O LVDS_A0- eDP0_TX0- 101 differential pair 0. LVDS_A1+ eDP0_TX1+ 103 LVDS primary channel LVDS O LVDS_A1- eDP0_TX1- 105 differential pair 1. LVDS_A2+ eDP0_TX2+ 107 LVDS primary channel LVDS O LVDS_A2- eDP0_TX2- 109 differential pair 2. LVDS_A3+ eDP0_TX3+ 113 LVDS primary channel LVDS O LVDS_A3- eDP0_TX3- 115 differential pair 3. LVDS_A_CLK+ eDP0_AUX+ 119 LVDS primary channel LVDS O LVDS_A_CLK- eDP0_AUX- 121 differential pair clock lines. LVDS_B0+ eDP1_TX0+ 100 LVDS secondary channel LVDS O LVDS_B0- eDP1_TX0- 102 differential pair 0. LVDS_B1+ eDP1_TX1+ 104 LVDS secondary channel LVDS O LVDS_B1- eDP1_TX1- 106 differential pair 1. LVDS_B2+ eDP1_TX2+ 108 LVDS secondary channel LVDS O LVDS_B2- eDP1_TX2- 110 differential pair 2. LVDS_B3+ eDP1_TX3+ 114 LVDS secondary channel LVDS O LVDS_B3- eDP1_TX3- 116 differential pair 3. LVDS_B_CLK+ eDP1_AUX+ 120 LVDS secondary channel LVDS O LVDS_B_CLK- eDP1_AUX- 122 differential pair clock lines. LVDS_DID_CLK GP_I2C_CLK 127 Primary functionality is DisplayID DDC clock CMOS 3.3V O line used for LVDS flat panel detection. OD If primary functionality is not used it can be used as General Purpose I²C bus clock line.

Qseven Design Guide Page 70 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. Signal Shared with Pin Description I/O Type IOL/IIL I/O # (Signal) LVDS_DID_DAT GP_I2C_DAT 125 Primary functionality DisplayID DDC data line CMOS 3.3V I/O used for LVDS flat panel detection. If primary OD functionality is not used it can be used as General Purpose I²C bus data line. LVDS_BLC_CLK eDP1_HPD# 128 Control clock signal CMOS 3.3V I/O for external SSC clock chip. OD LVDS_BLC_DAT eDP0_HPD# 126 Control data signal CMOS 3.3V I/O for external SSC clock chip. OD

Note

1. ALL pull ups/downs are to be on the module.

2. The LVDS flat panel configuration within the BIOS of the Qseven® module shall be implemented in accordance to the DisplayID specification from the Video Electronics Standards Association (VESA). For more information about the LVDS flat panel configuration with DisplayID refer to the specification 'Display Identification Data (DisplayID) Structure Version 1.0' that is available on the web page of the Video Electronics Standards Association (VESA).

3.10.2 LVDS Implementation Guidelines Many carrier board designs do not need the full range of LVDS performance offered by Qseven® modules. It depends on the flat panel configuration of the Qseven® module, as well as the carrier board design, as to how many LVDS signal pairs are supported. While the dual channel 24-bit LVDS configuration needs all 10 LVDS signal pairs, a single channel 18-bit LVDS configuration only requires 4 LVDS signal pairs. In this case all unused LVDS signal pairs should be left open on the carrier board.

If the LVDS display interface of the Qseven® module is not implemented, all signals associated with this interface should be left open.

3.10.2.1 Connector and Cable Considerations The SGeT e.V. doesn't define the connector layout for interfacing LVDS on the Qseven® carrier board design. It is up to the system designer and the system requirements as to which connectors and which pinout will be used for the application. The following example in Figure 3-27 is taken from the Qseven® V2.0 Reference Carrier Board and should only be considered as an example of how to implement the LVDS interface on the carrier board.

CN1 L3 FB-BLM18PG121SN1 2 1 L6 FB-BLM18PG121SN1 LVDS_DID_DAT[2] LVDS_DID_CLK [2] 4 3

6 5 LVDS_AN0

LVDS_AP0 8 7 VDDON

LVDS_AN1 10 9 LVDS_AP1

BLON 12 11 LVDS_AP2

LVDS_AN2 14 13

LVDS_ACKN 16 15 LVDS_ACKP

LVDS_BLT_CTRL 18 17 LVDS_AP3

LVDS_AN3 20 19

LVDS_BN0 22 21 LVDS_BP0

24 23 LVDS_BN1

LVDS_BP1 26 25

LVDS_BN2 28 27 LVDS_BP2

30 29 LVDS_BCKP

LVDS_BCKN 32 31

LVDS_BP3 34 33 LVDS_BN3

A2004WR-2*17P

When implementing LVDS signal pairs on a single-ended carrier board connector, the signals of a pair should be arranged so that the positive and negative signal are side by side. The trace lengths of the LVDS signal pairs between the Qseven® module and the connector on the carrier board should be the same when possible. Additionally, one or more ground traces/pins must be placed between the LVDS pairs.

Balanced cables (twisted pair) are usually better than unbalanced cables (ribbon cable) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common-mode noise, which is rejected by the receiver.

Twisted pair cables provide a low-cost solution with good balance and flexibility. They are capable of medium to long runs depending upon the application skew budget. A variety of shielding options are available.

Ribbon cables are a cost effective and easy solution. Even though they are not well suited for high-speed differential signaling they do work fine for very short runs. Most cables will work effectively for cable distances of <0.5m.

The cables and connectors that are to be utilized should have a differential impedance of 100Ω ±15%. They should not introduce major impedance discontinuities that cause signal reflections.

For more information about this subject refer to the 'LVDS Owners Manual Chapter 6' available from Texas Instruments (http://www.ti.com).

3.10.2.2 Display Timing Configuration Usually the timing parameters for the flat panel display are stored in an external EEPROM that is implemented on the Qseven V2.0 Reference Carrier Board. It is accessible through the dedicated LVDS I²C bus via the signals 'LVDS_DID_CLK' and 'LVDS_DID_DAT', which can be found on the module's connector (pin 125 resp. pin 127). During POST the module's BIOS reads out the display timing data from the EEPROM and configures the module's graphics controller for proper flat panel operation. In order to be able to do this, the device address of the LVDS I²C EEPROM must be strapped to 0xA0.

Qseven Design Guide Page 72 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. For more information about the LVDS flat panel configuration with DisplayID refer to the specification 'Display Identification Data (DisplayID) Structure Version 1.0' that is available on the webpage of the Video Electronics Standards Association (VESA) (http://www.vesa.org).

Figure 3-28 LVDS I²C EEPROM

+3.3V_S_LVDS

CN2 1 8 C9 CC-100K

2 7

3 6 LVDS_DID_CLK

4 5 LVDS_DID_DAT

808-AG11D-ESL-LF

Note

Required pull ups/downs are integrated on the module.

3.10.2.3 Backlight Control The following LVDS reference circuitry shows a backlight control solution . The signal level of the signals coming from the module must be adapted to the specified level of the used devices. In the example used on the Qseven V2.0 Reference Carrier Board the signals LVDS_BLT_CTRL , LVDS_DID_DAT and LVDS_DID_CLK can level shifted by using the Backlight Logic Voltage Selection shown in Figure 3-29. The backlight supply voltage selection shown in the same figure allows adaption of the backlight supply voltage VDD to 5V or 12V

Backlight control is part of the EAPI ( Embedded Application Programmer Interface) API and can be accessed by using the 32bit API functions. For more details about EAPI refer to the Qseven specification and the module vendor's EAPI Programmers Guide.

Figure 3-29 LVDS Backlight and Panel Supply Voltage Control Circuitry

LVDS Backlight Connector +3.3V_S_LVDS R29 R-10K LVDS_BLT_CTRL_PWM 6 Q2A 2N7002DW 2 Package = 2 +3.3V_S_LVDS

1 +5V_S

R30 C10 CC-100K

5 U3 R-10K R31 R-10K 1 + C11 4 3 3 - CC-10u/6.3V Q2B LMV931SQ3T2G 5 2N7002DW 2 LVDS_BLT_CTRL[2] Package = 2

4 R32 R-20K R33 R-10K

CN3 +12V_S_LVDS +5V_S SW_VDD F1 nanoSMDC075F SW_VDD_FUSE 1 2 SW_BACK_FUSE F2 miniSMDC075F SW_BACK

F3 nanoSMDC075F 5V_FUSE 3 4 12V_FUSE F4 miniSMDC075F

VDDON 5 6 BLON

LVDS_BKL_DIMMING 7 8 LVDS_BLT_CTRL_PWM

9 10

70247-1054

Qseven Design Guide Page 73 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. LVDS Backlight Supply Voltage Selection P1 set jumper 1-2 for 12V backlight voltage (default) set jumper 2-3 for 5V backlight voltage SHORTING_PLUG

Q7 JP1 +12V_S_LVDS 8 SW_BACK 1 1 7 C1 C2 2 6 2 3 5 CC-100K/25V CC-10K +5V_S 3 SiSS27DN 4 R21 R-10K D1 1PS79SB40 JP-3X1

R23 R-100K +3.3V_S_LVDS C5

CC-100K/25V C6

CC-100K R25 R-0/X 6

5 U1 Q1A 1 2N7002DW LVDS_BLEN[2] 3 4 BLON 2 LVDS_RST#[1,2] Package = 1 6 +5V_S_PG_LVDS[1,2]

NC7SZ11P6X 1 R27 2 R-100K

LVDS Digital Logic Voltage Selection set jumper 1-2 for 5V digital voltage P2 set jumper 2-3 for 3.3V digital voltage (default) SHORTING_PLUG

JP2 +5V_S Q8 1 SI2333CDS

2 SW_VDD +3.3V_S_LVDS 3 C3 C4 R22 R-10K D2 1PS79SB40 JP-3X1 CC-100K/25V CC-10K

R24 R-100K +3.3V_S_LVDS C7

CC-100K/25V C8

CC-100K

R26 R-0/X 3

5 U2 Q1B 1 LVDS_PPEN[2] 3 4 VDDON 5 2N7002DW LVDS_RST#[1,2] 6 Package = 1 +5V_S_PG_LVDS[1,2]

NC7SZ11P6X 4 R28 2 R-100K

Note

Displays with LED backlight may use PWM for brightness control.

3.10.3 Routing Considerations for LVDS See section 4 of this document for trace routing guidelines and the Qseven specification and the 'LVDS Owners Manual Chapter 3' from Texas Instruments (http://www.ti.com) for more information about this subject.

Qseven Design Guide Page 74 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.11 Embedded DisplayPort (eDP) Qseven® Rev 2.0 modules optionally support up to two Embedded DisplayPort (eDP) Version 1.2 interfaces. These interfaces are shared with LVDS signals.

eDP is an open, industry standard digital display interface that is under development within the Video Electronics Standards Association (VESA). The eDP specification defines a scalable digital display interface. It defines a license-free, royalty-free, state- of-the-art digital video interconnect intended to be used primarily between a computer and its internal display(s). The eDP interface supports 1, 2, or 4 data pairs that carry the video signal and embeds the clock in the data signal. The eDP interface is designed to replace LVDS as an internal Graphics interface in the coming years. Benefits are embedded clock, higher data rates and less data lines than with LVDS. EDP support is offered by ARM and x86 processor based platforms, depending on the selected processor. AC coupling is provided on the module. If the eDP display interface of the Qseven® module is not implemented, all signals associated with this interface should be left open.

3.11.1 eDP Interface Signals Table 3-23 Embedded DisplayPort Signals

Signal Shared with Pin# Description I/O Type IOL/IIL I/ (Signal) O eDP0_TX0+ LVDS_A0+ 99 eDP primary channel PCIe O eDP0_TX0- LVDS_A0- 101 differential pair Lane 0. eDP0_TX1+ LVDS_A1+ 103 eDP primary channel PCIe O eDP0_TX1- LVDS_A1- 105 differential pair Lane 1. eDP0_TX2+ LVDS_A2+ 107 eDP primary channel PCIe O eDP0_TX2- LVDS_A2- 109 differential pair Lane 2. eDP0_TX3+ LVDS_A3+ 113 eDP primary channel PCIe O eDP0_TX3- LVDS_A3- 115 differential pair Lane 3. eDP0_AUX+ LVDS_A_CLK+ 119 eDP primary channel PCIe I/O eDP0_AUX- LVDS_A_CLK- 121 differential pair Auxiliary Channel used for link management and device control. eDP0_HPD# LVDS_BLC_DAT 126 eDP primary channel CMOS 3.3V OD I Hot Plug Detect. eDP1_TX0+ LVDS_B0+ 100 eDP secondary channel PCIe O eDP1_TX0- LVDS_B0- 102 differential pair Lane 0. eDP1_TX1+ LVDS_B1+ 104 eDP secondary channel PCIe O eDP1_TX1- LVDS_B1- 106 differential pair Lane 1. eDP1_TX2+ LVDS_B2+ 108 eDP secondary channel PCIe O eDP1_TX2- LVDS_B2- 110 differential pair Lane 2. eDP1_TX3+ LVDS_B3+ 114 eDP secondary channel PCIe O eDP1_TX3- LVDS_B3- 116 differential pair Lane 3. eDP1_AUX+ LVDS_B_CLK+ 120 eDP secondary channel PCIe I/O eDP1_AUX- LVDS_B_CLK- 122 differential pair Auxiliary Channel used for link management and device control. eDP1_HPD# LVDS_BLC_CLK 128 eDP secondary channel CMOS 3.3V OD I Hot Plug Detect.

Qseven Design Guide Page 75 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.11.2 eDP Implementation Guidelines Many carrier board designs do not need the full range of eDP performance offered by Qseven® modules. It depends on the flat panel configuration of the Qseven® module, as well as the carrier board design, as to how many eDP lanes are supported. In this case all unused eDP signal lanes should be left open on the carrier board. If the eDP display interface of the Qseven® module is not implemented at all, non-shared signals associated with this interface should be left open.

3.11.2.1 Connector and Cable Considerations The SGeT e.V. doesn't define the connector layout for interfacing eDP on the Qseven carrier board design. It is up to the system designer and the system requirements as to which connectors and which pinout will be used for the application. The following examples in Table 3-24 and Table 3-25 are taken from the Qseven® V2.0 Reference Carrier Board and should only be considered as an example of how to implement the eDP interface on the carrier board. However it is recommended to follow the VESA guidelines for eDP connectors. The examples below implement up to 2 lanes (30 pin) and up to 4 lanes (40 pin).

Table 3-24 Pinout Embedded DisplayPort Connector (eDP) 30 Pin on Baseboard

Pin# Signal Description Pin# Signal Description 1 n/c Rsvd. for LCD Manufacturer's Use 2 BACK Backlight Power (5V or 12V) 3 BACK Backlight Power (5V or 12V) 4 BACK Backlight Power (5V or 12V) 5 BACK Backlight Power (5V or 12V) 6 n/c Rsvd. for LCD Manufacturer's Use 7 n/c Rsvd. for LCD Manufacturer's Use 8 eDP_BLT_CTRL Backlight PWM Dimming Control* 9 BLON_eDP Backlight enable (on/off)* 10 GND Backlight Ground 11 GND Backlight Ground 12 GND Backlight Ground 13 GND Backlight Ground 14 eDP_HPD# Hot Plug Detect 15 GND Logic Ground 16 GND Logic Ground 17 n/c LCD Self Test Enable* 18 VDD_eDP Logic Power (3.3V or 5V) 19 VDD_eDP Logic Power (3.3V or 5V) 20 GND Signal Ground 21 DP_AUX- Auxiliary Channel (negative) 22 DP_AUX+ Auxiliary Channel (positive) 23 GND Signal Ground 24 eDP_TX0+ eDP Lane 0 (positive) 25 eDP_TX0- eDP Lane 0 (negative) 26 GND Signal Ground 27 eDP_TX1+ eDP Lane 1 (positive) 28 eDP_TX1- EDP Lane 1 (negative) 29 GND Signal Ground 30 n/c Rsvd. for LCD Manufacturer's Use

* denotes optional signals

Pin# Signal Description Pin# Signal Description 1 n/c Rsvd. for LCD Manufacturer's Use 2 BACK Backlight Power (5V or 12V) 3 BACK Backlight Power (5V or 12V) 4 BACK Backlight Power (5V or 12V) 5 BACK Backlight Power (5V or 12V) 6 n/c Rsvd. for LCD Manufacturer's Use 7 n/c Rsvd. for LCD Manufacturer's Use 8 eDP_BLT_CTRL Backlight PWM Dimming Control* 9 BLON_eDP Backlight enable (on/off)* 10 GND Backlight Ground 11 GND Backlight Ground 12 GND Backlight Ground 13 GND Backlight Ground 14 eDP_HPD# Hot Plug Detect 15 GND Logic Ground 16 GND Logic Ground 17 GND Logic Ground 18 GND Logic Ground 19 n/c LCD Self Test Enable* 20 VDD_eDP Logic Power (3.3V or 5V) 21 VDD_eDP Logic Power (3.3V or 5V) 22 VDD_eDP Logic Power (3.3V or 5V) 23 VDD_eDP Logic Power (3.3V or 5V) 24 GND Signal Ground 25 DP_AUX- Auxiliary Channel (negative) 26 DP_AUX+ Auxiliary Channel (positive) 27 GND Signal Ground 28 eDP_TX0+ eDP Lane 0 (positive) 29 eDP_TX0- eDP Lane 0 (negative) 30 GND Signal Ground 31 eDP_TX1+ eDP Lane 1 (positive) 32 eDP_TX1- eDP Lane 1 (negative) 33 GND Signal Ground 34 eDP_TX2+ eDP Lane 2 (positive) 35 eDP_TX2- EDP Lane 2 (negative) 36 GND Signal Ground 37 eDP_TX3+ eDP Lane 3 (positive) 38 eDP_TX3- EDP Lane 3 (negative) 39 GND Signal Ground 40 n/c Rsvd. for LCD Manufacturer's Use

* denotes optional signals

Note 1. As the VESA Guidelines for the pin out of the eDP Connector refers to the panel connector the signal numbering of the connector on the baseboard appears in reverse order. 2. Depending on the Type of FlatPanel Display used an Inverter for the HotPlugDetect signal may be required. 3. eDP switches may be used to link both types of connectors (30 pin and 40 pin) to the same eDP channel (primary or secondary).

30 Pin eDP Connector 40 Pin eDP Connector

CN6 CN5

1 1 SW_BACK_FUSE_eDP 2 SW_BACK_FUSE_eDP 2 3 3 4 4 5 5 6 6 7 7 eDP_BLT_CTRL 8 eDP_BLT_CTRL 8 eDP_BLT_CTRL BLON_eDP 9 BLON_eDP 9 10 10 11 11 12 12 13 13 eDP0_HPD 14 eDP0_HPD 14 15 15 16 16 17 17 SW_VDD_FUSE_eDP 18 18 19 19 20 20 21 21 eDP0_AUX- 22 22 eDP0_AUX+ 23 SW _VDD_FUSE_eDP 23 24 24 eDP0_TX0+ 25 25 eDP0_TX0- eDP0_AUX- 26 26 eDP0_AUX+ 27 27 eDP0_TX1+ 28 28 eDP0_TX1- eDP0_TX0+ 29 29 eDP0_TX0- 30 30 31 eDP0_TX1+ 32 eDP0_TX1- 20455-030E-02S 33 34 eDP0_TX2+ 35 eDP0_TX2- 36 37 eDP0_TX3+ 38 eDP0_TX3- 39 40

20455-040E-02S

HotPlugDetect Signal Inverter When implementing eDP signal pairs on a single-ended carrier board connector, the signals of a pair should be arranged so that the positive and negative signal are side by side. The trace lengths of the eDP signal pairs must be length matched. Additionally, one or more ground traces/pins must be placed between the eDP pairs.

Micro coaxial cables are the first choice to connect eDP devices.

The cables and connectors that are to be utilized should have a differential impedance of 100Ω ±15%. They should not introduce major impedance discontinuities that cause signal reflections.

3.11.2.2 Display Timing All display timing information (i.e. pixel clock,Hsync, Vsync) and video information (bits- per-pixel, color space, etc.). video data error correction and optional audio data are carried in the eDP main link. EDID information (display format information), link training protocol, display control (from eDP1.2), power management and error checking of main link data (CRC protocol) are carried in the eDP AUX channel.

Qseven Design Guide Page 78 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.11.2.3 eDP Backlight and Panel Voltage Control The following eDP reference circuitry shows a panel Voltage control solution. The signal level of the signals coming from the module must be adapted to the specified signals/voltage level of the used devices on the panel display. In the example shown in Figure 3-31, which is used on the Qseven V2.0 Reference Carrier Board, the supply voltage for the display can be set to 12V or 5V via jumper JP3, and the supply voltage for the digital electronics circuitry can be set to 3.3V or 5V via jumper JP4.

Figure 3-31 eDP Backlight and Panel Voltage Control

eDP Backlight Supply Voltage Selection

set jumper 1-2 for 12V backlight voltage (default) P4 set jumper 2-3 for 5V backlight voltage SHORTING_PLUG

JP3 +12V_S_EDP Q9 1 8 1 7 2 2 6 SW_BACK_eDP +5V_S 3 5 3 R42 R-10K D5 1PS79SB40 SiSS27DN C19 C20 JP-3X1 4 CC-100K/25V CC-10K R45 R-100K

C23 +3.3V_S_EDP CC-100K/25V

C26

CC-100K/25V

R47 R-0/X 6

5 U6 Q5A 1 eDP_BLEN 2N7002DW 3 4 BLON_eDP 2 Package = 5 SW_BACK_eDP F6 miniSMDC075F SW _BACK_FUSE_eDP eDP_RST# 6 +5V_S_PG_eDP

NC7SZ11P6X 1 2

R49 R-100K

eDP Digital Logic Voltage Selection

set jumper 1-2 for 5V digital voltage P2 set jumper 2-3 for 3.3V digital voltage (default) SHORTING_PLUG

JP2 +5V_S Q8 1 SI2333CDS

2 SW_VDD +3.3V_S_LVDS 3 C3 C4 R22 R-10K D2 1PS79SB40 JP-3X1 CC-100K/25V CC-10K

R24 R-100K +3.3V_S_LVDS C7

CC-100K/25V C8

CC-100K

R26 R-0/X 3

5 U2 Q1B 1 LVDS_PPEN[2] 3 4 VDDON 5 2N7002DW LVDS_RST#[1,2] 6 Package = 1 +5V_S_PG_LVDS[1,2]

NC7SZ11P6X 4 R28 2 R-100K

3.11.3 Routing Considerations for eDP Embedded Display Port is based on PCI Express signal technology.

Please see instructions for PCI Express technology in section 4 of this document for trace routing guidelines and the Qseven® specification for more information about this subject.

3.12.1 DisplayPort Interface Signals (from Module) Qseven® Rev 2.0 modules optionally support one DisplayPort Version 1.2 interface. This interface is shared with TMDS signals.

DisplayPort is an open, industry standard digital display interface that is under development within the Video Electronics Standards Association (VESA). The DisplayPort specification defines a scalable digital display interface with optional audio and content protection capability. It defines a license-free, royalty-free, state-of-the-art digital audio/video interconnect intended to be used primarily between a computer and its display monitor.

The DisplayPort interface supports 1, 2, or 4 data pairs that carry the video signal, clock and optional audio signals. The video signal of the DisplayPort interface is not compatible with DVI or HDMI but a DisplayPort connector can pass these signals through. While DVI and HDMI require separate clock signals, DisplayPort embeds the clock in the data signal. Unlike the separate DVI/HDMI and LVDS standards, DisplayPort supports both external (monitor) or internal (LCD panel) display connections.

Display Port++ (also known as dual-mode DisplayPort) output signals can easily provide the lower voltages required for Display Port using a passive adapter. This enables cost- efficient direct support for single-link HDMI and DVI signals. Dual-mode chipsets are able to detect when a DVI or HDMI passive adapter is connected and then switch to DVI/HDMI mode using the 4-lane main DisplayPort link and the AUX channel link to transmit 3 TMDS signals, clock and display data channel Data and Clock. Dual-mode compatible devices are recognizable by the DP++ logo.

Note

AC coupling is provided on the module for the main link, auxiliary channel needs AC coupling on the carrier board. DP/DP++ use the same (shared) pins as TMDS to transmit the DP/DP++ graphics signals (see below).

Table 3-26 Signal Definition DisplayPort

Signal Shared With Pin# Description I/O Type IOL/IIL Module I/O DP_LANE3- TMDS_CLK- 133 DisplayPort differential pair lines lane 3. PCIe O DP_LANE3+ TMDS_CLK+ 131 DP_LANE2- TMDS_LANE0- 145 DisplayPort differential pair lines lane 2. PCIe O DP_LANE2+ TMDS_LANE0+ 143 DP_LANE1- TMDS_LANE1- 139 DisplayPort differential pair lines lane 1. PCIe O DP_LANE1+ TMDS_LANE1+ 137 DP_LANE0- TMDS_LANE2- 151 DisplayPort differential pair lines lane 0. PCIe O DP_LANE0+ TMDS_LANE2+ 149 DP_AUX- 140 Auxiliary channel used for link management PCIe I/O DP_AUX+ 138 and device control. Differential pair lines. DP_HPD# 154 Hot plug detection signal that serves as an CMOS I interrupt request. 3.3V

Support of the DisplayPort interface is chipset dependent and therefore may not be available on all Qseven® modules. It is available with most X86 processor technology based modules and some ARM processor technology based modules.

DisplayPort interface signals are shared with the signals for the TMDS interface (SDVO is no longer supported with Qseven V2.0).

DisplayPort

V1.2 introduces a new, HBR2 mode with a higher data rate of 5.4 Gb/s for increased resolutions and refresh rates as well as multiple independent video streams (daisy- chain connection with multiple monitors).

3.12.1.1 DisplayPort Connector Signals Figure 3-32 DisplayPort Connector

Table 3-27 Pinout DisplayPort Connector

Pin# Signal Description Pin# Signal Description 1 DP_LANE0+ DisplayPort Lane 0 (positive) 2 GND Ground 3 DP_LANE0- DisplayPort Lane 0 (negative) 4 DP_LANE1+ DisplayPort Lane 1 (positive) 5 GND Ground 6 DP_LANE1- DisplayPort Lane 1 (negative) 7 DP_LANE2+ DisplayPort Lane 2 (positive) 8 GND Ground 9 DP_LANE2- DisplayPort Lane 2 (negative) 10 DP_LANE3+ DisplayPort Lane 3 (positive) 11 GND Ground 12 DP_LANE3- DisplayPort Lane 3 (negative) 13 CONFIG1 Configuration Pin 1 (connected to 14 CONFIG2 Configuration Pin 2 (connected to Ground via 1M resistor) Ground) 15 DP_AUX+ Auxiliary Channel (positive) 16 GND Ground 17 DP_AUX- Auxiliary Channel (negative) 18 DP_HPD# Hot Plug Detect 19 RETURN Return For Power 20 DP_PWR Power For Connector

Qseven Design Guide Page 81 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.12.2 DP++ to DVI or HDMI Transmitter Reference Circuitry The following circuitry shows an example of how to connect a NXP PTN3380B active level shifter (http://www.nxp.com) directly to the Qseven® module. The Qseven V2.0 refernce carrier board is implemented differently. It uses an external graphics adapter does not include an onboard level shifter for external graphics output. For details please see the Qseven V2.0 reference carrier board manual.

Figure 3-33 DP++ to DVI/HDMI Transmitter Reference Circuitry using an active level shifter VCC3V3 U1 2 25 2 1 VCC3V3 11 VDD_2 OE_N R1 0R 15 VDD_11 2 1

1 1 1 1 1 1 1 1 GND 21 VDD_15 R2 0R NO C1 C2 C3 C4 C5 C6 C7 C8 26 VDD_21 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 33 VDD_26 40 VDD_33 32 2 1

2 2 2 2 2 2 2 2 VCC3V3 46 VDD_40 DDC_EN R3 0R VDD_46 2 1 GND 1 R4 0R NO 5 GND_1 12 GND_5 GND_12 GND 18 6 2 1 VCC3V3 24 GND_18 REXT R5 0R NO GND_24 27 2 1 GND 31 GND_27 3 R6 10k HDMI 37 GND_31 NC_3 4 43 GND_37 NC_4 10 GND_43 NC_10 License is necessary!

X1 39 22 HDMI_D2+_X 1 DP_LANE0+ [P149] HDMI_D2+ 38 IN_D1+ OUT_D1+ 23 HDMI_D2- 2 TMDS Data2+ DP_LANE0- [P151] IN_D1- OUT_D1- HDMI_D2-_X 3 TMDS Data2 Shield 42 19 HDMI_D1+ HDMI_D1+_X 4 TMDS Data2- DP_LANE1+ [P137] 41 IN_D2+ OUT_D2+ 20 HDMI_D1- 5 TMDS Data1+ DP_LANE1- [P139] IN_D2- OUT_D2- HDMI_D1-_X 6 TMDS Data1 Shield 45 16 HDMI_D0+ HDMI_D0+_X 7 TMDS Data1- DP_LANE2+ [P143] IN_D3+ OUT_D3+ TMDS Data0+ DP_LANE2- [P145] 44 17 HDMI_D0- 8 IN_D3- OUT_D3- HDMI_D0-_X 9 TMDS Data0 Shield HDMI_CLK+_X 10 TMDS Data0- DP_LANE3+ [P131] 48 13 HDMI_CLK+ 47 IN_D4+ OUT_D4+ 14 HDMI_CLK- 11 TMDS Clock+ DP_LANE3- [P133] IN_D4- OUT_D4- HDMI_CLK-_X 12 TMDS Clock Shield V5OUT 13 TMDS Clock- 14 CEC 2 2 HDMI_SCL_X 15 Reserved R9 R10 HDMI_SDA_X 16 SCL 10k 10k 17 SDA HDMI_5VPWR 18 DDC/CEC Ground 9 28 HDMI_SCL 1 1 HDMI_HPD_X 19 +5V Power HDMI_CTRL_CLK [P152] SCL_SOURCE SCL_SINK Hot Plug Detect 8 29 HDMI_SDA 20 HDMI_CTRL_DAT [P150] SDA_SOURCE SDA_SINK 21 CASE_20 34 V5OUT 22 CASE_21 V5OUT 23 CASE_22 36 CASE_23 CP HDMI Type A 1 GND SHLD C9 22uF 6.3V

2 Only one of these connectors shall be 35 CN connected at the same time! 7 30 HDMI_HPD HPD_SOURCE HPD_SINK U_NXP_PTN3380B GND GND VCC3V3 3 3 D4 D1 2 DVI 6V 6V R11 10k X2 HDMI_D2- 4 3 HDMI_D2-_X 1 2 1 2 1 1 L1 2 TMDS_D2- HDMI_HPD# [P153] HDMI_D2+ 1 2 HDMI_D2+_X 3 TMDS_D2+ 3 4 2/4 Shield 5 TMSD_D4- T1 HDMI_SCL 2 1 HDMI_SCL_X 6 TMDS_D4+ BSS138 1 DP_HPD HDMI_SDA Z32 1 HDMI_SDA_X 7 DDC_CLK Z2 8 DDC_DATA 1 HDMI_D1- 4 3 HDMI_D1-_X 9 Analog_VSYNC 2 R12 L2 10 TMDS_D1- 100k HDMI_D1+ 1 2 HDMI_D1+_X 11 TMDS_D1+ 12 1/3 Shield 2 13 TMDS_D3- GND GND V5OUT 2 1 HDMI_5VPWR 14 TMDS_D3+ Z1 15 +5V HDMI_HPD 2 1 HDMI_HPD_X 16 GND HDMI_D0- Z44 3 HDMI_D0-_X 17 Hot plug detect L3 18 TMDS_D0- HDMI_D0+ 1 2 HDMI_D0+_X 19 TMDS_D0+ 20 0/5 Shield 21 TMDS_D5- 22 TMDS_D5+ HDMI_CLK+ 4 3 HDMI_CLK+_X 23 CLK Shield 25 L4 24 TMDS_CLK+ SHIELD_1 26 HDMI_CLK- 1 2 HDMI_CLK-_X TMDS_CLK- SHIELD_2

DVI Series GND SHLD

D2 D3 HDMI_D2-_X 1 1+ NC 10 HDMI_D2-_X HDMI_D0-_X 1 1+ NC 10 HDMI_D0-_X HDMI_D2+_X 2 1- NC 9 HDMI_D2+_X HDMI_D0+_X 2 1- NC 9 HDMI_D0+_X

GND 3 GND GND 8 GND GND 3 GND GND 8 GND HDMI_D1-_X 4 2+ NC 7 HDMI_D1-_X HDMI_CLK+_X 4 2+ NC 7 HDMI_CLK+_X HDMI_D1+_X 5 2- NC 6 HDMI_D1+_X HDMI_CLK-_X 5 2- NC 6 HDMI_CLK-_X

ESD7104MUTAG ESD7104MUTAG

Note

1. Only one of the connectors shown shall be connected at the same time!

2. DP++ capabilities are required on the module

3. In this example the carrier board supports HDMI and DVI only

Qseven Design Guide Page 82 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.12.2.1 DP++ Transmitter Reference Circuitry The following circuitry shows an example for a DP/DP++ transmitter circuitry with a direct DisplayPort output. In this implementation the carrier board supports common DP Displays directly, HDMI and DVI via an external cable adapter connected to the DP++ connector. The external cable adapter corresponds to the level shifter in the schematics of Figure 3-33.

Figure 3-34 DP++ to DP Transmitter Reference Circuitry

X1 DP_LANE0+ [P149] 4 3 DP_D0+ 1 21 L1 2 Lane0+ SHLD_21 22 GND GND_2 SHLD_22 DP_LANE0- [P151] 1 2 DP_D0- 3 23 4 3 DP_D1+ 4 Lane0- SHLD_23 24 DP_LANE1+ [P137] Lane1+ SHLD_24 L2 GND 5 1 2 DP_D1- 6 GND_5 DP_LANE1- [P139] Lane1- 4 3 DP_D2+ 7 SHIELD DP_LANE2+ [P143] Lane2+ L3 GND 8 1 2 DP_D2- 9 GND_8 DP_LANE2- [P145] Lane2- DP_LANE3+ [P131] 4 3 DP_D3+ 10 L4 11 Lane3+ GND GND_11 DP_LANE3- [P133] 1 2 DP_D3- 12 2 1 CAD_X 13 Lane3- Z1 14 CFG1 2 1 DP_AUX+ 15 CFG2 AUX+ Z2 GND 16 2 1 DP_AUX- 17 GND_16 Z32 1 DP_HPD_X 18 AUX- HPD Z4 GND 19 VCC3V3 VCC3V3_DP 20 GND_PWR U1 PWR 14 DisplayPort Connector VCC

2 VCC3V3 VCC3V3 C1 100nF 15 1 2 1 C A 1 2 1 7 PAD R1 GND 100k Z5 2 1 D4 F1 C3 C4 500mA 2 GND 2 3 2 1 SDA_AUX- 100nF 22uF 16V DP_AUX- [P140] 1 1A 1B C2 100nF OE1# 1 2 GND GND 5 6 2 1 SCL_AUX+ DP_AUX+ [P138] 4 2A 2B C5 100nF OE2# 1 D1 1 10 R2 DP_D0+ 1+ NC DP_D0+ 2 9 9 8 DP_D0- 1- NC DP_D0- HDMI_CTRL_DAT [P150] 100k 10 3A 3B OE3# 2 GND 3 GND GND 8 GND GND DP_D1+ 4 2+ NC 7 DP_D1+ HDMI_CTRL_CLK [P152] 12 11 13 4A 4B DP_D1- 5 2- NC 6 DP_D1- OE4# U_TI_74_3125 ESD7104MUTAG

D2 DP_D2+ 1 1+ NC 10 DP_D2+ DP_D2- 2 1- NC 9 DP_D2-

GND 3 GND GND 8 GND U2A DP_D3+ 4 2+ NC 7 DP_D3+ 4 74LVC00 1 DP_D3- 5 2- NC 6 DP_D3- 1 CAD 3 ESD7104MUTAG HDMI_HPD# [P153] 2 DP_HPD VCC3V3 U2B D3 4 2 1

7 74LVC00 1 CAD_X 1 1+ NC 10 CAD_X 4

1 1 U2D 1 DP_HPD_X 2 1- NC 9 DP_HPD_X U2C 4 C6 74LVC00

4 74LVC00 6 R3 R4 GND 100nF 10 1 3 GND GND 8 5 100k 100k 8 GND GND 13 9 11 2 2 DP_AUX- 4 2+ NC 7 DP_AUX- DP_HPD# [P154] 7 DP_AUX+ 5 6 DP_AUX+ 12 GND GND 2- NC 7 ESD7104MUTAG GND GND 7

Note

DP++ capabilities are required on the module.

The Qseven V2.0 reference carrier board is implemented differently. It uses an external graphics adapter and does not include an onboard level shifter for external graphics output. For details please see the Qseven V2.0 reference carrier board manual.

Figure 3-35 Pictures of a DP++ to DVI Level shifter

Qseven Design Guide Page 83 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.13 HDMI Interface Signals (from Module) High-Definition Multimedia Interface (HDMI) is a licenseable compact audio/video connector interface for transmitting uncompressed digital streams. HDMI encodes the video data into TMDS for digital transmission and is fully backward-compatible with the single-link Digital Visual Interface (DVI) carrying digital video. Additionally, HDMI adds the ability to send up to 8 separate channels of uncompressed digital audio and auxiliary control data during the horizontal and vertical blanking intervals of the TMDS video stream.

The Qseven® specification defines a single-link HDMI interface with a pixel clock rate of up to 165 MHz. The appropriate TMDS receive and transmit differential signal pair, as well as additional control signals, can be found on the Qseven® module edge connector. This interface is shared with the DisplayPort signals.

Table 3-28 Signal Definition HDMI

Signal Shared With Pin# Description I/O Type IOL/IIL Module I/O (Signal) TMDS_CLK- DP_LANE3- 133 TMDS differential pair clock lines. TMDS O TMDS_CLK+ DP_LANE3+ 131 TMDS_LANE0- DP_LANE2- 145 TMDS differential pair lines lane 0. TMDS O TMDS_LANE0+ DP_LANE2+ 143 TMDS_LANE1- DP_LANE1- 139 TMDS differential pair lines lane 1. TMDS O TMDS_LANE1+ DP_LANE1+ 137 TMDS_LANE2- DP_LANE0- 151 TMDS differential pair lines lane 2. TMDS O TMDS_LANE2+ DP_LANE0+ 149 HDMI_CTRL_CLK 152 DDC based control signal (clock) CMOS 3.3V I/O for HDMI device. OD HDMI_CTRL_DAT 150 DDC based control signal (data) CMOS 3.3V I/O for HDMI device. OD HDMI_HPD# 153 Hot plug detection signal that CMOS 3.3V I serves as an interrupt request. Note

Level Shifters and pull-ups to 5V for HDMI_CTRL_CLK and HDMI_CTRL_DAT shall be on the carrier board as shown in the schematics.

Support of the TMDS interface is chipset dependent and therefore may not be available on all Qseven® modules. TMDS interface signals are shared with the DisplayPort interface. The TMDS interface enables Qseven® modules to support DVI or HDMI.

3.13.1 HDMI Implementation The HDMI signals on Qseven® modules are provided by the internal graphics chipset. On modules with x86 processor based technology the integrated HDMI signals are usually multiplexed with the Display Port interface. High speed HDMI level shifters are required to translate the signals to the HDMI compliant open-drain current driven Rx terminated differential output. As the outputs are platform-dependent, these level shifters shall be on the Qseven module.

NXP PTN3380B (http://www.nxp.com) Parade Technologies PS101QFN48G (http://www.paradetech.com) Pericom Semiconductor PI3VDV411LSZDE (http://www.pericom.com) Chrontel CH7318 (http://www.chrontel.com).

Modules with ARM processor based technology usually feature native, unmultiplexed HDMI outputs.

3.13.1.1 HDMI Connector Signals

Figure 3-36 HDMI Connector

Table 3-29 Pinout HDMI Connector

Pin# Signal Description Pin# Signal Description 1 TMDS Data 2+ HDMI Lane 2 (positive) 2 TMDS Data 2 Shield of Data 2 pair Shield 3 TMDS Data 2- HDMI Lane 2 (negative) 4 TMDS Data 1+ HDMI Lane 1 (positive) 5 TMDS Data 1 Shield of Data 1 pair 6 TMDS Data 1- HDMI Lane 1 (negative) Shield 7 TMDS Data 0+ HDMI Lane 0 (positive) 8 TMDS Data0 Shield of Data 0 pair Shield 9 TMDS Data 0- HDMI Lane 0 (negative) 10 TMDS Clock- HDMI Clock (positive) 11 TMDS Clock Shield of Clock pair 12 TMDS Clock- HDMI Clock (negative) Shield 13 CEC Consumer Electronics Control 14 Reserved N.C. Interface 15 DDC Clock DDC based control signal (clock) 16 DDC Data DDC based control signal (data) 17 GND Ground 18 +5V +5V Power Supply 19 HPD Hot plug detect

Note

Native HDMI implementation is available with many ARM technology based modules.

Qseven Design Guide Page 85 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.13.2 Passive HDMI/DVI Transmitter Reference Circuitry The example shows a passive wiring to either connect a HDMI or a DVI connector on the carrier board with native HDMI output from a module. In this case only level shifters are required for the I2C interface.

Figure 3-37 Passive HDMI to DVI/HDMI Transmitter Reference Circuitry

HDMI License is necessary!

X1 HDMI_D2+_X 1 VCC3V3 VCC3V3 VCC5V 2 TMDS Data2+ HDMI_D2-_X 3 TMDS Data2 Shield HDMI_D1+_X 4 TMDS Data2- 5 TMDS Data1+ 2 2 HDMI_D1-_X 6 TMDS Data1 Shield 1 R3 R4 HDMI_D0+_X 7 TMDS Data1- 10k 10k 8 TMDS Data0+ HDMI_D0-_X 9 TMDS Data0 Shield 2 3 1 1 HDMI_SCL HDMI_CLK+_X 10 TMDS Data0- HDMI_CTRL_CLK [P152] 11 TMDS Clock+ HDMI_CLK-_X 12 TMDS Clock Shield 1 13 TMDS Clock- T1 14 CEC BSS138 HDMI_SCL_X 15 Reserved 2 3 HDMI_SDA 16 SCL HDMI_CTRL_DAT [P150] HDMI_SDA_X 17 SDA HDMI_5VPWR 18 DDC/CEC Ground HDMI_HPD_X 19 +5V Power T2 Hot Plug Detect BSS138 20 21 CASE_20 22 CASE_21 VCC5V 23 CASE_22 CASE_23 HDMI Type A 2 1 C A 1 2 GND SHLD

Z5 2 1 D3 F1 C1 C2 500mA 100nF 22uF 16V 1 2 GND GND Only one of these connectors shall be connected at the same time!

GND GND 3 3 D1 D2 6V 6V DVI X2 4 3 HDMI_D2-_X 1 2 1 2 1 TMDS_LANE2- [P151] L1 2 TMDS_D2- TMDS_D2+ TMDS_LANE2+ [P149] 1 2 HDMI_D2+_X 3 4 2/4 Shield 5 TMSD_D4- HDMI_SCL 2 1 HDMI_SCL_X 6 TMDS_D4+ HDMI_SDA Z12 1 HDMI_SDA_X 7 DDC_CLK Z2 8 DDC_DATA 4 3 HDMI_D1-_X 9 Analog_VSYNC TMDS_LANE1- [P139] L2 10 TMDS_D1- 1 2 HDMI_D1+_X 11 TMDS_D1+ TMDS_LANE1+ [P137] 12 1/3 Shield 13 TMDS_D3- 2 1 HDMI_5VPWR 14 TMDS_D3+ Z3 15 +5V HDMI_HPD 2 1 HDMI_HPD_X 16 GND Z44 3 HDMI_D0-_X 17 Hot plug detect TMDS_LANE0- [P145] L3 18 TMDS_D0- 1 2 HDMI_D0+_X 19 TMDS_D0+ TMDS_LANE0+ [P143] 20 0/5 Shield 21 TMDS_D5- 22 TMDS_D5+ 4 3 HDMI_CLK+_X 23 CLK Shield 25 TMDS_CLK+ [P131] L4 24 TMDS_CLK+ SHIELD_1 26 1 2 HDMI_CLK-_X TMDS_CLK- SHIELD_2 TMDS_CLK- [P133] DVI Series GND SHLD

D4 HDMI_D2-_X 1 1+ NC 10 HDMI_D2-_X HDMI_D2+_X 2 1- NC 9 HDMI_D2+_X

GND 3 GND GND 8 GND HDMI_D1-_X 4 2+ NC 7 HDMI_D1-_X HDMI_D1+_X 5 2- NC 6 HDMI_D1+_X VCC3V3 ESD7104MUTAG

2 D5 R13 HDMI_D0-_X 1 1+ NC 10 HDMI_D0-_X 10k HDMI_D0+_X 2 1- NC 9 HDMI_D0+_X

1 3 8 HDMI_HPD# [P153] GND GND GND GND

3 HDMI_CLK+_X 4 2+ NC 7 HDMI_CLK+_X HDMI_CLK-_X 5 2- NC 6 HDMI_CLK-_X T4 BSS138 1 ESD7104MUTAG 1

2 R14 100k 2

GND GND

Qseven Design Guide Page 86 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.14 LPC Interface Signals The Low Pin Count Interface was defined by Intel® Corporation to facilitate the industry's transition towards legacy free systems. It allows the integration of low-bandwidth legacy I/O components within the system, which are typically provided by a Super I/O controller. Furthermore, it can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embedded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer to the 'Intel® Low Pin Count Interface Specification Revision 1.1'.

Since Qseven® is designed to be a legacy free standard for embedded modules, it does not support legacy functionality such as PS/2 keyboard/mouse, serial and parallel ports. Instead it provides an LPC interface that can be used to add peripheral devices to the carrier board design. The reduced pin count of the LPC interface makes it easy to implement such devices. All corresponding signals can be found on the module connector.

Table 3-30 Signal Definition LPC

Signal Pin# Description I/O Type IOL/IIL I/O LPC_AD[0..3] 185 to 188 Multiplexed Command, Address and Data. CMOS 3.3V I/O LPC_FRAME# 190 LPC frame indicates the start of a new cycle or the CMOS 3.3V O termination of a broken cycle. LPC_LDRQ# 192 LPC DMA request. CMOS 3.3V I LPC_CLK 189 LPC clock. CMOS 3.3V O SERIRQ 191 Serialized Interrupt. CMOS 3.3V I/O

Note

1) While LPC interface is useful in x86 systems for backward compatibility it is not relevant at all for ARM systems.

2) Implementing external LPC devices on the Qseven® carrier board always requires customization of the Qseven® module's BIOS in order to support basic initialization for the LPC device. Otherwise the functionality of LPC device will not be supported by a Plug&Play or ACPI capable system.

3) All Examples in this chapter except the ones shown in Figure 3-38 (LPC Clock Buffer Reference Circuitry), Figure 3-41 and Figure 3-42 (LPC Super I/O SMSC SCH3114 Reference Circuitry) and Figure 3-48 (LPC Firmware Hub Reference Circuitry) have been taken from the current Qseven V2.0 reference carrier board.

3.14.1 LPC Bus Clock Signal Qseven® specifies a single LPC reference clock signal called 'LPC_CLK' on the modules connector on pin 189. If more than one LPC clock signal is required on the carrier board to supply several LPC devices, a zero delay buffer must be used to expand the number of LPC clock lines. Figure 3-38 shows an example of how to implement a Integrated Device Technology IDT2305 zero delay clock buffer (http://www.idt.com).

Note 1. Qseven® modules based on the Intel® Atom™ Processor and Intel® System Controller Hub US15W can not be booted from external BIOS Firmware Hubs (FWH) that are clocked by a buffered or delayed clock signal.

2. This is just an example. The Qseven 2.0 reference carrier board does not include an LPC Clock Buffer.

3.14.1.1 Routing Considerations for LPC Clock The LPC clock implementation should follow the routing guidelines for the PCI clock defined in the 'PCI Local Bus Specification Revision 2.3'.

3.14.2 LPC Reset Signal The LPC interface should use a reset signal that is generated by splitting the PCI Express reset (PCIE_RST#, pin 158 of the Qseven® connector) signal with a zero delay buffer. An example can be found in Figure 3-6 of this document. This solution is also used on the SGeT e.V. V2.0 evaluation carrier board. Here the LPC reset signal is called 'PLT_RESET#'. If the carrier board implements more than one LPC device, it is recommended that the LPC reset signal be split so that each LPC device will be provided with a separate reset signal.

3.14.3 LPC Super I/O Support The Qseven® BIOS firmware includes integrated support for the following external LPC Super I/O controllers in order to provide additional legacy COM ports:

• Nuvoton W83627DHG LPC Super I/O with 2 COM ports (http://www.nuvoton.com) • SMSC SCH3114 LPC Super I/O with 4 COM ports (http://www.smsc.com) • EXAR X28V384 LPC Super I/O with 4 COM ports http://www.exar.com

If any of the additional functionality of the Super I/O is required by the application, then it may be implemented via the application's software program. There are Super I/O functions that can be configured by hardware straps, which is defined within the datasheet of that particular Super I/O (for example PS/2 keyboard functionality).

Qseven Design Guide Page 88 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. The base address for these Super I/O controllers shall be 0x2E to be sure that the legacy COM port devices of the Super I/O controller can be initialized by the BIOS.

3.14.3.1 LPC Super I/O with Nuvoton W83627DHG

Figure 3-39 LPC Super I/O Nuvoton W83627DHG Reference Circuitry

+3.3V_S L106 FB-BLM18KG471SN1 C82 C83 C84 C85 C86

CC-100n CC-100n CC-100n CC-100n CC-100n

SIO_VTT 7 2 8 4 0 8 1 5 U10 1 2 4 6 9 7 1 1 3 2 T T B C _ _ _ T A S C C C C V B V V C C C 3 V A V V V UART0_RI#

27 3 3 3 57 LPC_AD0[3,6,13,15] 26 LAD0 RIA/GP60 56 UART0_DCD# LPC_AD1[3,6,13,15] 25 LAD1 DCDA/GP61 54 UART0_TXD LPC_AD2[3,6,13,15] 24 LAD2 L SOUTA/GP62/PENKBC 53 UART0_RXD

LPC_AD3[3,6,13,15] T 29 LAD3 P SINA/GP63 52 UART0_DTR# LPC_FRAME#[3,6,13,15] LFRAME DTRA/GP64/PENROM 22 C R 51 UART0_RTS# LPC_LDRQ#[3,6] LDRQ RTSA/GP65/HEFRAS

SIO_RST#_JP UART0_DSR#

30 O 50

LRESET I DSRA/GP66

23 / 49 UART0_CTS# P F

SERIRQ[3,6,15] SIO_PME# 86 SERIRQ CTSA/GP67 85 UART1_RI#

PME L RIB/GP40 84 UART1_DCD# DCDB/GP41 21 A 83 UART1_TXD LPC_CLK_SIO[3] I CLK48M_SIO 18 PCICLK SOUTB/IRTX/GP42/FAN_SET2 82 UART1_RXD IOCLK R SINB/IRRX/GP43 81 UART1_DTR# E DTRB/GP44 80 UART1_RTS#

S RTSB/GP45 79 UART1_DSR# +12V_S DSRB/GP46 78 UART1_CTS# CTSB/GP47 SIO_BEEP 118 R71 BEEP/SO SIO_CASEOPEN# 76 W83627DHG 42 LPT_PD0 CASEOPEN PD0 41 LPT_PD1 SIO_VIN0 99 PD1 40 LPT_PD2 R-56K SIO_VIN1 98 VIN0 QFP 128 PD2 39 LPT_PD3 SIO_VIN2 VIN1 PD3 LPT_PD4 SIO_VIN0 97 38 VIN2 PD4 LPT_PD5 +1.5V_S 96 37 R72 100 VIN3 PD5 36 LPT_PD6 CPUVCORE L PD6 H 35 LPT_PD7 E PD7

SIO_VREF 101 A 102 VREF L 31 LPT_SLCT R R-10K SIO_CPUTIN 103 AUXTIN L SLCT 32 LPT_PE D T SIO_AVSS SIO_SYSTIN 104 CPUTIN A PE 33 LPT_BUSY W SYSTIN R BUSY 5 R 34 LPT_ACK# SMI/OVT ACK

A O 45 LPT_ERR# +5V_S SIO_VID0 A ERR LPT_SLIN# 128 P P 43 SIO_VID1 127 VID0 R SLIN 44 LPT_INIT#

R73 E SIO_VID2 126 VID1 INIT 46 LPT_AFD#

SIO_VID3 VID2 AFD LPT_STB# 125 M 47 SIO_VID4 124 VID3 STB SIO_VID5 123 VID4 O R-30K SIO_VID6 122 VID5 N 1 SIO_VIN1 VID6 DRVDEN0 SIO_VID7 121 I 3 FDC_INDEX# R74 T VID7 INDEX 4 SIO_AUXFANIN0 111 O MOA 6

SIO_AUXFANIN1 58 AUXFANIN0 R DSA 8 AUXFANIN1/SI DIR

7 F 9 I R-10K AUXFANOUT / STEP / I 10 SIO_AVSS F WD SIO_CPUFANIN 112 11 CPUFANIN0 WE

SIO_CPUFANIN1 119 C 13 FDC_TRAK0# CPUFANIN1/GP21 TRAK0 14 FDC_WP# +5V_A D SIO_SYSFANIN 113 WP 15 FDC_RDATA# F 116 SYSFANIN RDATA 16 R75 SYSFANOUT HEAD 17 FDC_DSKCHG# 115 DSKCHG 120 CPUFANOUT0 CPUFANOUT1/GP20 R-30K SIO_VIN2 117 59 FAN_SET/PLED GA20M 60 R79 KBRST 62 KBD_CLK KCLK/GP27 KBD_DAT C 63 SIO_GP22 19 KDAT/GP26 65 MS_CLK SIO_GP23 2 GP22/SCE B MCLK/GP25 66 MS_DAT

R-10K K SIO_GP30 92 GP23/SCK MDAT/GP24 SIO_AVSS G SIO_GP31 91 GP30/PWROK2 SIO_GP35 87 GP31/VSBGATE P

GP35/ATXPGD

SIO_GP36 69 I 68

SIO_VREF GP36/FTPRST / PSIN/GP56 SIO_GP37 64 O 67 R84 SIO_GP50 77 GP37/SUSC PSOUT/GP57 75 SIO_EN_ACPI 70 GP50/WDTO/EN_GTL RSMRST/GP51 73 SIO_SUSB# GP55/SUSLED/EN_ACPI SUSB/GP52 72 I PSON/GP53 71 R-10K SIO_PECI P PWROK/GP54 SIO_SYSTIN 108 94 SIO_PECISB 106 PECI C RSTOUT0 93 PECISB RSTOUT1 A 90 R90 SIO_SST 114 RSTOUT2/GP32/SCL 89 SST RSTOUT3/GP33/SDA 88 T 109 RSTOUT4/GP34 R-ERTJ1VG103F 110 NC_1 SIO_AVSS NC_2 1 2 D _ SIO_VREF _ N S S

R98 S S G V V A W83627DHG 5 5 0 2 5 0

1 SIO_AVSS L107 FB-BLM18KG471SN1 R-15K +V3.3_CLK48 R377 R-10K SIO_CPUTIN +3.3V_S OSC1

3 L25 FB-742792651 4 3 CLK48M_SIO_R R99 R-33 CLK48M_SIO Q3 C102 C101 2 VCC OUT 1 2 GND OE CC-2n2 CC-100n 48MV3SB MMBT3904 1 SIO_AVSS

SIO_VID0 R442 R-4K7 SIO_CPUFANIN R411 R-4K7 LPT_PD3 R412 R-4K7 SIO_VID1 R444 R-4K7 SIO_SYSFANIN R413 R-4K7 LPT_PD2 R414 R-4K7 SIO_VID2 R445 R-4K7 SIO_AUXFANIN0 R415 R-4K7 LPT_PD1 R416 R-4K7 SIO_VID3 R446 R-4K7 SIO_AUXFANIN1 R417 R-4K7 LPT_PD0 R418 R-4K7 SIO_VID4 R448 R-4K7 SIO_CPUFANIN1 R419 R-4K7 LPT_PD7 R420 R-4K7 SIO_VID5 R450 R-4K7 SIO_GP22 R421 R-4K7 LPT_PD6 R422 R-4K7 SIO_VID6 R452 R-4K7 SIO_GP23 R423 R-4K7 LPT_PD5 R424 R-4K7 SIO_VID7 R454 R-4K7 SIO_SUSB# R425 R-4K7 LPT_PD4 R426 R-4K7 SIO_GP35 R427 R-4K7 LPT_SLCT R428 R-4K7 SIO_PECISB R456 R-4K7 SIO_GP31 R429 R-4K7 LPT_PE R430 R-4K7 SIO_PECI R457 R-4K7 SIO_GP30 R431 R-4K7 LPT_BUSY R432 R-4K7 SIO_VTT R458 R-4K7 SIO_GP37 R433 R-4K7 LPT_ACK# R434 R-4K7 SIO_SST R459 R-4K7 SIO_GP36 R435 R-4K7 LPT_SLIN# R436 R-4K7 SIO_CASEOPEN# R437 R-4K7 LPT_INIT# R438 R-4K7 SIO_PME# R532 R-4K7/X SIO_GP50 R439 R-4K7 LPT_ERR# R440 R-4K7 SIO_BEEP R533 R-4K7/X LPT_AFD# R441 R-4K7 LPT_STB# R443 R-4K7 FDC_INDEX# R447 R-4K7 FDC_TRAK0# R449 R-4K7 FDC_WP# R451 R-4K7 FDC_RDATA# R453 R-4K7 FDC_DSKCHG# R455 R-4K7

3.14.3.2 Boot Up Configuration for Nuvoton W83627DHG The default configuration of the Nuvoton W83627DHG LPC Super I/O controller during power-on can be implemented by hardware strap options. The hardware strap pins are located on the serial port interface of the Super I/O controller. They can be enabled by placing a 10kΩ pull-up resistor between +3.3V supply voltage and one of the dedicated hardware strap pins. Figure 3-40 shows the boot strap configuration options for the Nuvoton W83627DHG LPC Super I/O controller.

Figure 3-40 Nuvoton W83627DHG Boot Strap Configuration

SW2 SIO_RST#_JP LPC_RST#[4] UART0_RTS# UART0_RTS#_PU LPC_RST_XR28V384[4] LPC_RST_EXAR [15] PS_CONF_2E[15] HRM-04-T R85 R487 R534 SW1: ON - W83627 enabled OFF - W83627 disabled SW2: ON - W83627 Config. Address 4Eh OFF - W83627 Config. Address 2Eh R-4K7 R-4K7 R-4K7 SW3: ON - XR28V384 enabled OFF - XR28V384 disabled SW4: ON - XR28V384 Config. Address 4Eh OFF - XR28V384 Config. Address 2Eh

+3.3V_S

R535 R-1K UART0_TXD R91 R-1K/X UART0_RTS#_PU R93 R-1K KBC enable R94 R-1K UART1_TXD Config. Address 4Eh R95 R-1K UART0_DTR# FAN_SET2 strap R97 R-1K SIO_EN_ACPI SPI disabled ACPI disabled

Qseven Design Guide Page 90 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.14.3.3 LPC Super I/O with SMSC SCH3114 Note This is just an example. The Qseven 2.0 reference carrier board does not use an SMSC SCH3114 in its LPC Super I/O circuitry.

Figure 3-41 LPC Super I/O SMSC SCH3114 Reference Circuitry

3.14.3.4 LPC Boot Up Configuration for SMSC SCH3114 The default configuration of the SMSC SCH3114 LPC Super I/O controller during power-on can be implemented by hardware strap options. The hardware strap pins are located on the serial port interface of the Super I/O controller. They can be enabled by placing a 4.7kΩ pull-up resistor between +3.3V supply voltage and one of the dedicated hardware strap pins. Figure 3-42 shows the boot strap configuration options for the SMSC SCH3114 LPC Super I/O controller.

Figure 3-42 SMSC SCH3114 Boot Strap Configuration

SYSOPT1 SYSOPT2 Address 1 0 0x2Eh 1 1 0x4Eh 0 0 0x162Eh 0 1 0x164Eh

Figure 3-43 LPC Super I/O EXAR X28V34 Reference Circuit

PS_CONF_2E [14] +3.3V_S R378 R-10K L50 FB-742792651 # # # # # RI2# R R R R R R R

OSC2 # X X X X X X X CD2# R ______C215 4 3 CLK24M_XR_R R188 R-33 CLK24M_XR _ X D D R R S S VCC OUT D RI3# _ X T T 2 1 I C T S X CD3# T R D C GND OE R D R D

CC-100n ______+3.3V_S 1 1 1 1

1 1 1 1 DSR3#

ASE-24.000MHZ-LC-T R193 R-2K2 T T T T T T T T R536 R-0 DSR2# R R R R R R R R A A A A A A A A U U U U U U U U 8 7 4 3 0 9 6 5 2 1 U16 4 4 4 4 4 4 4 4 4 3 1 # # # # # # A A E 1 1 1 1 1 1 X 2 I Q Q X X _ S D R R R R R T F T I I R S C _ _ R N C R D I I 8 0 O F E C 3 3 38 RI2# _ _ _ RI2# S S S P P P / / +3.3V_S 1 / 37 CD2# # 1 LPC_RST_EXAR[14] PCIRST# # CD2# 1 1

R194 R-10K 2 X S T WDTOUT# R

T 36 TX2 T 2 TX2/PS_2F8_IRQB R D

H 35 RX2

RX2 C 4 CH1 UART 34 LPC_AD3[3,6,13,14] LAD3 DTR2#/PS_2E0_IRQB 5 T 32 DSR2#

LPC_AD2[3,6,13,14] LAD2 R DSR2#

6 A 33 RTS2# LPC_AD1[3,6,13,14] LAD1 RTS2#/PS_CONF_KEY1 L U 7 31 CTS2# LPC_AD0[3,6,13,14] LAD0 P CTS2#

8 C LPC_CLK_XR[3] LCLK 9 LPC_FRAME#[3,6,13,14] LFRAME# EXAR 10 SERIRQ[3,6,14] SERIRQ 28 RI3# X28V384 RI3# 27 CD3# CD3# 3 26 TX3 CLK24M_XR 12 H TX3/PS_3E8_IRQC CLKIN C 25 RX3 RX3

24 T DTR3#/PS_WDT

R 22 DSR3# DSR3# A 21 +3.3V_S UART CH4 U CTS3# 11 CTS3# 30 VCC 23 RTS3# VCC D RTS3#/PS_CONF_KEY0 C218 C219 C220 Q R I _

CC-100n CC-100n CC-100n 3 8

GND E

29 2

GND _ S # # # # 4 P 4 4 4 # / # 4 4 R S R S 4 4 T T X S T D I X C D R D R T C R XR28V384 5 6 9 0 3 4 7 8 1 1 1 1 1 1 1 2 # # # # # R R R R R R R # X X X X X X X _ R ______D X D R S S R D _ X T T I T S C X R R D R C D T D ______4 4 4 4 4 4 4 4 T T T T T T T T R R R R R R R R A A A A A A A A U U U U U U U U

3.14.3.6 LPC Boot Up Configuration for EXAR X28V384 The default configuration of the EXAR X28V384 LPC Super I/O controller during power- on can be implemented by hardware strap options. The hardware strap pins are located on the serial port interface of the Super I/O controller. They can be enabled by placing a 4.7kΩ pull-up resistor between +3.3V supply voltage and one of the dedicated hardware strap pins. Figure 3-43 shows the boot strap configuration options for the EXAR X28V384 LPC Super I/O controller.

Figure 3-44 EXAR X28V384 Boot Strap Configuration

+3.3V_S

R535 R-1K UART0_TXD R91 R-1K/X UART0_RTS#_PU R93 R-1K KBC enable R94 R-1K UART1_TXD Config. Address 4Eh R95 R-1K UART0_DTR# FAN_SET2 strap R97 R-1K SIO_EN_ACPI SPI disabled ACPI disabled

U9 ADM3310EARUZ 6 1 C91 C1+ V+ C88 +3.3V_S CC-100n 24 3 CC-100n 2 C1- VCC C87 C90 C2+ 27 CC-100n CC-100n 4 GND C89 28 C2- C93 C3+ 25 CC-100n V- 5 CN12A CC-100n 26 EN 23 19 C3- SHDN UART0_DTR# 7 22 COM0_a_DTR# COM0_a_DCD# 1 UART0_TXD 8 T1IN T1OUT 21 COM0_a_TXD COM0_a_DSR# 6 UART0_RTS# 9 T2IN T2OUT 20 COM0_a_RTS# COM0_a_RXD 2 UART0_RI# 10 T3IN T3OUT 19 COM0_a_RI# COM0_a_RTS# 7 UART0_CTS# 11 R1OUT R1IN 18 COM0_a_CTS# COM0_a_TXD 3 UART0_RXD 12 R2OUT R2IN 17 COM0_a_RXD COM0_a_CTS# 8 UART0_DSR# 13 R3OUT R3IN 16 COM0_a_DSR# COM0_a_DTR# 4 UART0_DCD# 14 R4OUT R4IN 15 COM0_a_DCD# COM0_a_RI# 9 R5OUT R5IN 5

5511-09M/M02RCZ

Shield Plane 3.14.3.8 LPC configurable RS232 Serial Port Reference Circuitry Figure 3-46 COM Port Reference Circuit (RS-232/485/422)

+3.3V_S +3.3V_S U57 U58 RTS2# 1 5 5 1 UART2_RTS#_DE UART2_485/232# 2 A VCC VCC A 2 UART2_HALF/FULL# 3 B 4 UART2_RTS#_DE UART2_RE# 4 B 3 GND (A^B) (A&B) GND NC7SZ86 C316 C323 NC7S08M5X SW12 CC-100n CC-100n UART2_485/232# UART2_HALF/FULL# UART3_485/232# UART3_HALF/FULL# +5V_S U56 29 31 HRM-04-T C298 C1+ VCC C216

CC-100n 32 2 CC-1u/10V C1- GND 27 C299 C2+ 28 C312 CC-100n V+ CN29A CC-100n 26 +3.3V_S 19 C2- 25 C303 CC-100n V- +3.3V_S 30 1 VL C300 12 R200 R-10K 6 FD_TX_TERM 13 R199 R-10K RXD_HF2 2 TERM CC-100n 17 RTS#_HF2 7 GND 20 UART2_RE# TXD_HF2 3 RE CTS#_HF2 8 TX2 22 3 TXD_HF2 4 T1IN,DI T1OUT,B/Z UART2_RTS#_DE 21 4 RTS#_HF2 9 T2IN,DE T2OUT,A/Y 5 CTS2# 6 19 CTS#_HF2 R1OUT R1IN,B RX2 7 18 RXD_HF2 20 +3.3V_S R2OUT,RO R2IN,A +3.3V_S 5511-09M/M02RCZ R195 R-10K UART2_485/232# 14 11 R198 R-10K Shield Plane RS-485/RS-232 SLEW

UART2_HALF/FULL# D R196 R-10K 15 A 10 R197 R-10K

HALF/FULL P SHDN SP335E 3 3

3.14.3.9 LPC PS2 Keyboard Port Reference Circuitry Figure 3-47 PS2 Keyboard Port Reference Circuit

+5V_S CN13 KBD_DAT 1

2 F7 MS_DAT 3

4 C98 +V5_KBD 5 nanoSMDC075F CC-100n KBD_CLK 6

MS_CLK 7

CON444/1/7_L

+5V_S R460 R-4K7 KBD_CLK R461 R-4K7 KBD_DAT R462 R-4K7 MS_DAT R463 R-4K7 MS_CLK

Qseven Design Guide Page 93 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.14.4 LPC Firmware Hub The LPC bus interface on Qseven® modules offers the possibility to boot the module using BIOS code programmed into an external firmware hub (FWH). The external FWH can be implemented on the carrier board. A hardware jumper must be provided on the carrier board to disable the module's onboard FWH and to enable the external FWH. The corresponding signal 'BIOS_DISABLE#' can be found on pin 41 of the Qseven® connector. Figure 3-48 shows a reference circuitry for an external 32-pin PLCC FWH socket.

Figure 3-48 LPC Firmware Hub Reference Circuitry

+V3.3 +V3.3 R215 R1%4k7S03 FWH_WP#

R217 R1%4k7S03 C219 C220 C221 FWH_TBL# C10uS05V16X C100nS03V50X C100nS03V50X

R219 R1%4k7S03 FWH_IC

R220 R1%4k7S03 FWH_GPI4

RN12 RN4K7VF 1 2 FWH_GPI0 +V3.3 3 4 FWH_GPI1 5 6 FWH_GPI2 7 8 FWH_GPI3 FWH_RST# LPC_CLK_FWH FWH_GPI3 FWH_GPI4 FWH_GPI2 +V3.3

2 1 0 +V3.3 +V3.3 R214 CN30 4 3 2 1 3 3 3 R1%330RS03 C292 +V3.3 R216 C100nS03V50X R1%4k7S03 LED_FWH FW H_GPI1 5 29 FWH_IC NA FW H_GPI0 6 28 U34 Y D23 FWH_WP# 7 27 1 VCC 5 DLED0603YEL FWH_TBL# 8 26 2 9 25 3 4 BOOT_ALT#_BF 10 24 FWH_RST# GND 11 23 LPC_FRAME# UNC7SZ125 12 22 LPC_AD0 13 21

CN31 BOOT_ALT# 1 CN31(2-3) 2 3 4 5 6 7 8 9 0 SPLCC32 1 1 1 1 1 1 2 XST1x3S MJMPR254 LPC_AD1 LPC_AD2 LPC_AD3

Note

For many new chipsets the Firmware Hub is no longer supported.

This is just an example. There is no firmware hub implemented on the Qseven V2.0 reference carrier board.

Qseven Design Guide Page 94 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.15 CAN Bus Interface Signals Controller Area Network (CAN or CAN-bus) is a message based protocol designed specifically for automotive applications but now is also used in other areas such as industrial automation and medical equipment.

Starting with Qseven® Specification revision 1.20, Qseven® modules can optionally support one CAN bus.

Table 3-31 Signal Definition CAN Bus

Signal Pin# Description I/O Type IOL/IIL I/O CAN0_TX 129 CAN (Controller Area Network) TX output for CAN Bus CMOS 3.3V O channel 0. In order to connect a CAN controller device to the Qseven® module's CAN bus it is necessary to add transceiver hardware to the carrier board. CAN0_RX 130 CAN0_RX RX input for CAN Bus channel 0. CMOS 3.3V I In order to connect a CAN controller device to the Qseven® module's CAN bus it is necessary to add transceiver hardware to the carrier board.

Note

If the CAN Bus interface is not used, and/or the Qseven® module's chipset does not support CAN Bus, then these pins shall be left unconnected.

Termination of all signals (e.g. required pullup/pulldown resistors) will be always on the module unless explicitly otherwise noted.

Figure 3-49 CAN Bus Reference Circuitry

CN25 CAN_RX R163 R-0/X 2 1 CAN_VDD

CAN_TX R165 R-0/X 4 3 +3.3V_S 6 5 C208 C209 8 7 CC-10u/6.3V CC-100n 10 9 R398 CON444/2/10_L

+12V_S JP10 1 P13 R-0 SHORTING_PLUG C204 2 SIZE = 0603 +5V_S CC-100n 3 C206 U47 +5V_S JP-3X1 R164 R-0 1 3 CAN_TX[3] CC-100n TXD VCC C368 CN26A R166 R-0 4 19 CAN_RX[3] RXD CC-100n +3.3V_S 1 5 7 CAN_H 6 C369 VIO BUS_H R167 R-120 2

1 2 7 CC-100n 2 3 GND JP11 JP-2X1 8 8 6 CAN_L 4 S BUS_L CAN_VDD 9 TJA1051T/3 L47 FB-BLM18KG471SN1 5

20 SH_CN26[22] P14 5511-09M/M02RCZ SHORTING_PLUG

Qseven Design Guide Page 95 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.16 SPI Interface Signals The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially lower-cost alternative for system devices such as EEPROM and flash components.

Starting with Qseven® Specification revision 1.20, Qseven® modules can optionally support one SPI interface. Check module vendor's user guide whether general purpose SPI can be used.

Figure 3-50 SPI Interface Connector Reference Circuitry

+3.3V_S C65 CC-100n C66 CC-100n CN7 2 1

4 3 SPI_MOSI[3] SPI_CS0# [3] R381 R-33 6 5 SPI_MISO[3] SPI_CS1# [3] 8 7 1-Wire_Bus SPI_SCK[3] 10 9

CON444/2/10_L

Table 3-32 Signal Definition SPI Interface

Signal Pin# Description I/O Type IOL/IIL I/O SPI_MOSI 199 Master serial output/Slave serial input signal. SPI serial CMOS 3.3V O output data from Qseven® module to the SPI device. SPI_MISO 201 Master serial input/Slave serial output signal. SPI serial CMOS 3.3V I input data from the SPI device to Qseven® module. SPI_SCK 203 SPI clock output. CMOS 3.3V O SPI_CS0# 200 SPI chip select 0 output. CMOS 3.3V O SPI_CS1# 202 SPI Chip Select 1 signal is used as the second chip CMOS 3.3V O select when two devices are used. Do not use when only one SPI device is used.

Figure 3-51 Shows a reference circuitry for an external SPI flash.

Figure 3-51 SPI Flash Reference Circuitry

JP5 1 1-Wire_Bus +3.3V_S +3.3V_S 2 GP_1-Wire_Bus [3] R65 R66 3 HDMI_CEC [11] JP-3X1 CN6 R-4K7 +3.3V_S R-4K7 SPI_CS0# 1 8 C360 CC-100n

SPI_MISO R380 R-33 2 7 P5 SHORTING_PLUG 3 6 SPI_SCK

4 5 SPI_MOSI

ACA-SPI-004-K01

Qseven Design Guide Page 96 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.17 Input Power Qseven® modules are designed to be driven with a single +5V input power rail. Additionally, two optional power rails are specified by Qseven® to provide a +5V standby voltage (5V-Always) on the Qseven® module as well as a +3V Real Time Clock (RTC) supply voltage, which is provided by a battery cell located on the carrier board.

If the carrier board does not require standby functionality, then the +5V standby power rail can be omitted. In this case the VCC_5V_SB pins shall be connected to the +5V input power rail. The same applies to the +3V RTC battery voltage rail. If no RTC/CMOS backup functionality is required by the system during power-off, then the +3V RTC supply battery voltage can be omitted. During standby and power-on the RTC/CMOS should be supplied by the 3.3V standby rail on the carrier board (see Figure 3-58). Please refer to the Qseven specification for the power up and power down power rail sequencing.

The following practices should be implemented in order to prevent possible damage to the customized carrier board and/or injury to the operator.

Over-current Protection

For safety reasons, the main power supply path should be fused. There should be a fuse placed between the system's power supply output and the customized carrier board's power supply input. This fuse may be a standard fuse or could also be a poly fuse. Either one is sufficient. The maximum current must be tested and determined by the carrier board designer.

This mechanism will protect the system from serious damage if too much current is drawn from the power supply.

Reverse Polarity Protection

There are two options to ensure that a system is not damaged by reverse polarity.

One way is to use a power supply connector that is mechanically keyed and prevents reverse insertion. Figure 3-52 Shows an example for a coded connector for reverse polarity protection

Figure 3-52 Coded Power Connector for Reverse Polarity Protection

CN30 +12V_A 1 3

2 4

39-28-1043

The second option is to use electronic components to guarantee reverse polarity protection. One way to do this is to use a Schottky diode or an active power switch. This should be placed in the main power supplying path of the carrier board to avoid current flow into the system when system power is connected with reversed polarity. The maximum current must be set and tested by the carrier board designer.

Figure 3-53 Shows an example for a reverse polarity protection circuitry

+12V_A CN40 1 8 Q191 FDMC4435BZ 2 7 2 3 6 3 5 A-DC-001-A-X D35

4 R327 R-100K R328

P6SMB16CA R-10K

For more information about the power input, ripple tolerances and input power sequencing refer to the Qseven® 2.0 Specification.

Table 3-33 Signal Definition Input Power

Signal Pin# Description I/O

VCC 211 to 230 Power Supply +5VDC ±5%. P

VCC_5V_SB 205, 206 Standby Power Supply +5VDC ±5%. P

VCC_RTC 193 3 V backup cell input. VCC_RTC should be connected to a 3V P backup cell for RTC operation and storage register non-volatility in the absence of system power. (VCC_RTC = 2.4 - 3.3 V).

GND 1, 2, 23, 24, 25, 26, 34, 39, 40, Power Ground. P 57, 58, 73, 74, 97, 98, 117, 118, 135, 136, 141, 142, 147, 148, 159, 160, 165, 166, 183, 184, 197, 198

Note If the standby 5V power rail 'VCC_5V_SB' is not provided by the carrier board, then the VCC_5V_SB pins (pins 205-206) of the Qseven® module must be connected with the main VCC power rail pins (pins 211-230).

Qseven Design Guide Page 98 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.17.1 Single Source Power Supply Figures show examples for voltage regulating/power supply circuitry as used in the Qseven 2.0 reference carrier board. Shown are instances for 12V carrier board voltage as implemented on the Qseven V2.0 reference carrier board.

Figure 3-54 Power Enable Circuit for 5V_Always +12V_A

C338 +12V_A CC-100n 8 U37 R352 C

7 C

SENSE V 2 5 R353 R-0 R-100K +12V_A_PG [20] RESIN RESET R354

6 RESET 3 1 R-56K CT D REF C339 N C340 G CC-100n TL7709ACD CC-100n 4

R355 C341

CC-100n 2 U38 S

R-1M V 3 C342 IN+ 1 CC-100n OUT R356 D N G LT6703CDC/X R-56K 4

Figure 3-55 Power Regulator Circuit for 5V_Always

U31 MPQ8632GLE-12 +12V_A 9 8 C366 C286 14 VIN BST VIN + R315 C287 CC-100n CE-220u/35V CC-100n R-1M 2 FREQ 16 +5V_A SW 15 L101 IHLP5050EZER2R2M01 SW C290 C291 C292 C293 C461 C462 R321 R-0 1 R316 R-1M C289 CC-390 +12V_A_PG[21] EN MPQ8632GLE-12 R317 R318 CC-47u/10V CC-47u/10V CC-47u/10V CC-47u/10V CC-47u/10V CC-47u/10V

3 R-100 R-49K9 7 FB R320 C294 VCC R322

CC-1u/10V 4 R-47K GND_A_5V_A 6 SS C297 R-6K49

+5V_A_PG[21] D PG D D D D N N N N N G G G G G CC-100n A P P P P Connect both grounds in one single 5 0 1 2 3

1 1 1 1 connection point on the pcb GND_A_5V_A

GND_A_5V_A

GND_A_5V_A Figure 3-56 Power Regulator Circuit for 5V_Switched

+5V_A U41 1 8 +5V_S 13 VIN VOUT 9 C317 C318 +3.3V_A VIN VOUT 10 C319 C320 3 VOUT 11 CC-4u7/10V CC-100n C356 VCC VOUT 12 CC-100n CC-4u7/10V VOUT CC-100n 4 GND PSON 2 EN 7 R375 R-330 BLEED C357 CC-100n 5 6 +5V_S_PG SR PG NCP45560IMNTWG-H

Note

For details on PSON signaling see Chapter 3.18.3 .

Qseven Design Guide Page 99 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.17.2 ATX Power Supply ATX power supplies are widely used for consumer PC motherboards and they are also a cost effective and reliable solution for embedded designs. ATX power supplies provide all the necessary power rails required for a carrier board design and may be an alternative to a custom power supply design. Table 3-34 and Table 3-36 describe the signals provided by the ATX power supply connectors.

Note

This is an example only.

The Qseven V2.0 reference carrier board is not using an ATX power supply.

3.17.2.1 ATX Power Connector Table 3-34 ATX Connector 24 PIN

Signal Pin Description Signal Pin Description 3.3V 1 +3.3V Power Supply 3.3V 13 +3.3V Power Supply 3.3V 2 +3.3V Power Supply -12V 14 -12V Power Supply COM 3 Ground COM 15 Ground 5V 4 +5V Power Supply PS_ON# 16 Active low signal, which is controlled by the Qseven® module to turn on or off the ATX power supply. COM 5 Ground COM 17 Ground 5V 6 +5V Power Supply COM 18 Ground COM 7 Ground COM 19 Ground PWR_OK 8 Status signal generated by the ATX power Reserved 20 N.C. supply to notify the Qseven® module that the DC operating voltages are within the ranges required for proper operation. 5VSB 9 +5V Standby Voltage +5V 21 +5V Power Supply +12V 10 +12V Power Supply +5V 22 +5V Power Supply +12V 11 +12V Power Supply +5V 23 +5V Power Supply +3.3V 12 +3.3V Power Supply COM 24 Ground

Note

The above table describes the pinout of a 24-pin ATX connector. When using a 20-pin ATX connector omit the following four pins: 11, 12, 23 and 24.

Signal Pin Description Signal Pin Description 3.3V 1 +3.3V Power Supply 3.3V 11 +3.3V Power Supply 3.3V 2 +3.3V Power Supply -12V 12 -12V Power Supply COM 3 Ground COM 13 Ground 5V 4 +5V Power Supply PS_ON# 14 Active low signal, which is controlled by the Qseven® module to turn on or off the ATX power supply. COM 5 Ground COM 15 Ground 5V 6 +5V Power Supply COM 16 Ground COM 7 Ground COM 17 Ground PWR_OK 8 Status signal generated by the ATX power Reserved 18 N.C. supply to notify the Qseven® module that the DC operating voltages are within the ranges required for proper operation. 5VSB 9 +5V Standby Voltage +5V 19 +5V Power Supply +12V 10 +12V Power Supply +5V 20 +5V Power Supply

Table 3-36 +12V Power Connector 4 Pin

Signal Pin Description Signal Pin Description GND 1 Ground GND 2 Ground +12V 3 +12V Power Supply +12V 4 +12V Power Supply

Figure 3-57 Schematic of 24 Pin ATX Power Connector

set jumper 1-2 for ATX supply controlled (default) set jumper 2-3 for ATX supply in AT mode +V12_IN +V5_ATX CN41(1-2) +V5_ATX +V3.3_ATX CN38 +V3.3_ATX MJMPR254 13 1 3.3V_3 3.3V_1 PS_ON# 14 2 19 PS_ON# -12V 3.3V_2 CN41 15 3 1 GND_4 GND_1 2 PS_ON#_JP 16 4 3 PSON 5V_1 17 5 XST1x3S GND_5 GND_2

CN48 3 18 6 D GND_6 5V_2 +V5_SBY_IN 3,7,19,20 SUS_S3# 1 Q13 19 7 2 PS_ON 1 TBSS138 GND_7 GND_3 G 3 S2 20 8 ATX_PG -5V POK 3,7,19 SUS_S5# R208 21 9 XST1x3S R1%100kS03 5V_3 5VSB 22 10 5V_4 12V_1 CN48(1-2) 23 11 5V_5 12V_2 24 12 MJMPR254 GND_8 3.3V 25 26 25 XPWRATX24S 26 set jumper 1-2 for ATX supply controlled by signal S3 (default) set jumper 2-3 for ATX supply controlled by signal S5

+V5_SBY_IN +V12_IN +V5_ATX +V3.3_ATX

C228 C227 C290 C291 C100nS03V50X C100nS03V50X C100nS03V50X C100nS03V50X

Qseven Design Guide Page 101 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.17.3 RTC Battery The Real Time Clock (RTC) is responsible for maintaining the time and date even when the Qseven® module is not connected to a main power supply. Usually a +3V lithium battery cell is used to supply the internal RTC of the module. The Qseven® specification defines an extra power pin 'VCC_RTC', which connects the RTC of the module to the external battery. The specified input voltage range of the battery is defined between +2.4V and +3.3V. The signal 'VCC_RTC' can be found on the module's connector pin 193.

3.17.3.1 RTC Battery Reference Circuitry To implement the RTC Battery according to the Underwriters Laboratories Inc® (UL) guidelines, battery cells must be protected against a reverse current going to the cell. This can be done by either a series Schottky diode or a series resistor. The safest way, and the one recommended by the SGeT e.V., is to implement a RTC battery circuitry using a Schottky diode (D1404) as shown in Figure 3-58.

This method offers protection against a possible explosion hazard as a result of reverse current flowing to the battery. Moreover, this implementation offers more flexibility when choosing battery type and manufacturer. Lithium batteries are the most common form of battery used in this scenario.

Figure 3-58 RTC Battery Circuitry with Serial Schottky Diode

C263 VCC_RTC [3] R281 1 2 3 CC-1u/10V/X P16 SHORTING_PLUG JP13 JP-3X1 R-1K

BAT54C +3.3V_A

R286 R-1K BT1 1 CN35 D20 Coin Cell Battery

BTM-2032GW-U CR2032 2

Note

The SGeT e.V. recommends that a warning label is placed on or near the carrier board battery socket to indicate the appropriate manufacturer and model of battery that must be used to avoid creating an explosion hazard. This applies regardless of which RTC battery circuitry method has been implemented on the carrier board.

3.17.3.2 RTC Battery Lifetime The RTC battery lifetime determines the time interval between system battery replacement cycles. Current leakage from the RTC battery circuitry on the carrier board is a serious issue and must be considered during the system design phase. The current leakage will influence the RTC battery lifetime and must be factored in when a specific life expectancy of the system battery is being defined.

In order to accurately measure the value of the RTC current it should be measured when the complete system is disconnected from AC power.

The RTC power plane is normally ored with the 3V3 Voltage on the module, so it may not be necessary to perform this on the carrier board. Please consult the module vendor's documentation.

Signal Pin# Description of Power Control signals I/O Type IOL/IIL I/O PWGIN 26 High active input for the Qseven® module indicates that CMOS ≥ 4 mA I power from the power supply is ready. 5V PWRBTN# 20 Power Button: Low active power button input. This signal is CMOS OD ≥ 10 mA I triggered on the falling edge. 3.3V Standby

Note

Termination of all signals (e.g. required pullup/pulldown resistors) will be always on the module unless explicitly otherwise noted.

3.18.1 Power Good Input Signal PWGIN This signal is optionally generated by the power supply circuitry and indicates that the operating voltages are within the ranges required for proper operation of the Qseven ® module and carrier board components. The example in Figure 3-59 shows the implementation on the Qseven V2.0 reference carrier board.

Figure 3-59 PWGIN Generation Circuit

+5V_S

R346

+12V_S_PG +12V_S_PG D43 1PS79SB40 +5V_S U36 +5V_S_PG D38 1PS79SB40 R-10K 1 5 +5V_S_PG 2 A VCC +3.3V_S_PG D39 1PS79SB40 3 B 4 GND (A&B) PWGIN [3,6] +3.3V_S_PG +1.5V_S_PG[20] D40 1PS79SB40 NC7S08M5X C337

CC-100n +5V_S

R350

+3.3V_A_PG[20] D41 1PS79SB40 R-10K ALW_PG

+5V_A_PG[20] D42 1PS79SB40

3.18.2 Power Button Signal PWRBTN# The power button signal is used to turn on the Qseven® based system when using an ATX power supply or to wake up the system from ACPI power states S3 and S5. If the Power button is pressed for 4 seconds or longer a power override occurs and the power will be turned off (for x86 based modules only- check with your module vendor's user's guide for ARM based modules).

Figure 3-60 Power Button Implementation Example

SW7 1 3 PWRBTN# [3,6]

4 2 KTH00143-R

Note

In a case where the system does not require a power button (system boots automatically when the power is supplied) the PS_ON# signal of the ATX power supply must be pulled to ground (see Figure 3-61 jumper J1603).

Qseven Design Guide Page 103 of 126 V2.0 March 5, 2015 © 2015 SGeT e.V. 3.18.3 Power Up Control The power up control is responsible for switching the Qseven V2.0 reference carrier board on or off when a power-up or a power-down event occurs. A power event can be generated by pressing the power button or by another system event, which can originate from or be detected by the Qseven® module's chipset.

The native system power-up support of Qseven® modules utilize the 'SUS_S3#' signal to control the 'PSON' signal, which is used to switch the supply rails on or off. When using the SUS_S3#' signal, Qseven® modules are capable of supporting Suspend to RAM (S3).

When the system goes to Suspend to RAM (S3) or Soft Off (S5), the 'SUS_S3#' signal is asserted by the chipset of the module. Through this behavior the signal can be used to drive 'PSON' and switches off the power rails of the carrier. Vice versa, if the system is in a power-down system state, any system wake-up event invokes the module's chipset to deassert the 'SUS_S3#' signal and transfers the system to Full-On (S0) state.

Figure 3-61 Power Up Control Circuitry

+3.3V_A

R545

JP23 P27 3 R-10K SHORTING_PLUG 2 Jumper X29 settings: PSON [20] 1-2: ATX PSU is controlled (default) 1 2-3: ATX PSU in AT mode BUF_SUS_S3# [3,6] JP-3X1 Note