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IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII Or RMII

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IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII Or RMII KSZ8463ML/RL/FML/FRL IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII Features Port 2 and Source Address Filtering for Imple- menting Ring Topologies Management Capabilities • MAC Filtering Function to Filter or Forward • The KSZ8463ML/RL/FML/FRL Includes All the Unknown Unicast Packets Functions of a 10/100BASE-T/TX/FX Switch Sys- • Port 1 and Port 2 MACs Programmable as Either tem that Combines a Switch Engine, Frame Buffer E2E or P2P Transparent Clock (TC) Ports for Management, Address Look-Up Table, Queue 1588 Support Management, MIB Counters, Media Access Con- • Port 3 MAC Programmable as Slave or Master of trollers (MAC) and PHY Transceivers Ordinary Clock (OC) Port for 1588 Support • Non-Blocking Store-and-Forward Switch Fabric • Microchip LinkMD® Cable Diagnostic Capabilities Ensures Fast Packet Delivery by Utilizing 1024 for Determining Cable Opens, Shorts, and Length Entry Forwarding Table • Port Mirroring/Monitoring/Sniffing: Ingress and/or Advanced Switch Capabilities Egress Traffic to any Port • Non-Blocking Store-and-Forward Switch Fabric • MIB Counters for Fully Compliant Statistics Gath- Ensures Fast Packet Delivery by Utilizing 1024 ering: 34 Counters per Port Entry Forwarding Table • Loopback Modes for Remote Failure Diagnostics • IEEE 802.1Q VLAN for Up to 16 Groups with Full • Rapid Spanning Tree Protocol Support (RSTP) for Range of VLAN IDs Topology Management and Ring/Linear Recovery • IEEE 802.1p/Q Tag Insertion or Removal on a per • Bypass Mode Ensures Continuity Even When a Port Basis (Egress) and Support Double-Tagging Host is Disabled or Fails • VLAN ID Tag/Untag Options on per Port Basis Robust PHY Ports • Fully Compliant with IEEE 802.3/802.3u Stan- dards • Two Integrated IEEE 802.3/802.3u-Compliant • IEEE 802.3x Full-Duplex with Force-Mode Option Ethernet Transceivers Supporting 10BASE-T and and Half-Duplex Backpressure Collision Flow 100BASE-TX Control • Copper and 100BASE-FX Fiber Mode Support in • IEEE 802.1w Rapid Spanning Tree Protocol Sup- the KSZ8463FML and KSZ8463FRL port • Copper Mode Support in the KSZ8463ML and • IGMP v1/v2/v3 Snooping for Multicast Packet Fil- KSZ8463RL tering • On-Chip Termination Resistors and Internal Bias- • QoS/CoS Packets Prioritization Support: 802.1p, ing for Differential Pairs to Reduce Power DiffServ-Based and Re-Mapping of 802.1p Prior- • HP Auto MDI/MDI-X Crossover Support Elimi- ity Field per Port Basis on Four Priority Levels nates the Need to Differentiate Between Straight • IPv4/IPv6 QoS Support or Crossover Cables in Applications • IPv6 Multicast Listener Discovery (MLD) Snoop- MAC Ports ing Support • Three Internal Media Access Control (MAC) Units • Programmable Rate Limiting at the Ingress and • MII or RMII Interface Support on MAC Port 3 Egress Ports • 2Kbyte Jumbo Packet Support • Broadcast Storm Protection • Tail Tagging Mode (One byte Added before FCS) • Bypass Mode to Sustain the Switch Function Support at Port 3 to Inform The Processor Which between Port 1 and Port 2 when CPU (Port 3) Ingress Port Receives the Packet and its Priority Goes into Sleep Mode • Supports Reduced Media Independent Interface • 1K Entry Forwarding Table with 32K Frame Buffer (RMII) with 50 MHz Reference Clock Input or Out- • Four Priority Queues with Dynamic Packet Map- put ping for IEEE 802.1p, IPv4 TOS (DIFFSERV), • Supports Media Independent Interface (MII) in IPv6 Traffic Class, etc. Either PHY Mode or MAC Mode on Port 3 • Programmable MAC Addresses for Port 1 and 2018 Microchip Technology Inc. DS00002642A-page 1 KSZ8463ML/RL/FML/FRL Comprehensive Configuration Registers Access • Energy Detect Power-Down (EDPD), which Dis- • High-Speed SPI (4-Wire, Up to 50 MHz) Interface ables the PHY Transceiver when Cables are to Access All Internal Registers Removed • MII Management (MIIM, MDC/MDIO 2-Wire) • Dynamic Clock Tree Control to Reduce Clocking Interface to Access All PHY Registers per Clause in Areas Not in Use 22.2.4.5 of the IEEE 802.3 Specification • Power Consumption Less than 0.5W • I/O Pin Strapping Facility to Set Certain Register Additional Features Bits from I/O Pins at Reset Time • Single 25 MHz ±50 ppm Reference Clock • Control Registers Configurable On-the-Fly Requirement for MII Mode IEEE 1588v2 PTP and Clock Synchronization • Selectable 25 MHz or 50 MHz Inputs for RMII • Fully Compliant with the IEEE 1588v2 Precision Mode Time Protocol • Comprehensive Programmable Two LED Indica- • One-Step or Two-Step Transparent Clock (TC) tors Support for Link, Activity, Full-/Half-Duplex Timing Corrections and 10/100 Speed • E2E (End-to-End) or P2P (Peer-to-Peer) Trans- • LED Pins Directly Controllable parent Clock (TC) • Industrial Temperature Range: –40°C to +85°C • Grandmaster, Master, Slave, Ordinary Clock (OC) • 64-Pin (10 mm x 10 mm) Lead Free (ROHS) Support LQFP Package • IEEE1588v2 PTP Multicast and Unicast Frame Applications Support • Industrial Ethernet Applications that Employ IEEE • Transports of PTP Over IPv4/IPv6 UDP and IEEE 802.3-Compliant MACs. (Ethernet/IP, Profinet, 802.3 Ethernet MODBUS TCP, etc) • Delay Request-Response and Peer Delay Mech- • Real-Time Ethernet Networks Requiring Sub- anism Microsecond Synchronization over Standard • Ingress/Egress Packet time stamp Capture/ Ethernet Recording and Checksum Update • IEC 61850 Networks Supporting Power Substa- • Correction Field Update with Residence Time and tion Automation Link Delay • Networked Measurement and Control Systems • IEEE1588v2 PTP Packet Filtering Unit to Reduce • Industrial Automation and Motion Control Sys- Host Processor Overhead tems • A 64-bit Adjustable System Precision Clock • Test and Measurement Equipment • Twelve Trigger Output Units and Twelve time stamp Input Units Available for Flexible IEEE1588v2 Control of Twelve Programmable GPIO[11:0] Pins Synchronized to the Precision Time Clock • GPIO Pin Usage for 1 PPS Generation, Fre- quency Generator, Control Bit Streams, Event Monitoring, Precision Pulse Generation, Complex Waveform Generation Power and Power Management • Single 3.3V Power Supply with Optional VDD I/O for 1.8V, 2.5V, or 3.3V • Integrated Low Voltage (~1.3V) Low-Noise Regu- lator (LDO) Output for Digital and Analog Core Power • Supports IEEE P802.3az™ Energy Efficient Ethernet (EEE) to Reduce Power Consumption in Transceivers in LPI State • Full-Chip Hardware or Software Power-Down (All Registers Value are Not Saved and Strap-In Value will Re-Strap After Release the Power-Down) DS00002642A-page 2 2018 Microchip Technology Inc. KSZ8463ML/RL/FML/FRL TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected]. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2018 Microchip Technology Inc. DS00002642A-page 3 KSZ8463ML/RL/FML/FRL Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 5 2.0 Pin Description and Configuration ................................................................................................................................................... 9 3.0 Functional Description ................................................................................................................................................................... 17 4.0 Register Descriptions .................................................................................................................................................................... 59 5.0 Operational Characteristics ......................................................................................................................................................... 189 6.0 Electrical Characteristics ............................................................................................................................................................. 190 7.0 Timing Specifications
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