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Development of a Digital Terrestrial Front End

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Development of a Digital Terrestrial Front End DEVELOPMENT OF A DIGITAL TERRESTRIAL FRONT END J D Mitchell (BBC) and P Sadot (LSI Logic, France) ABSTRACT BBC Research and Development and LSI Logic are jointly developing a front end for digital terrestrial television transmitted according to the DVB-T specification. The front end consists of two separate components. First, an analogue down-converter that converts the input signal from UHF to a low IF. Second, an integrated circuit that accepts the analogue signal from the down-converter and performs the required DSP operations, which include synchronisation and demodulation, to form a stream of soft decisions suitable for presentation to an FEC decoder. The development process began by agreeing a set of requirements to which the two components must conform. This paper begins by outlining these requirements. During the development of the components, many issues have been considered and resolved. A selection of the key issues and the decisions that were reached is given and, finally, a discussion of the architecture that results from these decisions is presented. INTRODUCTION BBC Research and Development and LSI Logic are working together on the development of a digital terrestrial front end which is capable of decoding transmissions compliant with the European DVB-T specification (1). This development unites the BBC's system expertise in COFDM, see Nokes et al. (2), Stott (3) and (4), and LSI Logic's long-established chip design capability. As part of the front end development, LSI Logic and the BBC are working together on two distinct, but related, development projects: a single CMOS chip implementing a complete OFDM demodulator, and a new terrestrial down-converter designed for use with the digital chip. The aim of the overall system design is to optimise the cost effectiveness of the complete front end. This paper specifically addresses three technical issues: An overview of the new terrestrial down-converter, a selection of the possible trade-offs in the chip and the decisions that were taken, and the resulting architecture of the integrated circuit and a discussion about the function of each of the component blocks. REQUIREMENTS The target of LSI Logic and the BBC was to implement a fully DVB-T compliant COFDM demodulator. This section describes the initial set of requirements which were the basis of the architecture of the digital demodulator chip, called the L64780 in LSI Logic's DVB product range. Modes of operation Full compliance to the DVB-T specification means that the chip must be capable of decoding signals transmitted in the following modes: A signal that contains either 1705 or 6817 active carriers, commonly referred to as 2K and 8K respectively. The L64780 includes the functionality and memory required to perform the FFT algorithm in both modes. Non-hierarchical QPSK, 16-QAM and 64-QAM constellations. Hierarchical 16-QAM and 64-QAM constellations, either uniform or non uniform with the possible scale factors =2 and =4. Guard Intervals 1/4, 1/8, 1/16 and 1/32 of the OFDM symbol length. Viterbi code rates 1/2, 2/3, 3/4, 5/6 and 7/8. Channel impairments The front end architecture must provide the best possible performance under actual operating conditions. There are several key types of channel impairments that the front end must be adept at dealing with. Some of the key channel impairments are explained below: Adjacent analogue television signals. In multi-frequency networks OFDM signals may be transmitted in adjacent channels to PAL signals that could be 30dB higher in power. Therefore, special care must be taken when designing the IF filtering scheme in the down-converter. Co-channel analogue television interference. This will be particularly significant in interleaved frequency networks. Delayed signal interference, either due to reflections from natural obstacles, or created by the network itself as is the case with single frequency networks. Such interference causes frequency selective fading which may completely erase, or significantly affect the reliability of, the bits of information carried by some of the OFDM carriers. Narrow-band interference coming from intermodulation products due to non-linearities in the transmission chain may also corrupt the bits of information carried by some of the OFDM carriers but in a different way from the frequency selective fading. Co-channel interference from artificial sources such as radio microphones operating in the UHF frequency band and of course thermal noise, as is present in every transmission system. Down-converter performance The down-converter architecture must cope with the specific requirements of COFDM whilst operating in the channel conditions described above. This means: the IF filtering must ensure the proper rejection of adjacent channel analogue television signals, the gain distribution must preserve linearity in order not to create intermodulation products between the OFDM carriers, thus creating a self-interference effect on the signal, and the synthesiser phase-noise characteristics must be compatible with 64-QAM operation. Fast acquisition time The time and frequency synchronisation algorithms were defined with two objectives in mind: They must be robust enough to ensure reliable receiver acquisition in the presence of the above channel conditions, i.e. they must acquire the signal in conditions worse than those that would cause failure of the receiver due to data failure alone, and the overall acquisition time must be minimised to allow acceptable "channel hopping" times. Interfaces The output interfaces of the chip must allow for easy integration with existing chip-sets. Fig. 1 shows the overall structure of a DTT receiver. The key components to the system are the front-end (which for terrestrial applications consists of a down-converter, the OFDM demodulator chip and an FEC decoder), the transport stream demultiplexer, the audio and video decoders and the overall system microcontroller. Fig. 1 - Top level structure of a DTT receiver. The OFDM demodulator is the first chip in LSI Logic's digital terrestrial television product range. It will permit first generation DTTV set-top boxes based on a down-converter, the L64780 itself and an FEC chip such as the L64705 or the FEC part of the L64724. In a fully integrated set-top box, front-end components for satellite and cable may also be provided. The microprocessor interface of the OFDM demodulator chip can operate in two modes, either parallel or serial (I2C like). ARCHITECTURAL TRADE-OFFS During the development of the front-end many architectural trade-offs had to be considered. This section provides a discussion of some of the key trade-offs that were made. Memory budget The most significant problem that was encountered during the design of the integrated circuit was the amount of RAM that the chip required, even taking into account state-of-the-art developments in RAM technology. In planning the architecture, we wanted to make the best possible use of the RAM that we could fit onto the chip. Some of the blocks of memory, such as the FFT and symbol deinterleaver, require fixed amounts of RAM and it is not possible to reduce them (except by reducing the word widths and so degrading the performance). Other blocks, for example the timing synchronisation, required some algorithmic alterations for the sole purpose of reducing the amount of memory but without degrading the performance. The final technique that was employed to make best use of the available memory was to "reuse" some of the memories. For example, the data delay required to implement common- phase-error correction doubles as the first data delay in the channel equaliser. This means that only two additional data delays were required to implement full linear temporal equalisation. Table 1 shows the final allocations of RAM that were made in the chip. As this table shows, the highest memory usage is in the FFT circuitry and the smallest is in the timing synchronisation circuitry. We have found that this memory allocation provides the best compromise between performance and cost. Table 1: Proportion of RAM used by different elements of the DSP. Analogue versus digital AFC One of the processes that is required in the synchronisation of the demodulator is to obtain frequency synchronisation. In our front-end architecture we always make the measurement of the AFC error digitally, but we had the choice as to whether to apply the required frequency shift as an analogue correction in the down-converter, or as a digital frequency shift in the chip. Analogue frequency correction If we choose to implement the frequency correction by adjusting the frequency of the reference crystal in the down-converter, then we have to provide a control signal from the output of the integrated circuit back to the down-converter. This method has the advantage that the SAW filter inside the down-converter can be made as narrow as possible. The disadvantages are twofold. First, the integrated circuit must pass a control signal back to the down-converter. Second, the architecture of the down-converter is made more complicated since the control signal must adjust the reference crystal within the search range of the AFC. Digital frequency correction If we choose to implement the frequency correction in the integrated circuit, then the architecture of the down-converter is made much simpler since there is no longer any need to have a control signal from the chip, and the loop in the down-converter that drives the reference crystal is no longer required. The disadvantage of this method is that the bandwidth of the SAW filter must be increased by the AFC search range. This causes a significant penalty in terms of the adjacent channel protection ratio when the receiver is used in an environment where the existing analogue services are operated in adjacent channels to the new digital services.
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