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System V Application Binary Interface AMD64 Architecture Processor Supplement Draft Version 0.98

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System V Application Binary Interface AMD64 Architecture Processor Supplement Draft Version 0.98 System V Application Binary Interface AMD64 Architecture Processor Supplement Draft Version 0.98 Edited by Michael Matz1, Jan Hubickaˇ 2, Andreas Jaeger3, Mark Mitchell4 September 27, 2006 [email protected] [email protected] [email protected] [email protected] AMD64 ABI Draft 0.98 – September 27, 2006 – 9:24 Contents 1 Introduction 8 2 Software Installation 9 3 Low Level System Information 10 3.1 Machine Interface . 10 3.1.1 Processor Architecture . 10 3.1.2 Data Representation . 10 3.2 Function Calling Sequence . 13 3.2.1 Registers and the Stack Frame . 14 3.2.2 The Stack Frame . 14 3.2.3 Parameter Passing . 15 3.3 Operating System Interface . 22 3.3.1 Exception Interface . 22 3.3.2 Virtual Address Space . 22 3.3.3 Page Size . 24 3.3.4 Virtual Address Assignments . 24 3.4 Process Initialization . 25 3.4.1 Initial Stack and Register State . 25 3.4.2 Thread State . 29 3.4.3 Auxiliary Vector . 29 3.5 Coding Examples . 31 3.5.1 Architectural Constraints . 32 3.5.2 Conventions . 34 3.5.3 Position-Independent Function Prologue . 35 3.5.4 Data Objects . 36 3.5.5 Function Calls . 44 3.5.6 Branching . 46 1 AMD64 ABI Draft 0.98 – September 27, 2006 – 9:24 3.5.7 Variable Argument Lists . 49 3.6 DWARF Definition . 54 3.6.1 DWARF Release Number . 54 3.6.2 DWARF Register Number Mapping . 54 3.7 Stack Unwind Algorithm . 54 4 Object Files 58 4.1 ELF Header . 58 4.1.1 Machine Information . 58 4.1.2 Number of Program Headers . 58 4.2 Sections . 59 4.2.1 Section Flags . 59 4.2.2 Section types . 60 4.2.3 Special Sections . 60 4.2.4 EH_FRAME sections . 61 4.3 Symbol Table . 66 4.4 Relocation . 66 4.4.1 Relocation Types . 66 4.4.2 Large Models . 70 5 Program Loading and Dynamic Linking 72 5.1 Program Loading . 72 5.1.1 Program header . 73 5.2 Dynamic Linking . 73 5.2.1 Program Interpreter . 79 5.2.2 Initialization and Termination Functions . 79 6 Libraries 80 6.1 C Library . 80 6.1.1 Global Data Symbols . 80 6.1.2 Floating Point Environment Functions . 80 6.2 Unwind Library Interface . 81 6.2.1 Exception Handler Framework . 82 6.2.2 Data Structures . 84 6.2.3 Throwing an Exception . 86 6.2.4 Exception Object Management . 89 6.2.5 Context Management . 89 6.2.6 Personality Routine . 92 2 AMD64 ABI Draft 0.98 – September 27, 2006 – 9:24 6.3 Unwinding Through Assembler Code . 96 7 Development Environment 99 8 Execution Environment 100 9 Conventions 101 9.1 C++ . 102 9.2 Fortran . 103 9.2.1 Names . 103 9.2.2 Representation of Fortran Types . 104 9.2.3 Argument Passing . 105 9.2.4 Functions . 106 9.2.5 COMMON blocks . 107 9.2.6 Intrinsics . 108 A Linux Conventions 119 A.1 Execution of 32-bit Programs . 119 A.2 AMD64 Linux Kernel Conventions . 119 A.2.1 Calling Conventions . 119 A.2.2 Stack Layout . 120 A.2.3 Required Processor Features . 120 A.2.4 Miscellaneous Remarks . 120 3 AMD64 ABI Draft 0.98 – September 27, 2006 – 9:24 List of Tables 3.1 Hardware Exceptions and Signals . 23 3.2 Floating-Point Exceptions . 23 3.3 x87 Floating-Point Control Word . 26 3.4 MXCSR Status Bits . 26 3.5 rFLAGS Bits . 27 4.1 AMD64 Identification . 58 4.2 AMD64 Specific Section Header Flag, sh_flags . 59 4.3 Section Header Types . 60 4.4 Special sections . 60 4.5 Additional Special Sections for the Large Code Model . 61 4.6 Common Information Entry (CIE) . 63 4.7 CIE Augmentation Section Content . 64 4.8 Frame Descriptor Entry (FDE) . 65 4.9 FDE Augmentation Section Content . 66 4.10 Relocation Types . 69 4.11 Large Model Relocation Types . 71 5.1 Program Header Types . 73 7.1 Predefined Pre-Processor Symbols . 99 9.1 Mil intrinsics . 109 9.2 F77 intrinsics . 111 9.3 F90 intrinsics . 112 9.4 Math intrinsics . 112 9.5 Unix intrinsics . 114 A.1 Required Processor Features . 121 4 AMD64 ABI Draft 0.98 – September 27, 2006 – 9:24 List of Figures 3.1 Scalar Types . 11 3.2 Bit-Field Ranges . 13 3.3 Stack Frame with Base Pointer . 15 3.4 Register Usage . 20 3.5 Parameter Passing Example . 21 3.6 Register Allocation Example . 22 3.7 Virtual Address Configuration . 24 3.8 Conventional Segment Arrangements . 25 3.9 Initial Process Stack . 28 3.10 auxv_t Type Definition . 29 3.11 Auxiliary Vector Types . 30 3.12 Position-Independent Function Prolog Code . 35 3.13 Absolute Load and Store (Small Model) . 37 3.14 Position-Independent Load and Store (Small PIC Model) . 38 3.15 Absolute Load and Store (Medium Model) . 39 3.16 Position-Independent Load and Store (Medium PIC Model) . 40 3.17 Position-Independent Load and Store (Medium PIC Model), con- tinued . 41 3.18 Absolute Global Data Load and Store . 42 3.19 Faster Absolute Global Data Load and Store . 42 3.20 Position-Independent Global Data Load and Store . 43 3.21 Faster Position-Independent Global Data Load and Store . 43 3.22 Position-Independent Direct Function Call (Small and Medium Model) . 44 3.23 Position-Independent Indirect Function Call . 44 3.24 Absolute Direct and Indirect Function Call . 45 3.25 Position-Independent Direct and Indirect Function Call . 45 3.26 Absolute Branching Code . 47 5 AMD64 ABI Draft 0.98 – September 27, 2006 – 9:24 3.27 Implicit Calculation of Target Address . 47 3.28 Position-Independent Branching Code . 48 3.29 Absolute Switch Code . 48 3.30 Position-Independent Switch Code . 49 3.31 Parameter Passing Example with Variable-Argument List . 50 3.32 Register Allocation Example for Variable-Argument List . 50 3.33 Register Save Area . 51 3.34 va_list Type Declaration . 51 3.35 Sample Implementation of va_arg(l, int) . 53 3.36 DWARF Register Number Mapping . 55 3.37 Pointer Encoding Specification Byte . 57 4.1 Relocatable Fields . 67 5.1 Global Offset Table . 74 5.2 Procedure Linkage Table (small and medium models) . 76 5.3 Final Large Code Model PLT . 78 6.1 Examples for Unwinding in Assembler . 98 9.1 Example mapping of names . 104.
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