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CISC 3310 – Homework 2, Chapter 3 Answers 1. A. Yz + Z(Xy)

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CISC 3310 – Homework 2, Chapter 3 Answers 1. A. Yz + Z(Xy) CISC 3310 – Homework 2, Chapter 3 Answers 1. a. yz + z(xy)' x y z yz xy (xy)' z(xy)' yz+z(xy)' 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 c. (x + y)(x' + y) => y y (x+y)(x'+y) 0 0 1 1 2. a. xyz + z(yz)' + x'(y+z) + (xyz)' => 1 The terms xyz and (xyz)' are complementary and are joined by the logical operator + yielding the expression: xyz + (xyz)'. This expression always evaluates to 1, and since it is joined to the other terms in the original expression by the logical operator +, the entire expression will always evaluate to 1. 4. F(x,y,z) = (x' +y)(x + z)(y' + z)' F'(x,y,z) = ((x' + y)(x + z)(y' + z)')' = (x' + y)' + (x + z)' + (y' +z)'' = x''y' + x'z' + (y' + z) = xy' + x'z' + (y' + z) 9. (x XOR y)' = xy + (x + y)' x y x XOR y xy x + y (x + y)' xy + (x + y)' (x XOR y)' 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 1 0 1 1 * * *The two rightmost columns (starred) represent the truth-values of the expressions proposed to be equivalent. They are identical and so, the expressions are logically equivalent. 10. x = xy + xy' a. x y y' xy xy' xy + xy' 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 1 * * * Rightmost column and leftmost (starred) have the same set of truth values, therefore the expressions are logically equivalent. b. x/y 0 1 0 0 0 1 1 1 * Simplified expression: x : citcle bottom row 13. xz + x'y' + y'z' = xz + y' 22. Sum-of-Products: x'y'z' + x'yz' + xy'z + xyz' + xyz 25. xy' + x'y + xz + y'z Truth Table: x y z xy' + x'y + xz + y'z 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 Complemented Sum-of-Products: (x'y'z' + xyz')' 27. F(x,y,z) = y(x'z + xz') + x(yz + yz') a. x y z x' z' x'z xz' x'z + xz' y(x'z + xz') yz yz' Yz + yz' x(yz + yz') y(x'z + xz') + x(yz + yz') 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 b. (On separate page). c. x\y,z 0,0 0,1 1,1 1,0 0 0 0 1 0 1 0 0 1 1 * Simplified expression: xy + yz: circle 3rd column (yz) and bottom right two cells (xy) d. x y z yz xy xy + yz 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 e. (On separate page). 32. Truth Table: x y z F1 F2 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 0 K-map: F1 x\y,z 0,0 0,1 1,1 1,0 0 1 1 0 0 1 0 0 1 1 *Simplified expression: F1(x,y,z) = x'y' + xy: circle top left two cells (x'y') and bottom right two (xy) F2 x\y,z 0,0 0,1 1,1 1,0 0 0 0 1 1 1 1 1 0 0 *Simplified expression: F2(x,y,z) = xy' + x'y: circle top right two (x'y) and bottom left 2 (xy') **Circuit on separate page. 34. (On separate page). 37. x y z F1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 39. Decoder with 64 = 26 outputs has 6 inputs. 40. Multiplexer with 32 = 25 input has 5 selectors. 42. a. F1(x,y,z) = x'y'z' + x'y'z + x'yz' F2(x,y,z) = x'yz' + xy'z' + xyz' + xyz b. F1 x\y,z 0,0 0,1 1,1 1,0 0 1 1 0 1 1 0 0 0 0 F2 x\y,z 0,0 0,1 1,1 1,0 0 0 0 1 1 1 0 0 1 1 F1 is x'y' + x'z' (circle top left for x'y' and wrap top left and top right for x'z') F2 is y (circle of 4) c. (Circuit on separate page). 47. B'SW + BS'W + B'SW' + BSW Truth Table: B S W F 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 *Simplified expression: F(B,S,W) = BW + B'S K-Map: B\SW 00 01 11 10 0 1 1 1 1 1 Circle top right two cells: B'S Circle bottom middle two cells: BW Don't circle column 3 because all 1's are already covered by other circles. 51. (On separate page). 60. 1. Address is asserted on S0 and S1 2. Write enable is set to low (0) 3. Decoder using S0 and S1 enables a unique and-gate for each set of possible inputs, selecting a given word in memory. 4. When the line for the selected word is set to high (1), it is coupled with the value stored in each D flip-flop (each bit of the word) using an and-gate. 5. The combined values of the D flip-flop and the line from S0 and S1 determine whether the and- gate is activated and passes along the corresponding value to the output gate. K-maps (p. 209) 1. a. x'z + xz' b. x'z + x'y + xy'z' c. y' + z' + x 2. a. x' + y'z' b. y'z' + x'z' c. z' + xy 3. A x\y,z 0,0 0,1 1,1 1,0 0 1 0 1 1 1 0 0 0 0 simplified: x'y + xz' B x\y,z 0,0 0,1 1,1 1,0 0 1 0 0 1 1 1 0 0 1 simplified: z' C x\y,z 0,0 0,1 1,1 1,0 0 1 1 0 0 1 1 1 0 1 simplified: y' + xz'.
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