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Megabits to Megabytes: Bubble Memory System Design and Board Layout

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Megabits to Megabytes: Bubble Memory System Design and Board Layout A Publication of Intel Corporation September/October 1985 INTEL BRINGS HARMONY TO THE FACTORYFLOOR ApPLICATION NOTE Megabits to Megabytes: System Overview The Intel bubble memory solution consists of a highly so­ Bubble Memory System phisticated Bubble Memory Controller (BMC) that can sup­ port up to an entire megabyte for the 7200 controller, or up Design and Board Layout to four megabytes using the new 7225 Four-Megabit Bubble Memory Controller. In other words, one controller can sup­ by Steven K. Knapp port up to eight Bubble Storage Units (BSUs). he sophisticated seven-component bubble memory se­ Bubble Memory Controller (BMC) Tlection from Intel represents the most integrated solution The Bubble Memory Controller is a VLSI chip that provides for reliable, non-volatile memory applications. Bubble mem­ a complete bi-directional interface between the host micro­ ory's solid-state operation can offer much higher system processor system and the Bubble Memory Storage Unit reliability than that obtainable with other mass storage tech­ (BSU). The bubble memory designer's primary task is to nologies such as standard tape and disk drives, both of interface the Bubble Memory Controller (BMC) to the host which can suffer due to shock and vibration. Bubble memory microprocessor system. The interface to the BMC is much is compact, requires no routine maintenance, and can op­ like that of any standard peripheral controller, such as a erate in extreme temperatures, making it ideal for applica­ floppy-disk controller or a DMA controller. The actual electri­ tions such as industrial control or military systems that require cal interface between the BMC and the BSU is provided by consistent and maintenance-free operation. Intel's Bubble Intel, since this part of the system will remain entirely un­ Memory Controller (BMC) also makes interfacing to any changed from one design to another. Because the BMC is a microprocessor or microcontroller easy. peripheral controller, it also requires a certain amount of software for complete operation. Generally, this code has an Component bubble memory designs present no form factor approximate length of 1K-bytes. Upon receipt of a software limitations, allowing the system designer freedom to build a command from the host processor, the BMC generates the mass storage system to custom specifications. For the most proper timing and control signals necessary to operate the part, a bubble memory system is designed and assembled remaining support circuitry in each BSU. much like any other component design. However, there are a few unique considerations to be aware of before designing The functional description of each of the six support com­ any bubble memory system. The attention paid to a few ponents found in a Bubble Storage Unit (BSU) is as follows simple design guidelines will ensure the system design en­ (See figure 1): gineer a successful bubble memory system. 20 - Figure 1: A complete bubble memory storage system SEPTEMBER/OCTOBER 19B5 SOLUTIONS Magnetic Bubble Memory (MBM) Board Layout: How to Avoid the Pitfalls One Megabit Density: 711 OA, 711 OAZ Once the design engineer has completed the simple task of Four Megabit Density: 7114 interfacing the BMC to the host microprocessor or microcon­ The Magnetic Bubble Memory (MBM) is a high-density, highly troller, the next aspect of design is the board layout. The reliable, non-volatile solid state memory based on magnetic most critical layout area on a bubble memory board exists bubble technology. It is contained in a 20-pin leaded pack­ around the traces between the bubble memory detector out­ age surrounded by a mu-metal magnetic shield. Intel offers put and the inputs to the FSA. These signals - which are both one megabit and four megabit bubble memories. The on the order of only five millivolts in amplitude for the 711 OA solid-state operation of bubble memory makes it immune to and thirty millivolts for the 7114-must be protected from the failures common to other forms of mass storage such as noise. The detector lines carry the low level data signals to tape and disk. Bubble memory is stock and vibration-resist­ the FSA, where the binary state is resolved and then con­ ant, immune to airborne particles, and operates over a wide verted to TIL-level signals, as shown in Figure 2. Reducing temperature range. Its magnetic technology guarantees non­ spurious noise on the detector traces improves bubble de­ volatile data integrity without the need for batteries. Further­ tection and increases system performance. more, it has unlimited read/write capabilities when com­ pared to other solid-state memory technologies s.uch as Though it may appear difficult to isolate the low level detec­ EPROMs and E2PROMs. Data within the bubble memory tor signals from the high current switching transients gener­ device is organized serially. However, to aid in standard ated by the coil drivers, there are some simple design rules system design, the bubble memory controller assimilates to follow to ensure reliable operation. the bit-wide data stream from a bubble memory and con­ verts it to a byte-wide data path for the host processor. First, the connections between the bubble detector outputs and the FSA inputs should be kept as short and direct as Current Pulse Generator (CPG) possible. This applies to the path through the signal filter as One Megabit Density: 7230 well (which is provided in the system schematic). Otherwise, Four Megabit Density: 7234 long signal traces can act as "antennae" to receive induced The Current Pulse Generator (sometimes called a function noise from higher-level signals. A decreased path length generator) generates the necessary precision current wave­ prevents any significant signal loss. The effect of noise is forms to input and output data from the MBM. also reduced through the actual design of the bubble detec­ tion mechanism using differential pair outputs to the FSA. Formatter Sense Amplifier (FSA) Since the output is a differential pair, these signal traces One Megabit Density: 7242 should have approximately the same conductor length so Four Megabit Density: 7245 that both sides of the signal path have balanced resistances. The Formatter/Sense Amplifier (FSA) interfaces directly with both the MBM and the BMC. It converts the low level signals from the bubble memory detector outputs into TIL-level logic signals. The FSA also enables the generation of magnetic bubbles within the MBM. The FSA performs the additional tasks of data formatting, error correcting, and mapping the redundancy built into the MBM (redundancy is built into many high-density memory devices to increase manufacturing yields). Coil Pre-Driver (CPO) The 7250 is used in both one megabit and four megabit systems. The data within a bubble memory is moved and accessed by passing currents of the proper magnitude and phase through two coils within the MBM. The Coil Pre-Driver (CPD) works in conjunction with the BMC to generate the signals for driving the X and Y coil drive transistors of the bubble memory. Drive Transistors One Megabit Density: (2) 7254 Four Megabit Density:(4) 7254 There are two sets of drive transistors in a bubble memory system. One set drives the X coil inside the MBM while the other drives the Y coil. Both act as analog switches to pro­ duce the high current coil driver waveforms. The high cur­ rent waveforms create a rotating magnetic field as they pass 21 through the internal coils of the MBM. Figure 2: Signal to TTL-level conversion SEPTEMBER/OCTOBER 19B5 SOLUTIONS - Second, it is imperative that no digital logic signals cross or two-layer board is quite appropriate for single-bubble sys­ come within close proximity to the detector traces. The cir­ tems, since this will typically have a less complicated layout cuit board designer should avoid running digital logic signals than a multi-bubble system and is sometimes cost sensitive. parallel to the detector traces. A separation of at least 0.5 inches is sufficient. Even in multilayer designs, logic traces When using a two-layer circuit board, one layer should be should not run below the detector traces; the detector lines dedicated to routing the detector lines in a surrounding ground are only several millivolts in amplitude. A high speed logic plane while the second layer should be dedicated to a local line can easily cause noise-induced data errors through bad ground plane under the detector signals. Therefore, not only layout. does the ground plane physically isolate the detector signals from the other board signals, but it isolates them electrically Third, the X and Y coil drive input traces to the MBM should as well. This is shown in Figure 4. be separated from the detector signals by as much as pos­ sible. The coil drive signals carry large currents and are The ideal four-layer circuit board uses quite a different ap­ switched at 50KHz frequencies. The switching transients proach. By routing the detector traces in a ground plane can induce noise unless the coil drive signals are routed surrounded above and below by other ground planes, a correctly; by separating these signals from the detector out­ "pseudo-coaxial" shield is formed around the low-level sig­ put signals, the circuit board designer can decrease the nals from the MBM, as shown in Figure 5. However, in some amount of noise induced onto the detector outputs. designs this method may become too space- and layout­ intensive to use on a multi-layer board. In these cases, one The X and Y coil drive input traces from the 7254 drive of the ground planes can be substituted with one of the DC transistor sets to the X and Y coils contained within the MBM power planes.
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