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Matrox MGA-G400 Specification

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Matrox MGA-G400 Specification Matrox Graphics Inc. Matrox MGA-G400 Specification Document Number 10617-MS-0101 June 2, 1999 Trademark Acknowledgements MGA,™ MGA-G400,™ MGA-1164SG,™ MGA-2064W,™ MGA-2164W,™ MGA-VC064SFB,™ MGA-VC164SFB,™ MGA Marvel,™ MGA Millennium,™ MGA Mystique,™ MGA Rainbow Runner,™ MGA DynaView,™ PixelTOUCH,™ MGA Control Panel,™ and Instant ModeSWITCH,™ are trademarks of Matrox Graphics Inc. Matrox® is a registered trademark of Matrox Electronic Systems Ltd. VGA,® is a registered trademark of International Business Machines Corporation; Micro Channel™ is a trademark of International Business Machines Corporation. Intel® is a registered trademark, and 386,™ 486,™ Pentium,™ and 80387™ are trademarks of Intel Corporation. Windows™ is a trademark of Microsoft Corporation; Microsoft,® and MS-DOS® are registered trademarks of Microsoft Corporation. AutoCAD® is a registered trademark of Autodesk Inc. Unix™ is a trademark of AT&T Bell Laboratories. X-Windows™ is a trademark of the Massachusetts Institute of Technology. AMD™ is a trademark of Advanced Micro Devices. Atmel® is a registered trademark of Atmel Corporation. Catalyst™ is a trademark of Catalyst Semiconductor Inc. SGS™ is a trademark of SGS- Thompson. Toshiba™ is a trademark of Toshiba Corporation. Texas Instruments™ is a trademark of Texas Instruments. National™ is a trademark of National Semiconductor Corporation. Microchip™ is a trademark of Microchip Technology Inc. All other nationally and internationally recognized trademarks and tradenames are hereby acknowledged. This document contains confidential proprietary information that may not be disclosed without written permission from Matrox Graphics Inc. © Copyright Matrox Graphics Inc., 1997. All rights reserved. Disclaimer: Matrox Graphics Inc. reserves the right to make changes to specifications at any time and without notice. The information provided by this document is believed to be accurate and reliable. How- ever, no responsibility is assumed by Matrox Graphics Inc. for its use; nor for any infringements of pat- ents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Matrox Graphics Inc. or Matrox Electronic Systems Ltd. Contents Chapter 1: MGA Overview 1.1 Introduction. 1-2 1.1.1 Supported Multimedia Features . 1-3 1.2 System Block Diagram . 1-3 1.3 Chip Specifications. 1-4 1.3.1 Performance Characteristics and Key Features . 1-4 1.3.2 2D Drawing Engine . 1-5 1.3.3 3D Rendering Engine . 1-5 1.3.4 Video and Multimedia Features . 1-6 1.4 Typographical Conventions Used. 1-9 1.5 Locating Information. 1-9 Chapter 2: Resource Mapping 2.1 Memory Mapping . 2-2 2.1.1 Configuration Space Mapping. 2-2 2.1.2 MGA General Map . 2-3 2.1.3 MGA Control Aperture . 2-4 2.2 Register Mapping . 2-5 Chapter 3: Register Descriptions 3.1 Power Graphic Mode Register Descriptions. 3-2 3.1.1 Power Graphic Mode Configuration Space Registers . 3-2 3.1.2 Power Graphic Mode Memory Space Registers. 3-31 3.2 VGA Mode Register Descriptions. 3-288 3.2.1 VGA Mode Register Descriptions . 3-288 3.3 DAC Registers . 3-367 3.3.1 DAC Register Descriptions . 3-367 Chapter 4: Programmer’s Specification 4.1 HOST Interface. 4-2 4.1.1 Introduction . 4-2 4.1.2 PCI Retry Handling . 4-3 4.1.3 PCI Burst Support . 4-3 4.1.4 PCI Target-Abort Generation . 4-4 4.1.5 Transaction Ordering . 4-4 4.1.6 Direct Access Read Cache . 4-5 4.1.7 Big-Endian Support. 4-5 4.1.8 Host Pixel Format . 4-9 4.1.9 Programming Bus Mastering for DMA Transfers . 4-12 4.2 Memory Interface . 4-19 Contents 1 4.2.1 Frame Buffer Organization . .4-19 4.2.2 Pixel Format. .4-21 4.3 Chip Configuration and Initialization . 4-23 4.3.1 Reset . .4-23 4.3.2 Operations After Hard Reset . .4-23 4.3.3 Power Up Sequence . .4-24 4.4 Direct Frame Buffer Access . 4-28 4.5 Drawing in Power Graphic Mode . 4-29 4.5.1 Drawing Register Initialization Using General Purpose Pseudo-DMA4-29 4.5.2 Overview . .4-30 4.5.3 Global Initialization (All Operations). .4-31 4.5.4 Line Programming . .4-31 4.5.5 Trapezoid / Rectangle Fill Programming . .4-36 4.5.6 Sub-Pixel Trapezoids. .4-54 4.5.7 Bitblt Programming . .4-58 4.5.8 ILOAD Programming . .4-62 4.5.9 Loading the Texture Color Palette. .4-68 4.6 CRTC Programming . 4-70 4.6.1 Horizontal Timing. .4-70 4.6.2 Vertical Timing. .4-71 4.6.3 Memory Address Counter . .4-72 4.6.4 Programming in VGA Mode. .4-73 4.6.5 Programming in Power Graphic Mode. .4-74 4.7 Video Interface . 4-79 4.7.1 Operation Modes . .4-79 4.7.2 Palette RAM (LUT) . .4-80 4.7.3 Hardware Cursor . .4-81 4.7.4 Keying Functions . .4-81 4.7.5 Zooming. .4-82 4.7.6 Feature Connector. .4-82 4.7.7 Test Functions . .4-85 4.7.8 Clock Generator Circuit . .4-86 4.8 Video Input Interface . 4-94 4.8.1 Overview of the Video-Grabber . .4-94 4.8.2 MAFC Mode Selection. .4-94 4.8.3 Vertical Blanking and VBI Count . .4-94 4.8.4 Capture Modes / C-Cube Compatibility . .4-95 4.8.5 UYVY and YUY2 Formats . .4-98 4.8.6 Task Based VBI Detection. .4-98 4.8.7 Field/Task Generated Interrupts . .4-98 4.8.8 Horizontal Downscaling by 1/2 . .4-99 Contents 2 4.8.9 Feedback Path from Second CRTC . 4-99 4.8.10 Maximum Height Definition . 4-99 4.8.11 Programming Sequence . 4-99 4.8.12 Programming Table . 4-100 4.9 CODEC Interface . 4-101 4.9.1 Memory Organization . 4-101 4.9.2 Command Execution. 4-102 4.9.3 Output mode . 4-106 4.9.4 CODEC Interface RESET to IDLE Procedure . 4-107 4.9.5 Recovery Width Programming . ..
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