Mitigation of Cold Boot Attack Using an Encrypted Memory Controller IIIT

Mitigation of Cold Boot Attack Using an Encrypted Memory Controller Student Name: Preet Kaur Walia IIIT-D-MTech-ECE-VLSI-14-16 July 10, 2016 Indraprastha Institute of Information Technology New Delhi Advisor Mohammad S. Hashmi Submitted in partial fulfillment of the requirements for the Degree of M.Tech. in Electronics and Communication, with specialization in VLSI and Embedded Systems c 2016 Preet Kaur All rights reserved Certificate This is to certify that the thesis titled “Mitigation of Cold Boot Attack Using an En- crypted Memory Controller" submitted by Preet Kaur Walia for the partial fulfillment of the requirements for the degree of Master of Technology in VLSI & Embedded Systems is a record of the bonafide work carried out by him under my guidance and supervision in the Se- curity and Privacy group at Indraprastha Institute of Information Technology, Delhi.This work has not been submitted anywhere else for the reward of any other degree. Dr. Mohammad S. Hashmi Indraprastha Institute of Information Technology, New Delhi i Abstract RAMs which are widely used in PCs and laptops are likely to break the popular supposition that data in them is lost whenever power supply is cut down. It has been proved in 2008 by a group of researchers that RAMs are no longer volatile in nature. The data remanence behaviour of DRAMs have allowed to retrieve memory contents when the power has been switched off by an attack known as cold boot attack. In cold boot attack, memory can be frozen using a refrigerant and then removed from the computer. It is then quickly placed into a specially designed system that reads out its content, targeting encryption keys and other sensitive information. Also, the standard mechanisms for protecting sensitive data on laptops, smartphones, PCs and Macs is no longer safe and secure. Several design practices have been discussed in the thesis which are being adopted to mitigate such attacks. Mitigation of Cold Boot Attack by providing encryption support in the memory controller is a promising technique which has been proposed in the thesis. The proposed memory security model protects digital content and software stored in untrusted system memory from physical tamper. The thesis introduces a set of architecture innovations that aim for the implementation of the proposed security model. Further, a new key storage mechanism is proposed. Also, analysis on the overhead occurred due to the adoption of this scheme has been discussed. ii Acknowledgments Towards the end of my M.Tech. degree, I would like to pay my gratitude to several individuals who contributed from various perspectives. First of all, I would like to express my profound gratitude to my thesis supervisor, Dr. Mohammad S. Hashmi for his support, direction and motivation all along the way. He has been a great source of inspiration for me. I would like to thank the director Dr. Pankaj Jalote and all my professors at IIITD for providing a positive learning atmosphere to work. I also take this opportunity to express a deep sense of gratitude towards Mr. Arpan Jati for his support and encouragement for conquering every hurdle that I have encountered throughout the process. My regards to Ravneet Saluja and all my friends at IIIT-D who made this journey a wonderful one. Last but not the least; I would like to thank my Parents for supporting me spiritually and emotionally. iii Contents Certificate . .i Abstract . ii Acknowledgements . iii List of Figures . .v List of Tables . vii 1 Introduction 1 1.1 Motivation and Objective . .1 1.1.1 Execution of attack . .2 1.1.2 Reading the contents of memory . .3 1.1.3 Keys Regeneration . .4 1.1.4 Existing Solutions . .4 1.2 Terminologies . .5 1.3 Outline . .5 2 Preliminaries 7 2.1 Introduction . .7 2.2 AXI bus . .7 2.2.1 Channel Handshaking . .8 2.2.2 Channels . .8 2.2.3 Communication between AXI channels . 10 2.2.4 Dependencies between different handshake signals are discussed . 12 2.3 Memory Controller Block . 13 2.3.1 Memory controller block functional view . 14 2.3.2 MCB operation . 15 2.3.3 Command Signals . 16 2.3.4 Write Signals . 17 2.3.5 Read Signals . 19 iv 2.4 Advanced encryption Algorithm . 20 3 Proposed Work 22 3.1 Introduction . 22 3.2 Memory Encryption based a novel design methodology . 22 3.2.1 Architectural View . 22 3.2.2 Design Model . 24 3.2.3 Implementation and Results . 26 3.2.4 Project on ISE . 30 3.2.5 Testing of AES module . 32 3.2.6 Modifications in the existing Xilinx architecture . 33 3.3 Analysis . 33 4 Conclusion and Future Work 34 4.1 Conclusion . 34 4.2 Future work . 34 v List of Figures 1.1 Inverted can of compressed air . .2 2.1 Read channel . 11 2.2 Read Burst . 11 2.3 Write channel . 12 2.4 Write Burst . 12 2.5 Read Handshake Dependencies . 13 2.6 Write Handshake Dependencies . 13 2.7 Memory controller block functional view . 14 2.8 Command Path Timing(Write) . 17 2.9 Loading the Write Data FIFO . 18 2.10 Entering the Write Request into Command FIFO . 18 2.11 Entering the Read Request into Command FIFO . 19 2.12 Read Data Returning from the Memory Device . 20 2.13 Transferring Read Data into FPGA Logic . 20 2.14 AES Algorithm . 21 3.1 Read-Write(General approach) . 23 3.2 Write Request . 23 3.3 Read Request . 24 3.4 Design Model (Write) . 25 3.5 Design Model (Read) . 26 3.6 Xilinx processor architecture . 27 3.7 Write scenario . 28 3.8 Read Scenario . 28 3.9 Sequence Diagram showing algorithm adopted . 29 3.10 Delay in Write Channel . 29 3.11 Delay in Read Channel . 30 vi 3.12 DDR Interface . 31 3.13 MCB Read path timing . 31 3.14 MCB Write path timing . 32 3.15 AES encryption timing diagram . 32 4.1 Key Storage . 35 vii List of Tables 1.1 Test system used experiment . .3 1.2 Effect of cooling on error rates . .3 2.1 Read Data Channel Signals . .8 2.2 Address Read Channel Signals . .9 2.3 Write Data Channel Signals . .9 2.4 Address Write Channel Signals . 10 2.5 Write Response Channel Signals . 10 2.6 MCB Instructions and codes . 15 2.7 Command Path Signals . 16 2.8 Write Datapath Signals . 17 2.9 Read Datapath Signals . 19 3.1 Performance Analysis . 33 viii Chapter 1 Introduction Security is a vital concern for everyone in day to day life. Information Security is a problem being faced by modern organizations considering, many organizations today are fully dependent on information technology for survival. The increasing variety of threats and fierceness of cyber- attacks has made protecting information a complex challenge. As the records show, between 2002 and 2007, 773 breaches of US organizations were reported with a total of 267 million private records lost. Over 42% of these breaches were a result of lost or stolen hardware including laptops, PDAs and portable memory devices [1]. To exploit data sensitivity, many attacks have been innovated and explored. Some of them include Bus snooping, DMA fire-wire attack and Cold boot attack. Cold boot attack is an attack developed by researchers in Princeton University in 2008 which is of high concern. Many solutions have been developed to prevent and counter attack in such situations. Three general approaches include complex hardware.

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