Emerging Non-Volatile Storage Memories

IBM Research

Emerging Non-volatile Storage Memories

Gian-Luca Bona

gianni@us.ibm.com IBM Research, Almaden Research Center

Outline

Emerging Non-volatile Storage Memory Examples - Phase Change Memory - Polymer-based Charge Storage Memory - Storage Probe Memory - Magnetic Shift Register Memory

Summary & Conclusion: Expected Advances in Solid State Storage Technology

SL m+1 SL m

SL m-1

WL n-1

WL n

WL n+1

Everyone is looking for a dense (cheap) crosspoint memory. It is relatively easy to identify materials that show bistable hysteretic behavior (easily distinguishable, stable on/off states).

The Nonvolatile Memory Landscape More new non-volatile memory technologies under development today than at any time in history 2 reasons

Year 03 04 05 06 07 08 09 Flash 107 90 80 70 65 57 50 Technology node (nm) Flash NOR 9-10 8.5- 8.5- 8-9 8-9 8-9 8-9 tunnel oxide 9.5 9.5 thickness (nm)

Manufacturing solution exist ITRS 2004 Manufacturing solution is known Manufacturing solution is NOT known

Scaling: Oxide thickness will Explosive market growth reach limit very soon Diversified applications

© 2005 IBM Corporation IBM Research Non-volatile Storage Memory Storage Class Memory (SCM): Key Features: • Much faster to write small blocks than Flash, HDD • Less expensive than Flash • More rugged than HDD • Lower standby power than HDD SCM Specs:

Access Time <2.5 us

Data Rate (MB/s) 100 DRAM Endurance 1012 1.E+05 SCM -4 HER (/TB) 10 1.E+03 HDD MTBF (MH) 2 1.E+01 Tape On Power (mW) 100

1.E-01 (IOPS) Performance Standby (mW) 1 1.E+01 1.E-01 1.E-03 1.E-05 1.E-07 1.E-09 Cost ($/GB) <5.5 Access Time (s) CGR 35%

IOPS vs Access Time and Data Rate @ 4kB IO DRAM

1,000,000

100,000 SCM

10,000 HDD 5-6100K-1M 4-510K-100K IOPS 1,000 3-41K-10K 2-3100-1K NAND 1-210-100 100 (read) 0-1

4096 10 NAND Data Rate 256 (write) (MB/Sec) 1 16 3.9 250 62.5 15.6 0.98 0.24 4000 1000 0.061 0.015 16000 Access Time (uS)

Example: Phase Change Solid State Memory (PCM) Writing: transition from crystalline to amorphous phase by melting and fast cooling (10 ns) in GST-material (GeSbTe)

Erase: heating over Tcryst and slow cooling (10-100 ns) Read: Measure R at low current Companies report contact pore or line diameter as small as 50 nm Most materials characterization is done on blanket films Need to investigate properties of nanostructure to study scaling

write

Tmelt erase Tcryst crystalline temperature amorphous

M. H. R Lankhorts et al., S. L. Cho et al., Samsung, time Philips, Nature Mat. 4 (2005) 347 2005 Symp. On VLSI Technol.

SEM of GST nanostructures

Scanning electron microscope Scanning electron microscope image of 200 nm square GST patterns. image of 65 nm round GST patterns.

• Fabricated nanostructures of variable sizes from GST and 65 nm diameter from GeSb • Measured crystallization temperature as a function of structure size (for details see S. Raoux et al., Collaboration IBM, Macronix & Infineon, Sep. 2005, www.epcos.org ) © 2005 IBM Corporation Crosspoint PCM devices

Test arrays: defined by e-beam @ ARC ARC Material focus & fast prototyping: Substantial improvements:

-> TG, Tcryst -> fast switching, a few ns -> min. cell size: >=65nm

Devices

>108 switching cycles shown Collaboration IBM, Macronix & Infineon 8” Prototyping at MRL Watson Example: ‘Nanotrap’ Memory

• Polymer-based Charge Storage Cross- point Memory First Alq3 layer Granular Al or Au • Wide band-gap organic semiconductor containing ... • Layer of metallic nanoparticles • Between metal electrodes

Metal electrodes: Al ( 50nm) Granular metal: Al (5 nm)

Charge transport medium:Alq3 (50 nm)

FIB SEM by V. Deline Response of Nanotrap Memory Element

• Region I Al/Alq3/Al/Alq3/Al 100 – Bistable V max – ON and OFF states ON retained for > 1 year -2

) 10 2 – Pulse to Vmax to turn ON V min – Pulse to Vmin to turn OFF -4

10 REGION II V th • Region II -6 OFF 10 – Negative differential Current Density (A/cm Density Current resistance REGION I REGION III 10-8 – Increasing charge on 0246810 Voltage (V) particles

• Region III L. D. Bozano et al. Appl. Phys Lett., 2004 – Normal current flow IBM Research Example:“MILLIPEDE” Probe Storage “MILLIPEDE” SCANNER MICROMECHANICAL DATA STORAGE shuttle

permanent magnet (on shutte) movable table for storage fixed coil medium (6.5 x 6.5 mm)

parallelization Lever beam Electronic Cell CMOS Chip Coil Magnet Scanner Lever pivot spring system frame Interconnect

Bonding Pad Spacer read resistor write resistor Base Plate Interconnect

THERMOMECHANICAL RECORDING tip capacitive platform hinge 100 nm

1.14 Tbit / in2 500500 nmnm

641 Gbit / in2 500500 nmnm

LEVER ARRAY 410 Gbit / in2 500500 nmnm

Small-scale Storage Prototype MEMS Assembly Microscanner Small-scale storage prototype comprises: MEMS assembly in form factor (2D array/microscanner/thermal sensors) Readback electronics in non-form factor (parallel operation of up to 8 levers) Navigation/servo system Microcontroller for controlling all functions of Cantilever array prototype storage system

Data controller / ECC

– Compact Flash Interface – 512 byte sector size – 4 RS codeword per sector, 4-way interleaved – Encoder/Decoder RS (151,129) – (1,7) modulation Encoder/Decoder

Breaking the Terabit / in2 Barrier

2 Bit-pitchAreal = Density 13 nm Track-pitch1.217 Tbits/in = 27 nm Bit pitch 13.3 nm, Track pitch 26.6 nm

Single Lever Test-stand Data Set Size > 300 K bits

−4 Criterion: raw 10 bit-error-rate < 10-4

• Conclusion: Thermomechanical recording Track pitch: 26.6 nm achieves 1.2 Tbit/in2 in a On-track min. indent spacing: 26.6 nm stringent, industry-standard BIT-ERROR RATE BIT-ERROR Modulation code d=1 areal density demonstration

−5 • cf. Magnetic recording: 10 2 1300 1200 1100 1000 900 800 < 250 Gbit/in 2 AREAL DENSITY (Gb/in2)

Summary: Storage Probe Memory ‘Millipede’ Demonstration of small-scale prototype storage system with servo navigation and parallel read/write/erase capability using nano-scale probe-storage technology

First time a scanning-probe recording technology has reached this level of technical maturity demonstrating joint operation of all building blocks of a storage device

Challenges/open questions: - Tracking of multiple probes at sub-nanometer resolution - Optimization of tip/medium interaction - Optimal tradeoff between number of tips, data rate, and power consumption - Dependence of device operation on environmental conditions - System level reliability not yet assessed

2D Cantilever Arra y on CMOS Chip

Storage media on xy scanner

Storage-Class Memory: Example: Magnetic Race-track

Philosophy Æ Want a solid-state memory with no moving parts which is very cheap and of moderate to high performance Main approaches Æ Make extremely small cells Requires significant engineering developments Current roadmaps suggest that F<45nm will be possible within 5 years, thus making this approach extremely challenging Æ Access multiple bits from one set of logic Similar philosophy used in conventional storage drives and in millipede However we want a solid state memory with no moving parts Recent developments in magnetic materials makes this approach viable and attractive by storing information in domain walls (spatially varying order parameter in homogeneous material) Æ Lots of new science: Spin currents and torque, domain wall fringing fields

∂θ ∂φ Current Æ torque on DW ≠ 0, = 0 Massless motion!! ∂∂tt ∂θ ∂φ (Magnetic field Æ pressure on DW, ≠ 0, ≠ 0 ) From Sadamichi Maekawa ∂∂tt

Magnetic Race-track Memory

A novel three-dimensional spintronic storage class memory The capacity of a hard disk drive but the reliability and performance of solid state memory - a disruptive technology based on recent developments in spintronic materials and physics Parkin, US patents 6834005, 6898132, 6920062 ÆCurrent pulses move domains along “racetrack” shift register ÆTMR sensor to read bit pattern ÆSpecial current pulse-driven element to re-write a bit

Magnetic Racetrack Memory: writing mechanism

ÆWriting a bit – current pulse on special write element

Parkin, US patents 6834005, 6898132, 6920062

Magnetic Shift Register Memory

ÆMagnetic race-tracks can be connected in series ÆMany other configurations possible

IBM © 2005 IBM Corporation IBM Research Magnetic Race-Track Memory: Domain-Wall Magnetic Shift Register domain Information stored as domain walls in wall vertical “race track” Reading and writing carried out along bottom of race track Alternating layers of Electronics built under race track using two ferromagnetic materials to pin conventional CMOS domain walls Domains moved around track using nano second long pulses of current

- Data stored in the third dimension in tall columns of magnetic material - Domains “race” around track for reading and writing - 10 to 100 times the storage capacity of conventional solid state memory - Could displace flash memory and hard disk drives for many applications

Expected Advances in Solid State Storage Technology

Storage Class Memories (SCM): cost, scaling and density matters – Various cheap, non-volatile memories (SCM) are under development. If successful, they can displace flash first … Maturing and will be on market in a few years: – Phase Change Memory (PCM) – advanced demonstrations in and most mature in Samsung, Intel, …. Effort in IBM, partnership with Infineon, Macronix – MRAM - > – Scaling demonstrations pursued to 45nm in MRAM and PCM Exploratory: – Polymer (charge storage), Magnetic Shift Register (domain wall motion), Probe Storage ‘Millipede’, Perovskite (resistance change), Advancements in low cost manufacturing is key – Nanoimprint Lithography (stamping), Self-assembly, … – Multiple bits per cell, Multiple cell layers per chip