Part 2 – Data Communication
Reliability and Channel Coding
Gail Hopkins
Part 2 – Data Communication
Introduction
Types of error that can occur during transmission Techniques used to control errors
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Transmission Errors
Much of the complexity of networks arises from susceptibility to interference that can cause: transmitted data to be lost or changed random data to appear Single-bit errors versus burst errors Errors also caused by equipment failures or equipment operating below standard Small errors in transmission are harder to detect than complete failures!
Part 2 – Data Communication
Categories of Error
Interference E.g. EM radiation from other devices Distortion Physical systems distort signals Wires have capacitance and inductance – blocks signals at some frequencies Attenuation Weakening of signal with distance
2 Part 2 – Data Communication Tradeoffs with Error Detection/Correction Error detection adds overhead Designers need to decide whether to use error detection or not Consider a single bit error Not important for image transmission Could be hugely important for a bank transfer!
Part 2 – Data Communication
Errors and their Causes
Type of Error Description Single Bit Error Single bit in a block of bits is changed. All other bits in the block are unchanged. Often due to very short- duration interference. Burst Error Multiple bits in a block of bits are changed. Often due to longer-duration interference. Erasure (Ambiguity) The signal that arrives at a receiver is ambiguous – i.e. doesn’t clearly correspond to either a logical 1 or logical 0. Can result from distortion or interference.
From Comer, 2009
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Handling Channel Errors
Channel coding – two schemes: Forward Error Correction (FEC) mechanisms Add additional information to the data to allow the receiver to check if it is correct Allow receiver to detect when an error has occurred, which bits have changed and compute correct values (some techniques). E.g. Single Parity Bit Checking, Row and Column (RAC) Parity, Checksums, Cyclic Redundancy Check (CRC) Automatic Repeat reQuest (ARQ) mechanisms Use acknowledgement messages to check whether data has arrived at its destination Requires cooperation of sender and receiver
Part 2 – Data Communication Single Parity Bit Checking Count number of 1 bits in the data and add an extra parity bit to make this odd or even even parity - parity bit is set so that total number of 1s is even - 1011001 => parity bit 0 odd parity - total 1s should be odd - 1011001 => parity bit 1 Transmitter calculates and adds, receiver calculates and checks Introduces additional costs Only detects limited types of errors Cannot correct errors
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Even Parity Checking
The total number of bits with value 1 must be even Value of parity bit chosen to make this so Examples: Character: Parity Bit: (set by sender) 0110100 1 1001000 0 1011000 1 1011101 1
Part 2 – Data Communication
Odd Parity Checking
The total number of bits with value 1 must be odd Value of parity bit chosen to make this so Examples: Character: Parity Bit: (set by sender) 0110100 0 1001000 1 1011000 0 1011101 0
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Example Failure of Parity Checking
Errors that change an even number of bits:
0100101 1 0101001 1 0100101 1 0111101 1 0100101 1 0000001 1
Part 2 – Data Communication Row and Column (RAC) Parity Checking Parity 1 0 1 1 1 for each row Bits from 0 0 1 0 1 dataword 1 0 1 0 0 Parity 0 0 1 1 0 for each column
Single bit Sent changed during 1 0 1 1 1 transmission Locations 0 1 1 0 1 where calculated 1 0 1 0 0 parity bits disagree, 0 0 1 1 0 indicating the row and column Received of the error
6 Part 2 – Data Communication Row and Column Parity Checking (2) A bit error will cause two calculated parity bits to disagree with the bit received Identifies exact position due to row and column parity bits Allows receiver to correct the data bit Can only correct single-bit errors If more bits changed, can detect an odd number of errors
Part 2 – Data Communication
Other Error Detection Methods
Other methods include checksums and cyclic redundancy checks These can be compared according to: amount of extra data to be transmitted amount of extra computation involved types of errors that are detected Note the difference between detecting that an error occurred and knowing how to fix it
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Checksums
Interpret the data as if it were a sequence of integers and add them together to get an integer result called a checksum Add in any carry bits too Append the checksum to the frame 16 and 32 bit checksums are common and are usually computed for a whole packet
Part 2 – Data Communication
Example Checksum
H e l l o w o r l d . 48 65 6C 6C 6F 20 77 6F 72 6C 64 2E
4865 + 6C6C + 6F20 + 776F + 726C + 642E + carry = 71FC
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Evaluation of Checksums
Data overhead - 16 or 32 bits Computational overhead - simple additions Undetected errors - some periodic reversal of bits (e.g., reversing one bit in each of four data items)
Part 2 – Data Communication
Example Failure of Checksums
data item checksum data item checksum (binary) value (binary) value 0 0 0 1 1 0 0 1 1 3 0 0 1 0 2 0 0 0 0 0 0 0 1 1 3 0 0 0 1 1 0 0 0 1 1 0 0 1 1 3 totals 7 totals 7
9 Part 2 – Data Communication Cyclic redundancy checks (CRCs)
Detects more errors than checksums and only requires simple hardware Can be analysed mathematically but is best presented in terms of the hardware design
Part 2 – Data Communication
Overview of CRC Uses binary division instead of addition Sender wants to send D, a piece of data d bits long Sender and receiver agree a generator, G, a bit pattern that is r + 1 bits long Sender appends R (an additional sequence of r bits) to D so that the resulting sequence is exactly divisible by G using binary (modulo 2) arithmetic Receiver divides the received bit pattern by G and checks whether the remainder is 0
10 Part 2 – DataPacket Communication Transmission
d bits r bits
D: Data bits R: CRC bits
Can detect burst errors of less than r +1 bits and odd number of bit errors Can detect burst errors of length greater than r + 1 with probability 1 – 0.5r
Part 2 – Data Communication
CRC - Hardware Components
a b out out a 0 0 0 0 1 1 b 1 0 1 1 1 0 (a) (b)
Exclusive or (xor) unit
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CRC - Hardware Components (2)
shift register shift register 1 1 0 1 1 0 1 1 0 0 1 1 0 1
output value to be output input value shifted in changes shifts in (a) (b)
Shift register
Part 2 – Data Communication CRC - Combining Components
Combine 3 shift registers and 3 xor units Initialise registers and then feed in the bits of the message one at a time Final state gives the CRC - calculated by both the transmitter and receiver
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
input 10
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Why do CRCs work?
Mathematical analysis is beyond our scope Intuition each single bit of the message dramatically affects the whole CRC (feeds into three places) the effect of each bit loops through the process several times (the registers are connected into a cycle)
Part 2 – Data Communication
Evaluation of CRCs
Data overhead - 16 or 32 bits Computational overhead - low - combines simple hardware devices Can be applied to an arbitrary length message Types of errors - good for burst errors - changes to several bits in one location that may be caused by a sudden interference (e.g. by lightening)
13 Part 2 – Data Communication Automatic Repeat reQuest (ARQ) Mechanisms Sender and receiver communicate metainformation Sender sends data Receiver sends acknowledgement (ack) message back When sender receives ack, it knows original data arrived correctly If no ack after a timeout, sender retransmits copy of original data
Part 2 – Data Communication
ARQ (2)
Good for when underlying system detects error but when underlying system doesn’t correct it Can be used to add guarantees to delivery
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Summary
Types of errors Single bit, burst errors, erasure Mechanisms for detection of errors Single parity bit, Row and Column parity bit, Checksums, CRC ARQ – for retransmission when messages are lost Reading: Chapter 8, Computer Networks and Internets, Comer, 5th Edition, 2009
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