DOCSLIB.ORG

Exploring Performance Portability for Accelerators Via High-Level Parallel Patterns

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Exploring Performance Portability for Accelerators Via High-Level Parallel Patterns Exploring Performance Portability for Accelerators via High-level Parallel Patterns Kaixi Hou Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science and Application Wu-chun Feng, Chair Calvin J. Ribbens Hao Wang Yong Cao Gagan Agrawal May 2, 2018 Blacksburg, Virginia Keywords: Parallel Patterns, Vector Processing, SIMD, Parallel Accelerators, Multi-core, Many-core, DSL, Algorithmic Skeleton Copyright 2018, Kaixi Hou Exploring Performance Portability for Accelerators via High-level Parallel Patterns Kaixi Hou (ABSTRACT) Parallel computing dates back to the 1950s-1960s. It is only in recent years, as various parallel accelerators have become prominent and ubiquitous, that the pace of parallel computing has sped up and has had a strong impact on the design of software/hardware. The essence of the trend can be attributed to the physical limits of further increasing operating frequency of processors and the shifted focus on integrating more computing units on one chip. Driven by the trend, many commercial parallel accelerators are available and become commonplace in computing systems, including multi-core CPUs, many-core GPUs (Graphics Processing Units) and Intel Xeon Phi. Compared to a traditional single-core CPU, the performance gains of parallel accelerators can be as high as many orders of magnitude, attracting extensive interest from many scientific domains. Nevertheless, it presents two main difficulties for domain scientists and even expert developers: (1) To fully utilize the underlying computing resources, users have to redesign their applications by using low-level languages (e.g., CUDA, OpenCL) or idiosyncratic intrinsics (e.g., AVX vector instructions). Only after a careful redesign is carried out can efficient kernels be written. (2) These kernels are oftentimes specialized and in turn imply that as far as the performance is concerned, the codes might be not portable to a new given architecture, leading to more tedious and error-prone redesign. Parallel patterns, therefore, can be a promising solution in lifting the burdens from pro- grammers. The idea of parallel patterns attempts to build a bridge between target algorithms and parallel architectures. There has already been some research on using high-level languages as parallel patterns for programming on modern accelerators, such as ISPC, Lift, etc. However, the existing approaches fall short from efficiently taking advantage of both parallelism of algorithms and diversified features of accelerators. For example, by using such high-level languages, it is still challenging to describe the patterns of the convoluted data-reordering operations in sorting net- works, which are oftentimes treated as building blocks of parallel sort kernels. On the other hand, compilers or frameworks lack the capability and flexibility to quickly and efficiently re-target the parallel patterns to another different architectures (e.g., what types of vector instructions to use, how to efficiently organize the instructions, etc.). To overcome the aforementioned limitations, we propose a general approach that can create an effective and abstracted layer to ease the generating efficient parallel codes for given algorithms and architectures. From algorithms to parallel patterns, we exploit the domain expertise to ana- lyze the computational and communication patterns in the core computations and represent them in DSL (Domain Specific Language) or algorithmic skeletons. This preserves the essential informa- tion, such as data dependencies, types, etc., for subsequent parallelization and optimization. From parallel patterns to actual codes, we use a series of automation frameworks and transformations to determine which levels of parallelism can be used, what optimal instruction sequences are, how the implementation changes to match different architectures, etc. In this dissertation, we present our approaches by investigating a couple of important computational kernels, including sort (and segmented sort), sequence alignment, stencils, etc., across parallel platforms (CPUs, GPUs, Intel Xeon Phi). Through these studies, we show: (1) Our automation frameworks use DSL or algo- rithmic skeletons to express parallelism. (2) Generated parallel programs take into consideration of both parallelism of the target problems and characteristics of underlying hardware. (3) Evalu- ations are discussed on the portable performance and speedups over the state-of-the-art optimized codes. Besides, for some problems, we also propose novel adaptive algorithms to accommodate the parallel patterns to varying input scenarios. Exploring Performance Portability for Accelerators via High-level Parallel Patterns Kaixi Hou (GENERAL AUDIENCE ABSTRACT) Nowadays, parallel accelerators have become prominent and ubiquitous, e.g., multi-core CPUs, many-core GPUs (Graphics Processing Units) and Intel Xeon Phi. The performance gains from them can be as high as many orders of magnitude, attracting extensive interest from many scientific domains. However, the gains are closely followed by two main problems: (1) A complete redesign of existing codes might be required if a new parallel platform is used, leading to a nightmare for developers. (2) Parallel codes that execute efficiently on one platform might be either inefficient or even non-executable for another platform, causing portability issues. To handle these problems, in this dissertation, we propose a general approach using parallel patterns, an effective and abstracted layer to ease the generating efficient parallel codes for given algorithms and across architectures. From algorithms to parallel patterns, we exploit the domain expertise to analyze the computational and communication patterns in the core computations and represent them in DSL (Domain Specific Language) or algorithmic skeletons. This preserves the essential information, such as data dependencies, types, etc., for subsequent parallelization and optimization. From parallel patterns to actual codes, we use a series of automation frameworks and transformations to determine which levels of parallelism can be used, what optimal instruction sequences are, how the implementation change to match different architectures, etc. Experiments show that our approaches by investigating a couple of important computational kernels, including sort (and segmented sort), sequence alignment, stencils, etc., across various parallel platforms (CPUs, GPUs, Intel Xeon Phi). ACKNOWLEDGEMENTS First of all, I would like to thank my advisor Prof. Wu-chun Feng, who provides me invaluable knowledge and insights on research, communication skills, and introduces me into the world of academia. I have learned so much from Dr. Feng: how to read/write research papers, how to express my idea briefly and deliver a good presentation, how to establish productive collaboration with others, etc. Without Wu’s guidance and support, I would have never reach where I am now. Next, I would like to thank my other committee members: Prof. Calvin J. Ribbens, Dr. Hao Wang, Dr. Yong Cao, and Prof. Gagan Agrawal. I appreciate all their insightful comments and feedback on my dissertation, as well as their precious time they put into serving at various stages of my Ph.D. journey. Special thanks go to Dr. Hao Wang for working closely with me on many research projects and providing me with great suggestion and helpful advise on strengthening my research capability. I have been fortunate to work with many researchers from other research institutes. I am grateful to Shuai Che (AMD research) for his guidance on the GPU project to accelerate graph algorithms. My thanks also go to Jonathan Gallmeier (AMD research) for the technical discus- sions on how to efficiently utilize different GPU platforms. I am indebted to Seyong Lee, Jeffrey Vetter, and Mehmet Belviranli (Oak Ridge National Lab), for the extended brainstorming discus- sions on GPU-based wavefront problems. I would also like to thank Weifeng Liu (University of Copenhagen) for sharing his knowledge and experience on GPU computing. I also want to share my gratitude to the wonderful people around me throughout these years. I am so fortunate to have Jing Zhang, Xiaodong Yu, Xuewen Cui, Da Zhang as my lab colleagues during my Ph.D. I cannot forget the many “pizza” nights that we spent on the submission deadlines. Special thanks go to my roommates, Fang Liu, Yao Zhang, and Jinxing Wang/Libei Huang couple, at different stages of my Ph.D. I would like to thank the following people who make my life colorful and entertaining in this “isolated” Blacksburg: Bo Li/Yao Wang couple, Hao Zhang, Yue Cheng, Sichao Wu, Liangzhe Chen, Qianzhou Du, Xiaokui Shu, Ji Wang, Run Yu, Mengsu Chen. My best wishes to all of you for the future endeavors. Finally, I am immensely grateful to my family back in China: my parents, Jianjun Hou and v Lu Zhao. Without their support, understanding, and unconditional love, I cannot go through my ups and downs and finish my Ph.D. A last big thank you to my wife, Lingjie Zhang, for her love, support, for bringing enthusiasm in my life, and for being patient and understanding. Funding Acknowledgment My research was supported by National Science Foundation (NSF- BIGDATA IIS-1247693, NSF-XPS CCF1337131), Air Force Office of Scientific Research (AFOSR) Basic Research Initiative (Grant No. FA9550-12-1-0442), the European Unions Horizon 2020 re- search and innovation programme under the
Load more

Recommended publications
  • Fast Parallel GPU-Sorting Using a Hybrid Algorithm
    Fast Parallel GPU-Sorting Using a Hybrid Algorithm Erik Sintorn Ulf Assarsson Department of Computer Science and Engineering Department of Computer Science and Engineering Chalmers University Of Technology Chalmers University Of Technology Gothenburg, Sweden Gothenburg, Sweden Email: [email protected] Email: uffe at chalmers dot se Abstract— This paper presents an algorithm for fast sorting of that supports scattered writing. The GPU-sorting algorithms large lists using modern GPUs. The method achieves high speed are highly bandwidth-limited, which is illustrated for instance by efficiently utilizing the parallelism of the GPU throughout the by the fact that sorting of 8-bit values [10] are nearly four whole algorithm. Initially, a parallel bucketsort splits the list into enough sublists then to be sorted in parallel using merge-sort. The times faster than for 32-bit values [2]. To improve the speed of parallel bucketsort, implemented in NVIDIA’s CUDA, utilizes the memory reads, we therefore design a vector-based mergesort, synchronization mechanisms, such as atomic increment, that is using CUDA and log n render passes, to work on four 32- available on modern GPUs. The mergesort requires scattered bit floats simultaneously, resulting in a nearly 4 times speed writing, which is exposed by CUDA and ATI’s Data Parallel improvement compared to merge-sorting on single floats. The Virtual Machine[1]. For lists with more than 512k elements, the algorithm performs better than the bitonic sort algorithms, which Vector-Mergesort of two four-float vectors is achieved by using have been considered to be the fastest for GPU sorting, and is a custom designed parallel compare-and-swap algorithm, on more than twice as fast for 8M elements.
    [Show full text]
  • GPU Sample Sort We Should Mention That Hybrid Sort [15] and Bbsort [4] Involve a Distribution Phase Assuming That the Keys Are Uniformly Distributed
    GPU Sample Sort Nikolaj Leischner∗ Vitaly Osipov† Peter Sanders‡ Abstract In this paper, we present the design of a sample sort algorithm for manycore GPUs. Despite being one of the most efficient comparison-based sorting algorithms for distributed memory architectures its performance on GPUs was previously unknown. For uniformly distributed keys our sample sort is at least 25% and on average 68% faster than the best comparison-based sorting algorithm, GPU Thrust merge sort, and on average more than 2 times faster than GPU quicksort. Moreover, for 64-bit integer keys it is at least 63% and on average 2 times faster than the highly optimized GPU Thrust radix sort that directly manipulates the binary representation of keys. Our implementation is robust to different distributions and entropy levels of keys and scales almost linearly with the input size. These results indicate that multi-way techniques in general and sample sort in particular achieve substantially better performance than two-way merge sort and quicksort. 1 Introduction Sorting is one of the most widely researched computational problems in computer science. It is an essential building block for numerous algorithms, whose performance depends on the efficiency of sorting. It is also an internal primitive utilized by database operations, and therefore, any applica- tion that uses a database may benefit from an efficient sorting algorithm. Geographic information systems, computational biology, and search engines are further fields that involve sorting. Hence, it is of utmost importance to provide efficient sort primitives for emerging architectures, which arXiv:0909.5649v1 [cs.DS] 30 Sep 2009 exploit architectural attributes, such as increased parallelism that were not available before.
    [Show full text]
  • A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis
    A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis Yomna Ben Jmaa1,2, Rabie Ben Atitallah2, David Duvivier2, Maher Ben Jemaa1 1 NIS University of Sfax, ReDCAD, Tunisia 2 Polytechnical University Hauts-de-France, France [email protected], fRabie.BenAtitallah, [email protected], [email protected] Abstract. Nowadays, sorting is an important operation the risk of accidents, the traffic jams and pollution. for several real-time embedded applications. It is one Also, ITS improve the transport efficiency, safety of the most commonly studied problems in computer and security of passengers. They are used in science. It can be considered as an advantage for various domains such as railways, avionics and some applications such as avionic systems and decision automotive technology. At different steps, several support systems because these applications need a applications need to use sorting algorithms such sorting algorithm for their implementation. However, as decision support systems, path planning [6], sorting a big number of elements and/or real-time de- cision making need high processing speed. Therefore, scheduling and so on. accelerating sorting algorithms using FPGA can be an attractive solution. In this paper, we propose an efficient However, the complexity and the targeted hardware implementation for different sorting algorithms execution platform(s) are the main performance (BubbleSort, InsertionSort, SelectionSort, QuickSort, criteria for sorting algorithms. Different platforms HeapSort, ShellSort, MergeSort and TimSort) from such as CPU (single or multi-core), GPU (Graphics high-level descriptions in the zynq-7000 platform. In Processing Unit), FPGA (Field Programmable addition, we compare the performance of different Gate Array) [14] and heterogeneous architectures algorithms in terms of execution time, standard deviation can be used.
    [Show full text]
  • Parallelization of Tim Sort Algorithm Using Mpi and Cuda
    JOURNAL OF CRITICAL REVIEWS ISSN- 2394-5125 VOL 7, ISSUE 09, 2020 PARALLELIZATION OF TIM SORT ALGORITHM USING MPI AND CUDA Siva Thanagaraja1, Keshav Shanbhag2, Ashwath Rao B3[0000-0001-8528-1646], Shwetha Rai4[0000-0002-5714-2611], and N Gopalakrishna Kini5 Department of Computer Science & Engineering Manipal Institute Of Technology Manipal Academy Of Higher Education Manipal, Karnataka, India-576104 Abstract— Tim Sort is a sorting algorithm developed in 2002 by Tim Peters. It is one of the secure engineered algorithms, and its high-level principle includes the sequence S is divided into monotonic runs (i.e., non- increasing or non-decreasing subsequence of S), which should be sorted and should be combined pairwise according to some specific rules. To interpret and examine the merging strategy (meaning that the order in which merge and merge runs are performed) of Tim Sort, we have implemented it in MPI and CUDA environment. Finally, it can be seen the difference in the execution time between serial Tim Sort and parallel Tim sort run in O (n log n) time . Index Terms— Hybrid algorithm, Tim sort algorithm, Parallelization, Merge sort algorithm, Insertion sort algorithm. I. INTRODUCTION Sorting algorithm Tim Sort [1] was designed in 2002 by Tim Peters. It is a hybrid parallel sorting algorithm that combines two different sorting algorithms. This includes insertion sort and merge sort. This algorithm is an effective method for well-defined instructions. The algorithm is concealed as a finite list for evaluating Tim sort function. Starting from an initial state and its information the guidelines define a method that when execution continues through a limited number of next states.
    [Show full text]
  • An English-Persian Dictionary of Algorithms and Data Structures
    An EnglishPersian Dictionary of Algorithms and Data Structures a a zarrabibasuacir ghodsisharifedu algorithm B A all pairs shortest path absolute p erformance guarantee b alphab et abstract data typ e alternating path accepting state alternating Turing machine d Ackermans function alternation d Ackermanns function amortized cost acyclic digraph amortized worst case acyclic directed graph ancestor d acyclic graph and adaptive heap sort ANSI b adaptivekdtree antichain adaptive sort antisymmetric addresscalculation sort approximation algorithm adjacencylist representation arc adjacencymatrix representation array array index adjacency list array merging adjacency matrix articulation p oint d adjacent articulation vertex d b admissible vertex assignmentproblem adversary asso ciation list algorithm asso ciative binary function asso ciative array binary GCD algorithm asymptotic b ound binary insertion sort asymptotic lower b ound binary priority queue asymptotic space complexity binary relation binary search asymptotic time complexity binary trie asymptotic upp er b ound c bingo sort asymptotically equal to bipartite graph asymptotically tightbound bipartite matching
    [Show full text]
  • Register Level Sort Algorithm on Multi-Core SIMD Processors
    Register Level Sort Algorithm on Multi-Core SIMD Processors Tian Xiaochen, Kamil Rocki and Reiji Suda Graduate School of Information Science and Technology The University of Tokyo & CREST, JST {xchen, kamil.rocki, reiji}@is.s.u-tokyo.ac.jp ABSTRACT simultaneously. GPU employs a similar architecture: single- State-of-the-art hardware increasingly utilizes SIMD paral- instruction-multiple-threads(SIMT). On K20, each SMX has lelism, where multiple processing elements execute the same 192 CUDA cores which act as individual threads. Even a instruction on multiple data points simultaneously. How- desktop type multi-core x86 platform such as i7 Haswell ever, irregular and data intensive algorithms are not well CPU family supports AVX2 instruction set (256 bits). De- suited for such architectures. Due to their importance, it veloping algorithms that support multi-core SIMD architec- is crucial to obtain efficient implementations. One example ture is the precondition to unleash the performance of these of such a task is sort, a fundamental problem in computer processors. Without exploiting this kind of parallelism, only science. In this paper we analyze distinct memory accessing a small fraction of computational power can be utilized. models and propose two methods to employ highly efficient Parallel sort as well as sort in general is fundamental and bitonic merge sort using SIMD instructions as register level well studied problem in computer science. Algorithms such sort. We achieve nearly 270x speedup (525M integers/s) on as Bitonic-Merge Sort or Odd Even Merge Sort are widely a 4M integer set using Xeon Phi coprocessor, where SIMD used in practice.
    [Show full text]
  • Hybrid Quicksort: an Empirical Study
    International Journal of Communication & Information Technology (CommIT) http://msi.binus.ac.id/commit/ Vol. 7 No. 2 Oktober 2013, pp. 41-45 HYBRID QUICKSORT: AN EMPIRICAL STUDY Surya Sujarwo School of Computer Science, Bina Nusantara University Jln. K. H. Syahdan No. 9, Jakarta 11480, Indonesia [email protected] Abstract: This article describes an empirical study of hybrid approach of quicksort algorithms. The hybrid approach uses various variations of quicksort partition algorithms in combination with cutoff to shellsort using several cutoff elements. The paper compares the running time performance of the existing quicksort partition algorithms with the proposed hybrid approachusing uniqueand duplicate elements. As a result, it is found that several the hybrid approaches performs faster than the existing algorithms for uniqueand duplicate elements. Keywords: Hybrid approach; Cutoff; Shellsort; Quicksort INTRODUCTION paper is organized as follows: a section describing Sorting plays a major role in commercial data existing algorithms used in partition for comparison, processing [1]. Many applications utilize quicksort a section describing the proposed hybrid approach algorithm because the algorithm works well and algorithm inspired from existing algorithms, and a easy to implement for variety of different kinds of section comparing the performance of existing and input data. The algorithm is substantially faster than proposed algorithms. other sorting methods for general purpose use [1, 2]. In addition, the algorithm uses no additional space Existing Algorithms for data storing and requires processing time that The first existing quicksort partition algorithm proportional to n log (n) on average to sort n items [1, used for comparison is based on Hoare algorithm 3].
    [Show full text]
  • Fast Parallel Gpu-Sorting Using a Hybrid Algorithm
    Fast Parallel GPU-Sorting Using a Hybrid Algorithm Erik Sintorn, Ulf Assarsson Department of Computer Science and Engineering Chalmers University Of Technology Gothenburg, Sweden Abstract This paper presents an algorithm for fast sorting of large lists using modern GPUs. The method achieves high speed by efficiently utilizing the parallelism of the GPU throughout the whole algorithm. Initially, GPU-based bucketsort or quicksort splits the list into enough sublists then to be sorted in parallel using merge-sort. The algorithm is of complexity n log n, and for lists of 8M elements and using a single Geforce 8800GTS-512, it is 2.5 times as fast as the bitonic sort algorithms, with standard complexity of n(log n)2, which for long was considered to be the fastest for GPU sorting. It is 6 times faster than single CPU quicksort, and 10% faster than the recent GPU-based radix sort. Finally, the algorithm is further parallelized to utilize two graphics cards, resulting in yet another 1.8 times speedup. Key words: parallelism, sorting, GPU-algorithms PACS: 07.05.Hd, 07.05.Kf 1 Introduction Sorting is a general problem in computer science. Mergesort [11] is a well- known sorting algorithm of complexity O(n log n), and it can easily be im- plemented on a GPU that supports scattered writing. The GPU-sorting algo- rithms are highly bandwidth-limited, which is illustrated for instance by the fact that bitonic sorting of 8-bit values [5] are nearly four times faster than for 32-bit values [4]. To improve the speed of memory reads, we therefore design a vector-based mergesort, using CUDA and log n render passes, to work on four 32-bit floats simultaneously, resulting in a nearly 4 times speed improvement compared to merge-sorting on single floats.
    [Show full text]
  • Sorting with Gpus: a Survey Dmitri I
    1 Sorting with GPUs: A Survey Dmitri I. Arkhipov, Di Wu, Keqin Li, and Amelia C. Regan Abstract—Sorting is a fundamental operation in computer Our key findings are the following: science and is a bottleneck in many important fields. Sorting • Effective parallel sorting algorithms must use the faster is critical to database applications, online search and indexing, biomedical computing, and many other applications. The explo- access on-chip memory as much and as often as possible sive growth in computational power and availability of GPU as a substitute to global memory operations. coprocessors has allowed sort operations on GPUs to be done • Algorithmic improvements that used on-chip memory much faster than any equivalently priced CPU. Current trends and made threads work more evenly seemed to be more in GPU computing shows that this explosive growth in GPU effective than those that simply encoded sorts as primitive capabilities is likely to continue for some time. As such, there is a need to develop algorithms to effectively harness the power of GPU operations. GPUs for crucial applications such as sorting. • Communication and synchronization should be done at points specified by the hardware. Index Terms—GPU, sorting, SIMD, parallel algorithms. • Which GPU primitives (scan and 1-bit scatter in partic- ular) are used makes a big difference. Some primitive I. INTRODUCTION implementations were simply more efficient than others, In this survey, we explore the problem of sorting on GPUs. and some exhibit a greater degree of fine grained paral- As GPUs allow for effective hardware level parallelism, re- lelism than others.
    [Show full text]
  • Comparison Based Sorting for Systems with Multiple Gpus
    Comparison Based Sorting for Systems with Multiple GPUs Ivan Tanasicx, Lluís Vilanovax, Marc Jordàx, Javier Cabezasx, Isaac Geladox Nacho Navarroxz, Wen-mei Hwu∗ xBarcelona Supercomputing Center zUniversitat Politecnica de Catalunya ∗University of Illinois {first.last}@bsc.es [email protected] [email protected] ABSTRACT 1. INTRODUCTION As a basic building block of many applications, sorting algo- Sorting is a key building block in many High Performance rithms that efficiently run on modern machines are key for Computing (HPC) applications. Examples of these are N- the performance of these applications. With the recent shift body simulations [1], some high performance sparse ma- to using GPUs for general purpose compuing, researches trix-vector multiplication implementations [2], graphics al- have proposed several sorting algorithms for single-GPU sys- gorithms like Bounding Volume Hierarchy (BVH) construc- tems. However, some workstations and HPC systems have tion [3], database operations [4], machine learning algorithms multiple GPUs, and applications running on them are de- [5] and MapReduce framework implementations [6, 7]. signed to use all available GPUs in the system. A common trend in computing today is the utilization In this paper we present a high performance multi-GPU of Graphical Processing Units (GPUs) that efficiently exe- merge sort algorithm that solves the problem of sorting data cute codes rich in data parallelism, to form high performance distributed across several GPUs. Our merge sort algorithm heterogeneous systems [8]. In these CPU/GPU systems, ap- first sorts the data on each GPU using an existing single- plication phases rich in data parallelism are executed in the GPU sorting algorithm.
    [Show full text]
  • 1 Slide 3: Introduction Multi-Way Sorting Algorithms
    1 Slide 3: Introduction multi-way sorting algorithms A general divide-and-conquer technique can be described in three steps: the input is recursively split into k tiles while the tile size exceeds a fixed size M, individual tiles are sorted independently and merged into the final sorted sequence. Most divide-and-conquer algorithms are based either on a k-way distribution or a k-way merge procedure. In the former case, the input is split into tiles that are delimited by k ordered splitting elements. The sorted tiles form a sorted sequence, thus making the merge step superfluous. As for a k-way merge procedure, the input is evenly divided into logk n/M tiles, that are sorted and k-way merged in the last step. In contrast to two-way quicksort or merge sort, multi-way approaches perform logk n/M scans through the data (in expectation for k-way distribution). This general pattern gives rise to several efficient manycore algorithms varying only in the way they implement individual steps. For instance, in a multicore gcc sort routine [10], each core gets an equal-sized part of the input (thus k is equal to the number of cores), sorts it using introsort [6], and finally, cooperatively k-way merges the intermediate results. 1 2 Slide 4: NVidia Tesla Architecture Current NVidia GPUs feature up to 30 streaming multiprocessors (SMs) each of which containing 8 scalar processors (SPs), i.e., up to 240 physical cores. However, they require a minimum of around 5000–10 000 threads to fully utilize hardware and hide memory latency.
    [Show full text]
  • UC Davis IDAV Publications
    UC Davis IDAV Publications Title Efficient Parallel Merge Sort for Fixed and Variable Length Keys Permalink https://escholarship.org/uc/item/2514r4h1 Authors Davidson, Andrew Tarjan, David Garland, Michael et al. Publication Date 2012 DOI 10.1109/InPar.2012.6339592 Peer reviewed eScholarship.org Powered by the California Digital Library University of California Efficient Parallel Merge Sort for Fixed and Variable Length Keys Andrew Davidson David Tarjan University of California, Davis NVIDIA Corporation [email protected] [email protected] Michael Garland John D. Owens NVIDIA Corporation University of California, Davis [email protected] [email protected] ABSTRACT ison sorts on the GPU include a bitonic sort by Peters et al. [16], We design a high-performance parallel merge sort for highly paral- a bitonic-based merge sort (named Warpsort) by Ye et al. [26] a lel systems. Our merge sort is designed to use more register com- Quicksort by Cederman and Tsigas [5] and sample sorts by Leis- munication (not shared memory), and does not suffer from over- chner et al. [12] and Dehne and Zaboli [8]. segmentation as opposed to previous comparison based sorts. Us- In this work we implement a merge-sort-based comparison sort ing these techniques we are able to achieve a sorting rate of 250 that is well-suited for massively parallel architectures like the GPU. MKeys/sec, which is about 2.5 times faster than Thrust merge sort Since a GPU requires hundreds or thousands of threads to reach performance, and 70% faster than non-stable state-of-the-art GPU bandwidth saturation, an efficient GPU comparison sort must se- merge sorts.
    [Show full text]