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Ultrasparc T2 Processor UltraSPARC T2 Processor Vortrag im Rahmen des Seminars „Ausgewählte Themen in Hardwareentwurf und Optik“ HWS07 Universität Mannheim Janusz Schinke Inhalt Überblick Core Crossbar L2 Cache Internes Netzwerk PCI-Express Power Management System Status & Einsatz Bereich Zusammenfassung 09.10.07 Janusz Schinke 2 UltraSPARC T2 Processor Überblick Überblick 1/5 Zweite Generation eines Chip Multi-Threading (CMT) Prozessors 8 Sparc Cores, 4MB shared L2 Cache. Ausführung von 64 Threads (8 Threads pro Core). mehr als doppelte UltraSparc T1's Rechenleistung und Rechenleistung/Watt. mehr als zehn mal schnellere Floating Point Berechnung 09.10.07 Janusz Schinke 4 Überblick 2/5 Server-on-a-Chip Komponenten (SOC) zwei 10G Ethernet Anschlüsse Verschlüsselungseinheit On-chip PCI-Express FBDIMM Speicher 09.10.07 Janusz Schinke 5 Überblick 3/5 Block Diagramm 09.10.07 Janusz Schinke 6 Überblick 4/5 Niagara2 Die Micrograph 09.10.07 Janusz Schinke 7 Überblick 5/5 09.10.07 Janusz Schinke 8 UltraSPARC T2 Processor Core Core IFU – Instruction Fetch Unit EXU0/1 – Integer Execution Units LSU – Load/Store Unit FGU – Floating-Point/Graphics Unit SPU – Security Processing Unit TLU – Trap Logic Unit MMU – Memory Management Unit 09.10.07 Janusz Schinke 10 Core Pipeline 8-stufige Integer Pipeline 3-Taktzyklen load-use Latenz Speicher Bypass Writeback 09.10.07 Janusz Schinke 11 Core Pipeline 12-stufige Floating-Point Pipeline 6-Taktzyklen Latenz für abhnängige FP Operationen Längere Pipeline Stufe für Division/Quadratwurzel 09.10.07 Janusz Schinke 12 IFU – Instruction Fetch Unit Die IFU besteht aus: Fetch Unit Pick Unit Decode Unit Sprungvorhersage Bei falscher Vorhersage 5 Takte Latenz 09.10.07 Janusz Schinke 13 EXU0/1 – Integer Execution Units Führt alle ganzzahlige Berechnungen und logischen Operationen aus Untermodule Arithmetic Logic Einheit (ALU) Shifter (SHFT) Operand Bypass (BYP) Inetger Register File (IRF) Register Management Logic (RML) 09.10.07 Janusz Schinke 14 LSU – Load/Store Unit Eine Load /Store Operation pro Takt Funktions Blöcke: Data Cache Array (DCA) Data Tag Array (DTAG) Data Translation Lookaside Buffer (DTLB) Load Miss Queue (LMQ) Store buffer (STB) Gasket 09.10.07 Janusz Schinke 15 FGU – Floating/Graphics Unit Ein FGU pro Core 8 Threads teilen sich eine FGU Komplett gepipelined (ausgenommen Division/Quadratwurzel) FGU führt Integer Multiplikationen und Divisionen aus 09.10.07 Janusz Schinke 16 SPU - Security Processing Unit Eine SPU pro Core Zwei unabhängige Submodule Modular Arithmetic Einheit (MA) Cipher/Hash Einheit Direct Memory Access (DMA) Engine benutzt den Crossbar Port des Cores 09.10.07 Janusz Schinke 17 SPU - Security Processing Unit Linear Feedback Shift Register (LFSR) Voltage Controlled Oscillator (VCO) Liefert 64-bittige Zufallszahlen etwa 10 mal schnellere Verschlüsselungsfunktion Janusz Schinke 09.10.07 18 TLU – Trap Logic Unit Flush Logic erzeugt Flushes als Antwort auf Exception Trap Stack Array (TSA) verwaltet Trap Zustände für acht Threads Trap State Machine arbitriert Trap Anfragen für acht Threads in zwei Gruppen. 09.10.07 Janusz Schinke 19 MMU – Memory Management Unit Hardware Tablewalk bis zu 4 Page Tables gleichzeitig Jede Page Table unterstützt eine Seitengröße von 8KB, 64KB, 4MB oder 256MB Drei Suchmodi : Sequential Burst Prediction 09.10.07 Janusz Schinke 20 MMU – Memory Management Unit Translation Storage Buffer(TSB) Translation Lookaside Buffer (TLB) Translation Table Entries (TTE) Real Adress (RA) Physical Adress (PA) Alternate Space Identifier(ASI) 09.10.07 Janusz Schinke 21 UltraSPARC T2 Processor Crossbar Crossbar 65nm, vorauss. 1.4GHz Core-Takt 8 Cores mit je 8 Threads ⇒ 64 „CPUs“ on Die! Verdoppelung der Threads ist flächeneffizienter als Verdoppelung der Cores. Crossbar on Chip 09.10.07 Janusz Schinke 23 UltraSPARC T2 Processor L2 Cache L2 Cache 4 MB L2 Cache 16 fach assoziativ 8 L2 Bänke 64 Byte Cache Line Größe Kohärenz wird durch den L2 Cache gehandhabt Datentransfer zwischen L2 Cache und Core erfolgt in 16 byte Paketen 09.10.07 Janusz Schinke 25 UltraSPARC T2 Processor Internes Netzwerk Internes Netzwerk 1/2 09.10.07 Janusz Schinke 27 Internes Netzwerk 2/2 Networking Features Mehrere DMA (Direct Memory Access) Einheiten Ordnet die DMAs den Threads zu 16 Sende- und 16 Empfangskanäle Zwei Ethernetanschlüsse 2 dual-speed (10G/1G) 09.10.07 Janusz Schinke 28 UltraSPARC T2 Processor PCI-Express PCI-Express I/O Memory Mapping Unit (IOMMU) Transaction Layer Packets (TLPs) Datentransfer geschieht in Form von Paketen mit Header und einer Payload zwischen 128B und 512B 09.10.07 Janusz Schinke 30 UltraSPARC T2 Processor Power Management Power Management Durch den Einsatz der Chip Multi Threading (CMT) Technlogie konnte die Leistung pro Watt optimiert werden. 'GATE-BIAS' Zellen benutzt um Leckströme zu reduzieren. 09.10.07 Janusz Schinke 32 Power Management 09.10.07 Janusz Schinke 33 Power Management 09.10.07 Janusz Schinke 34 UltraSPARC T2 Processor System Status & Einsatz Bereich System Status & Einsatz Bereich Erste CPU wurde schon Ende Mai ausgeliefert Die ersten UltraSparc T2 Systeme werden 2H2007 erwartet Server: Web, DB, etc. 09.10.07 Janusz Schinke 36 UltraSPARC T2 Processor Zusammenfassung Zusammenfassung Niagara2 kombiniert alle hauptsächlichen Serverfunktionen auf einem Chip Internes Netzwerk PCI-Express Kryptographische Einheit Niagara2 hat die Leistung verbessert ggü. UltraSparc T1 Besserer Integer Durchsatz und Durchsatz/Watt (>2x) Verbesserte Integer Single-Thread Leistung (>1.4x) Besserer Floating-Point Durchsatz (>10x) Bessere Floating-Point Single-Thread Leistung (>5x) Ermöglicht neue energiesparsame, Hochsicherheits rechenzentren 09.10.07 Janusz Schinke 38 09.10.07 Janusz Schinke 39 09.10.07 Janusz Schinke 40 Ausblick : Der ROCK 16 CPU Kerne in einem Viererverband Je Verband 32KB I - Cache Je Verband 32KB D - Cache 4x512KB L2 Cache Wahrscheinlich Hybrid Transaction Memory (HTM) 09.10.07 Janusz Schinke 41 Quellenverzeichnis [1] http://opensparc.net/cgi-bin/goto.php?w=http://opensparc- t2.sunsource.net/specs/OpenSPARCT2_Core_Micro_Arch.pdf [2] http://opensparc- t2.sunsource.net/specs/OpenSPARCT2_SoC_Micro_Arch.pdf [3] http://realworldtech.com/page.cfm?ArticleID=RWT090406012516 [4] http://www.golem.de/0708/54029.html [5] http://www.pc- magazin.de/common/nws/einemeldung.php?id=53721 [6] http://www.heise.de/newsticker/meldung/93999 [7]http://www.embedded.com/news/embeddedindustry/192300656?p gno=1 [8]http://www.opensparc.net/pubs/preszo/06/HotChips06_09_ppt_ma ster.pdf 09.10.07 Janusz Schinke 42 UltraSPARC T2 Processor FRAGEN?.
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