US009748371B2 (12 ) United States Patent ( 10 ) Patent No. : US 9 , 748 ,371 B2 Radosavljevic et al. ( 45 ) Date of Patent : Aug. 29 , 2017

(54 ) TRANSITION METAL DICHALCOGENIDE ( 56 ) References Cited SEMICONDUCTOR ASSEMBLIES ( 71 ) Applicant: Intel Corporation , Santa Clara , CA U . S . PATENT DOCUMENTS (US ) 2007 /0181938 A1 8 /2007 Bucher et al. ( 72 ) Inventors: Marko Radosavljevic , Portland , OR 2009/ 0146141 A1 6 /2009 Song et al. (US ) ; Brian S . Doyle , Portland , OR (Continued ) (US ); Ravi Pillarisetty , Portland , OR (US ) ; Niloy Mukherjee , Portland , OR FOREIGN PATENT DOCUMENTS (US ); Sansaptak Dasgupta , Hillsboro , OR (US ) ; Han Wui Then , Portland , KR 101348059 B1 1 / 2014 OR (US ) ; Robert S . Chau , Beaverton , WO 2012093360 A1 7 / 2012 OR (US ) ( 73 ) Assignee : INTEL CORPORATION , Santa Clara , OTHER PUBLICATIONS CA (US ) International Search Report and Written Opinion mailed Dec . 11 , ( * ) Notice : Subject to any disclaimer, the term of this 2014 , issued in corresponding International Application No . PCT/ patent is extended or adjusted under 35 US2014 /031496 , 10 pages . U . S . C . 154 (b ) by 0 days . (Continued ) (21 ) Appl. No. : 15 /120 , 496 (22 ) PCT Filed : Mar. 21 , 2014 Primary Examiner — Jaehwan Oh (86 ) PCT No .: PCT/ US2014 /031496 (74 ) Attorney , Agent, or Firm — Schwabe, Williamson & $ 371 (c )( 1 ), Wyatt , P .C . ( 2 ) Date : Aug . 19 , 2016 ( 87 ) PCT Pub . No .: WO2015 /142358 (57 ) ABSTRACT PCT Pub . Date : Sep . 24 , 2015 Embodiments of semiconductor assemblies, and related (65 ) Prior Publication Data integrated circuit devices and techniques, are disclosed US 2017 /0012117 A1 Jan . 12 , 2017 herein . In some embodiments , a semiconductor assembly (51 ) Int. CI. may include a flexible substrate , a first barrier formed of a HOIL 29/ 778 ( 2006 . 01 ) first transition metal dichalcogenide ( TMD ) material, a HOIL 29 / 786 transistor channel formed of a second TMD material, and a ( 2006 .01 ) second barrier formed of a third TMD material. The first (Continued ) barrier may be disposed between the transistor channel and (52 ) U . S . CI. the flexible substrate , the transistor channel may be disposed CPC .. . . HOLL 29/ 7782 ( 2013. 01 ); HOLL 21/ 02422 between the second barrier and the first barrier, and a ( 2013 .01 ) ; HOLL 21/ 02568 ( 2013 .01 ) ; bandgap of the transistor channel may be less than a bandgap (Continued ) of the first barrier and less than a bandgap of the second (58 ) Field of Classification Search barrier. Other embodiments may be disclosed and /or ??? ...... HO1L 29 / 24 ; HO1L 29 /66969 ; HOIL claimed . 29 /78696 ; HO1L 21 /02568 ; HOIL 29 /78681 ; H01L 29/ 778 ; H01L 21 /02527 See application file for complete search history . 22 Claims, 6 Drawing Sheets

100

116 118 - - 120 114 12424. . . . .ULU . 106 108 112 110 - 124124

104 102

122 US 9 ,748 ,371 B2 Page 2

(51 ) Int. Cl. HOIL 29 /24 ( 2006 .01 ) HOIL 21/ 02 ( 2006 . 01 ) HOIL 21/ 8256 ( 2006 .01 ) HOIL 27 / 12 ( 2006 .01 ) HOIL 29 /66 ( 2006 . 01 ) HOIL 29 /08 ( 2006 . 01) (52 ) U . S . CI. CPC ...... HOIL 21 /8256 ( 2013 .01 ) ; HOIL 27 / 124 ( 2013 . 01 ) ; HOIL 27 / 1225 ( 2013 .01 ) ; HOIL 29 /24 ( 2013 . 01 ) ; HOIL 29 /66969 ( 2013 .01 ) ; HOIL 29 / 786 ( 2013 . 01 ) ; HOIL 29 /0843 ( 2013 .01 ) ( 56 ) References Cited U . S . PATENT DOCUMENTS 2013 /0105824 A1 5 /2013 Paranjape et al . 2015 / 0303315 A1 * 10 / 2015 Das ...... HO1L 29 /78681 257 / 347 2016/ 0093491 A1 * 3 / 2016 Choi ...... HO1L 21/ 02485 438 / 151 2017/ 0015599 A1* 1/ 2017 Bessonov ...... C04B 41/ 80 OTHER PUBLICATIONS Taiwan Office Action mailed mailed Jul. 26 , 2016 , issued in corresponding Taiwan Patent Application No . 104104565. International Preliminary Report on Patentability mailed Oct . 6 , 2016 , issued in corresponding International Application No. PCT/ US2014 /031496 , 7 pages. * cited by examiner U . S . Patert A ug. 29, 2017 sheet 1 of 6 US 9 , 748 , 371 B2

? ??

?? 6 ? 3 ??. . 2

? # 223 24 ,, . . . . . ?? ??? ????????????????????------. . . ------. . . 124. #

???????

? ? 22 FIG. 1

2C - - 202 ?02 EIG. 2 U . S . Patent Aug. 29 , 2017 Sheet 2 of 6 US 9, 748 . 371 B2

32 3 ~ 302 | 104 102 FIG . 3

400 42 | 110 104 102 FIG. 4

112 10 104

02 FIG . 5 U . S . Patent Aug. 29 ,2017 Sheet 3 of 6 US 9 , 748 ,371 B2

60060------2 604

5??

- 6 “ ????? 112 11

{} & { .

102 FIG . 6 10 “ ? 18

114 16 { 08 112 11

4, 102 FIG . 7 ...U . S . Patent ...Aug. 29, 2017 Sheet... 4 of 6 ...US 9 , 748... , 371. B2

? 826

????????????? ????????????

??? 82 }

??? 6 ? 82 - 84834

NON

84 84

FIG . 8 U . S . Patent Aug . 29, 2017 Sheet 5 of 6 US 9 ,748 , 371 B2

900

mere START

DEPOSIT A TMD MATERIAL ON A FLEXIBLE SUBSTRATE TO FORM A FIRST BARRIER 902

DEPOSIT A TMD MATERIAL ON THE FIRST BARRIER TO FORM A TRANSISTOR CHANNEL 904

DEPOSIT A TMD MATERIAL ON THE TRANSISTOR CHANNEL TO FORMA SECOND BARRIER 906 . - .- .- . - . .-. - . - . .-. . . . DEPOSIT TMD MATERIALS TO FORMA TRANSISTOR SOURCE AND DRAIN 908 DEPOSIT TMD MATERIALS TO FORM CONDUCTIVE CONTACTS 910

FORMDV INTERCONNECTS 912

END

FIG . 9 U . S . Patent Aug . 29, 2017 Sheet 6 of 6 US 9 ,748 , 371 B2

= CAMERA COMMUNICATION CHIP PROCESSOR 1006 1004 COMMUNICATION CHIP 1006

CHIPSET DRAM DRAM ???? GRAPHICS 2 AMP CPU fram UU

ROM 2

TOUCHSCREEN 2 CONTROLLER GPS COMPASS MOTHERBOARD 1002 TOUCHSCREEN SPEAKER DISPLAY

BATTERY COMPUTING DEVICE 1000 FIG . 10 US 9 ,748 , 371 B2 TRANSITION METAL DICHALCOGENIDE first transition metal dichalcogenide ( TMD ) material, a SEMICONDUCTOR ASSEMBLIES transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first CROSS -REFERENCE TO RELATED barrier may be disposed between the transistor channel and APPLICATION 5 the flexible substrate , the transistor channel may be disposed between the second barrier and the first barrier , and a The present application is a national phase entry under 35 bandgap of the transistor channelmay be less than a bandgap U .S . C . 8371 of International Application No. PCT/ US2014 ) of the first barrier and less than a bandgap of the second barrier. 031496 , filed Mar . 21 , 2014 , entitled “ TRANSITIONR10 The semiconductor assemblies and related techniques METAL DICHALCOGENIDE SEMICONDUCTOR 10 disclosed herein may enable the formation of transistor ASSEMBLIES , ” which designates the United States of device layers on flexible substrates with improved perfor America , the entire disclosure of which is hereby incorpo mance properties over existing flexible substrate integrated rated by reference in its entirety and all purposes . circuit (IC ) devices. In particular, the semiconductor assem TECHNICAL FIELD 15 blies disclosed herein may use TMD materials , which are compounds of a transition metal and sulfur, , or The present disclosure relates generally to the field of tellurium . TMD materials may take the form of two -dimen semiconductor devices , and more particularly , to semicon sional layers of molecules weakly bonded between layers ductor assemblies with transition metal dichalcogenide via physical bonds (e . g ., van der Waal' s forces ) to form a 20 three -dimensional structure . In some embodiments , a semi ( TMD ) materials . conductor assembly may predominantly or wholly be BACKGROUND formed of TMD materials . Various embodiments of TMD materials may provide a Some attempts have been made to develop flexible elec - number of advantages over conventional semiconductor tronic circuits for use in wearables and other devices. In 25 materials . First, a conventional three -dimensional material these devices, flexibility has typically been obtained at the may be constrained by strong chemical bonds ( e . g . , covalent expense of electrical performance . In particular, because the around bonds) between molecules in a layer and between substrates used in existing flexible electronic circuits are layers, and therefore must absorb the distortion forces both unable to withstand high processing temperatures, only within a layer and between layers . Thus , such materials may semiconductor materials with low processing temperatures 30 be brittle ; if the chemical bonding constraints are violated , have been used ; because these materials typically have a conventional three - dimensional material may fail . By lower performance than materials with high processing contrast, when a TMD material is physically distorted ( e . g ., temperatures, electrical performance of flexible electronic by bending ) , the two -dimensional layers may readily adjust the weak bonds between layers to respond to the distortion circuits has been limited . 35 ( e . g . , by moving and sliding ) . Consequently , various BRIEF DESCRIPTION OF THE DRAWINGS embodiments of TMD materials may be more resilient to physical distortion , and therefore may be more appropriate Embodiments will be readily understood by the following for use with flexible substrates . detailed description in conjunction with the accompanying Additionally , when conventional three - dimensionalmate drawings . To facilitate this description , like reference 40 rials are thinned so as to reduce the number of layers ( and numerals designate like structural elements . Embodiments consequently , the number of layers of chemical bond con are illustrated by way of example, and not by way of straints) , the thinning may disrupt the crystal structure of the limitation , in the figures of the accompanying drawings . three -dimensional material and may create dangling bonds . FIG . 1 is cross -sectional view of a semiconductor assem - These dangling bonds may exhibit a high recombination rate bly including one or more transition metal dichalcogenide 45 and thereby deplete local regions of minority carriers and ( TMD ) materials, in accordance with various embodiments . impede the electrical performance of the thinned three FIGS. 2 - 7 are side views of various stages in a process for dimensional material. By contrast , because various embodi manufacturing the semiconductor assembly of FIG . 1 , in ments of TMD materials may be " true ” two -dimensional accordance with various embodiments . materials (with no chemical bonds between layers ) , electri FIG . 8 is a cross -sectional view of a portion of an 50 cal performance of TMD materials may not suffer from integrated circuit ( IC ) device , which may include one or dangling bond -related depletion . more of the semiconductor assemblies disclosed herein , in The interlayer chemical bonding constraints of conven accordance with some embodiments . tional three - dimensional materials may also limit the range FIG . 9 is a flow diagram of an illustrative process for of substrates that may be used . In particular, since a layer of manufacturing an IC device including a semiconductor 55 a conventional three -dimensional material seeks to chemi assembly with TMD materials , in accordance with various cally bond with molecules in the substrate , substrates must embodiments . often be selected so as to have a lattice structure that FIG . 10 schematically illustrates a computing device that approximately matches the lattice structure of the three may include one or more semiconductor assemblies dis - dimensional material. When these lattice structures fail to closed herein , in accordance with various embodiments . 60 match , the three - dimensional material will be strained even before any applied physical distortion . For example , when a DETAILED DESCRIPTION layer of germanium is applied to a silicon wafer, the bond lengths of the germanium may strain to match the bond Embodiments of semiconductor assemblies , and related lengths of the silicon . In such arrangements , subsequent integrated circuit devices and techniques , are disclosed 65 physical distortion may cause the three - dimensional mate herein . In some embodiments , a semiconductor assembly rial to fail or have dramatic performance changes . The may include a flexible substrate , a first barrier formed of a magnitude of this mismatch strain may increase as the US 9 ,748 ,371 B2 thickness of the applied three -dimensional material disclosure . Therefore , the following detailed description is decreases. Consequently , in conventional three - dimensional not to be taken in a limiting sense , and the scope of materials , the ability to stack these materials may be limited embodiments is defined by the appended claims and their by the defects caused by bond length and lattice mismatches . equivalents . However, because of the weak ( non - chemical) interaction 5 Various operations may be described as multiple discrete between two -dimensional layers of TMD materials , a two - actions or operations in turn , in a manner that is most helpful dimensional layer of a TMD material may not seek to form in understanding the claimed subject matter. However , the matched bonds with the underlying substrate , and therefore order of description should not be construed as to imply that TMD materials may be readily stacked on other materials these operations are necessarily order dependent. In particu having lattice structures different from the TMD material. 10 lar, these operations may not be performed in the order of Because individual two - dimensional layers of a TMD presentation . Operations described may be performed in a material are weakly bonded with the other two -dimensional different order than the described embodiment. Various layers , it is possible to obtain and utilize a TMD material additional operations may be performed and /or described having a single - layer thickness . Various electrical properties operations may be omitted in additional embodiments . of the TMD material, such as the bandgap of the TMD 15 For the purposes of the present disclosure , the phrase " A material, may be tuned by adjusting the number of layers of and / or B ” means ( A ) , ( B ) , or ( A and B ) . For the purposes of the TMD material. Additionally, because some TMD mate the present disclosure , the phrase " A , B , and / or C ” means rials exhibit properties similar to a metal and some TMD (A ), (B ), (C ), ( A and B ), ( A and C ), ( B and C ), or ( A , B and materials exhibit (tunable ) semiconducting properties, a C ) . wide variety of electronic structures may be built entirely or 20 The description uses the phrases “ in an embodiment, ” or largely from various TMD materials ( e . g ., quantum wells ) . “ in embodiments , " which may each refer to one or more of Thus, the performance advantages of TMD materials ) may the same or different embodiments . Furthermore , the terms be applied to some or all components of various electronic " comprising, ” “ including, " " having ,” and the like , as used devices . In particular, devices are described herein in which with respect to embodiments of the present disclosure, are components other than or in addition to a transistor channel 25 synonymous . are formed from TMD materials . In some embodiments , FIG . 1 is a cross- sectional view of a semiconductor remote doping techniques may improve the mobility of assembly 100 including one or more TMD materials , in TMD materials used in channels of semiconductor assem - accordance with various embodiments . The semiconductor blies . Remote doping techniques may provide carriers in a assembly 100 may include a number of components , dis channel ( e . g . , in a quantum well) while putting impurities in 30 cussed below , one or more of which may be formed from a the channel in a remote location , thereby removing the TMD material. In some embodiments , all of the conducting impurities from the channel. Since impurities tend to induce and semiconducting components of the semiconductor scattering of carriers, which decreases the carrier speed , assembly 100 illustrated in FIG . 1 may be formed from a remote doping may enable an increase in the mobility of TMD material. carriers in the channel at higher doping levels . 35 The particular structure of the semiconductor assembly Various embodiments of the semiconductor assemblies 100 may be suitably used as a transistor, but the TMD disclosed herein may also exhibit improved electrical per - material- based techniques and assemblies disclosed herein formance over the organic or amorphous materials conven - are not limited to transistors or to the particular transistor tionally used with flexible substrates. For example , typical structure shown in FIG . 1 , but may be used to form any organic semiconductors typically have mobilities of 40 suitable IC component ( e . g ., transistors having any suitable approximately 0 . 1 - 1 centimeters squared per volt second architecture , or IC components formed using conventional Various embodiments of the TMD materials included in the three -dimensional semiconductor materials ). semiconductor assemblies disclosed herein may have The semiconductor assembly 100 may include a flexible mobilities of approximately 100 to 300 centimeters squared substrate 102. In some embodiments , the flexible substrate per volt second . These mobilities may be achieved for TMD 45 102 may be formed from a plastic material. The flexible materials having a single layer or a small number of layers ; substrate 102 may be formed from any flexible substrate by contrast , very thin layers of silicon may have mobilities material desirable for flexible electronic applications. For of less than 100 centimeters squared per volt second . example , in some embodiments , the flexible substrate 102 Although semiconductor assemblies with TMD materials may be formed from one or more of polyethylene terephtha are discussed principally herein , other two - dimensional 50 late , polyethylene naphthalate , polycarbonate material , materials may be used instead of or in addition to TMD polyethersulfone material, polyimide material , or alkali - free materials . Examples of such materials include grapheme and borosilicate . In some embodiments , the flexible substrate boron nitride . The two - dimensional nature of these materials 202 may be an amorphous material ( e . g . , one whose con may provide some of the structural advantages discussed stituent molecules are not arranged regionally or wholly in above with reference to the two - dimensional nature of TMD 55 a regular pattern ) . Although the use of flexible substrates materials , and may exhibit various electrical or other prop may be advantageous in a number of applications, the TMD erties that may make them appropriate for some applica - material -based techniques and assemblies disclosed herein tions . Thus, embodiments of the semiconductor assemblies need not include a flexible substrate ( such as the flexible disclosed herein may be formed with non - TMD two - dimen - substrate 102 ), but may be formed on a rigid substrate ( e . g . , sional materials . 60 a conventional wafer substrate or any other substrate ) . In the following detailed description , reference is made to The semiconductor assembly 100 may include a barrier the accompanying drawings , which form a part hereof 104 . In some embodiments , the barrier 104 may be disposed wherein like numerals designate like parts throughout, and on the flexible substrate 102. The barrier 104 may be formed in which is shown by way of illustration embodiments that from a TMD material. TMD material suitable for use of the may be practiced . It is to be understood that other embodi- 65 barrier 104 may include those TMD materials that have ments may be utilized and structural or logical changes may electronic characteristics of semiconductor materials . For be made without departing from the scope of the present example , the transistor channel 110 may be formed of US 9 ,748 ,371 B2 , , molybde The barrier 112 may be formed from a TMD material. In num ditelluride , tungsten disulfide , , or some embodiments , the barrier 112 may be formed from a tungsten ditelluride. TMD material that has a bandgap that is greater than a The semiconductor assembly 100 may include a transistor bandgap of the transistor channel 110 (which may also be channel 110 . In some embodiments , the barrier 104 may be 5 formed from a TMD material) . Thus , in some embodiments , disposed between the transistor channel 110 and the flexible both the barrier 104 and the barrier 112 may have bandgaps substrate 102 in a direction 120 . In some embodiments , the that are greater than a bandgap of the transistor channel 110 . transistor channel 110 may be disposed on the barrier 104 . In some embodiments , the barrier 104 and the barrier 112 The transistor channel 110 may be formed from a TMD may be formed of a same TMD material. In some embodi material. TMD material suitable for use of the transistor 10 ments, the barrier 104 and the barrier 112 may have approxi channel 110 may include those TMD materials that have mately the same bandgap . In embodiments in which the electronic characteristics of semiconductor materials , such barrier 112 is formed of a TMD material , the TMD material as those materials discussed above with reference to the for the barrier 112 may be selected in accordance with any barrier 104 . In some embodiments, the transistor channel of the embodiments discussed above with reference to the 110 may be a single layer of a TMD material . Single layers 15 barrier 104 . of TMD materials may have different electronic properties In some embodiments , the barrier 104 , the transistor than multiple - layer ( or " bulk ” ) arrangements . In particular, channel 110 and the barrier 112 may form a quantum well. the bandgap ( e . g . , the energy difference between the top of The quantum well may be a potential well with only discrete the valence band and the bottom of the conduction band ) of energy values . Because the barrier 104 and the barrier 112 single -layer TMD materials may be greater than the bandgap 20 may have larger bandgaps than the transistor channel 110 , ofmultiple - layer TMD materials . For example , the bandgap mobile charges may “ fall ” from the barrier 104 and the of single - layer molybdenum disulfide may be 1. 8 electron barrier 112 into the transistor channel 110 ( the lower energy volts , while the bandgap of multiple - layer molybdenum state ). disulfide may be 1 . 2 electron volts . The semiconductor assembly 100 may include a transistor In some embodiments , the barrier 104 may be formed 25 source 106 and a transistor drain 108 . In some embodiments , from a TMD material that has a bandgap that is greater than the transistor channel 110 may be disposed between the a bandgap of the transistor channel 110 (which may also be transistor source 106 and the transistor drain 108 in a formed from a TMD material) . A number of embodiments direction 122 (which may be perpendicular to the direction discussed herein will be discussed with reference to a pair of 120 ) . In particular, the transistor channel 110 may be in components having different bandgaps . Approximate band - 30 contact with the transistor source 106 and the transistor drain gaps of various TMD materials are listed below in Table 1 . 108 at the sides 124 so that current may flow through the In any embodiment in which two different components ( e . g ., transistor source 106 , the transistor channel 110 and the two different components of the semiconductor assembly transistor drain 108 . In some embodiments, the barrier 112 100 ) are described as having different bandgaps , the com - may be disposed between the transistor source 106 and the ponents may be formed respectively of different materials 35 transistor drain 108 in the direction 122 . In some embodi from Table 1 , selected so that the relative bandgaps are as ments , the transistor source 106 and / or the transistor drain desired . For example , if the barrier 104 is to be formed from 108 may be disposed on the barrier 104 . The transistor a TMD material that has a bandgap that is greater than a source 106 and / or the transistor drain 108 may be formed bandgap of the transistor channel 110 , the transistor channel from a TMD material. 110 may be formed from single - layer molybdenum disele - 40 In some embodiments , the transistor source 106 and the nide and the barrier 104 may be formed from single -layer transistor drain 108 may be formed of a same TMD material . molybdenum disulfide . Any combination of the materials TMD materials suitable for use as the transistor source 106 listed in Table 1 is contemplated , with various combinations and /or the transistor drain 108 may include those TMD suitable for various applications ( e . g ., depending upon band materials that have electronic characteristics of semiconduc gap specifications ). 45 tor materials (e . g ., those materials discussed above with reference to the transistor channel 110 ) . In some embodi TABLE 1 ments , the transistor source 106 and the transistor drain 108 may have approximately the same bandgap . TMD materials and approximate bandgaps. In some embodiments , the transistor source 106 and /or Approximate bandgap 50 the transistor drain 108 may be formed from TMD materials Material ( electron volts ) that have bandgaps that are less than a bandgap of the barrier , bulk 1 . 0 112 and also less than a bandgap of the barrier 104 . In some Molybdenum ditelluride , single layer 1 . 1 embodiments , the transistor source 106 and / or the transistor Tungsten ditelluride, single layer 1 . 1 drain 108 may be formed from TMD materials that have Molybdenum diselenide , bulk 1 . 1 bandgaps that are greater than a bandgap of the transistor Molybdenum disulfide, bulk 1 . 2 Tungsten diselenide , bulk channel 110 . In some such embodiments , the transistor Tungsten disulfide , bulk AN source 106 and / or the transistor drain 108 may be formed Molybdenum diselenide, single layer HARRA1. 5 from a multiple - layer TMD material while the transistor Tungsten diselenide , single layer 1 . 7 channel 110 may be formed from a single - layer version of Molybdenum disulfide , single layer 1. 8 60 the same TMD material . For example , the transistor channel Tungsten disulfide, single layer 1 . 9 - 2 . 1 110 may be formed of single - layer molybdenum diselenide , molybdenum disulfide, molybdenum ditelluride, tungsten The semiconductor assembly 100 may include a barrier disulfide , or tungsten diselenide, and the transistor source 112 . In some embodiments , the transistor channel 110 may 106 and the transistor drain 108 may be formed from be disposed between the barrier 112 and the barrier 104 in 65 multiple - layer molybdenum diselenide, molybdenum disul the direction 120 . In some embodiments , the barrier 112 may fide , molybdenum ditelluride , tungsten disulfide or tungsten be disposed on the transistor channel 110 . diselenide , respectively . By using smaller bandgap materials US 9 ,748 ,371 B2 for the transistor source 106 ( and /or the transistor drain 108 ) , formed of any of the materials discussed above with refer the contact resistance between the transistor source 106 ence to the source conductive contact 116 and the drain ( and /or the transistor drain 108 ) and any conductive contacts conductive contact 118 , for example . ( e . g . , the conductive contacts 116 and 118 discussed below ) FIGS . 2 - 7 are side views of various stages in a process for may be reduced , thereby reducing electrical losses as signals 5 manufacturing the semiconductor assembly 100 , in accor flow through the interface between the conductive contacts dance with various embodiments . In these stages , a number and the transistor source 106 (and /or the transistor drain 108 ). of materials ( e. g ., TMD materials ) are described as depos In some embodiments , the bandgaps of the barrier 104 ited . Various deposition techniques may be used as suitable and the barrier 112 may be greater than the bandgaps of the 10 at any of these stages . For example , in some embodiments , transistor source 106 and the transistor drain 108 , and the a tape method may be used to deposit TMD material ( e . g . , bandgaps of the transistor source 106 and the transistor drain the TMD material of the transistor channel 110 or any of the 108 may be greater than the bandgap of the transistor other components of the semiconductor assembly 100 ). In a channel 110 . In such embodiments , mobile charges may tape method , an adhesive tape may be attached to a bulk “ fall” from the barrier 104 , the barrier 112 , the transistor 15 formation of the desired TMD material (e . g . , a three -dimen source 106 and the transistor drain 108 into the transistor sional formation including multiple two- dimensional layers channel 110 ( the lower energy state ). For example , the of TMD material weakly bonded between layers ). The barriers 104 and 112 may be formed of multiple - layer strength of the adhesive may be selected so that , when the molybdenum disulfide , the transistor source 106 and drain tape is peeled away from the bulk formation , the interlayer 108 may be formed from multiple - layer molybdenum dis - 20 bonding strength may be over, and a desired number of elenide, and the transistor channel 110 may be formed from layers of the TMD material may be removed with the tape . single - layer molybdenum diselenide . In some embodiments . The desired number oflayers of the TMD material may then the transistor source 106 and /or the transistor drain 108 may be applied to the surface on which they are to be deposited , not be formed of a TMD material (and instead , e . g ., may be and a solvent may be used to dissolve the tape away. formed of another semiconductor material) . 25 FIG . 2 depicts an assembly 200 formed after a flexible The semiconductor assembly 100 may include a source substrate 102 is provided . The flexible substrate 102 may conductive contact 116 and a drain conductive contact 118 . take the form of any of the corresponding embodiments The transistor source 106 may be disposed between the source conductive contact 116 and the barrier 104 in the discussed above with reference to FIG . 1 . For example , in direction 120 . The transistor drain 108 may be disposed 30 some embodiments , the flexible substrate 102 may be a between the drain conductive contact 118 and the barrier 104 plastic material. The flexible substrate 102 may have an in the direction 120 . The source conductive contact 116 may exposed surface 202 . be disposed on the transistor source 106 . The drain conduc FIG . 3 depicts an assembly 300 formed after a material is tive contact 118 may be disposed on the transistor drain 108 . deposited on the surface 202 of the flexible substrate 102 to In use . current may flow between the source conductive 35 form a barrier 104 . The barrier 104 may take the form of any contact 116 , the transistor source 106 , the transistor channel of the corresponding embodiments discussed above with 110 , the transistor drain 108 and the drain conductive contact reference to FIG . 1 . The barrier 104 may have an exposed 118 . surface 302 . In some embodiments , the source conductive contact 116 FIG . 4 depicts an assembly 400 formed after a material is and the drain conductive contact 118 may be formed of a 40 deposited on the surface 302 of the barrier 104 to form a same TMD material. TMD materials suitable for use as the transistor channel 110 . The transistor channel 110 may take source conductive contact 116 and /or the drain conductive the form of any of the corresponding embodiments dis contact 118 may include those TMD materials that have cussed above with reference to FIG . 1 . The transistor chan electronic characteristics substantially similar to those of nel 110 may have an exposed surface 402 . metals . For example , the source conductive contact 116 45 FIG . 5 depicts an assembly 500 formed after a material is and / or the drain conductive contact 118 may be formed of deposited on the surface 402 of the transistor channel 110 to niobium disulfide , , niobium ditelluride, form a barrier 112 . The barrier 112 may take the form of any disulfide , tantalum diselenide , and /or tantalum of the corresponding embodiments discussed above with ditelluride . In some embodiments , the source conductive reference to FIG . 1 . contact 116 and/ or the drain conductive contact 118 may not 50 FIG . 6 depicts an assembly 600 formed after a material is be formed of a TMD material ( and instead , e. g . , may be deposited on the surface 302 of the barrier 104 to form a formed of a metal or other conductive material) . transistor source 106 , and after material is deposited on the The semiconductor assembly 100 may include a gate surface 302 of the barrier 104 to form a transistor drain 108 . conductive contact 114 . Voltage applied to the gate conduc - The transistor source 106 and the transistor drain 108 may tive contact 114 may regulate the amount of current flow 55 take the form of any of the corresponding embodiments between the source conductive contact 116 and the drain discussed above with reference to FIG . 1 . The transistor conductive contact 118 (via the transistor channel 110 ). The source 106 may have an exposed surface 602 , the transistor barrier 112 may be disposed between the gate conductive drain 108 may have an exposed surface 604 and the barrier contact 114 and the transistor channel 110 in the direction 112 may have an exposed surface 606 . 120 . In some embodiments, the gate conductive contact may 60 FIG . 7 depicts the semiconductor assembly 100 formed be disposed on the barrier 112 . In some embodiments , the after a material is deposited on the surface 602 of the gate conductive contact 114 may be disposed between the transistor source 106 to form the source conductive contact transistor source 106 and the transistor drain 108 in the 116 , after material is deposited on the surface 604 of the direction 122 . In some embodiments , the gate conductive transistor drain 108 to form the drain conductive contact contact 114 may be disposed between the source conductive 65 118 , and after material is deposited on the surface 606 of the contact 116 and the drain conductive contact 118 in the barrier 112 to form the gate conductive contact 114 . The direction 122 . The gate conductive contact 114 may be source conductive contact 116 , the drain conductive contact US 9 ,748 ,371 B2 10 118 and the gate conductive contact 114 may take the form example , planar and non -planar transistors such as dual- or of any of the corresponding embodiments discussed above double - gate transistors , tri- gate transistors , and all - around with reference to FIG . 1 . gate (AAG ) or wrap -around gate transistors, some of which The semiconductor assemblies disclosed herein (such as may be referred to as FinFETs ( Field Effect Transistors ) . In the semiconductor assembly 100 ) may be used in a device 5 some embodiments , the device layer 818 may include one or layer in electrical and /or optical circuit devices . Various more transistors or memory cells of a logic device or a devices, such as transistors, may be formed using TMD memory device , or combinations thereof. In some embodi materials in a manner analogous to conventional semicon ments , the device layer 818 may include optical devices . ductor circuit manufacture techniques ( e . g ., those performed Some or all of the transistors or other devices included in the on silicon or other semiconductor wafers ) and may be 10 device layer 818 may be formed partially or entirely from included in otherwise conventional IC circuitry . For TMD materials . example , the semiconductor assembly 100 may be included Electrical signals such as, for example , power and / or in a device layer of an IC device ( e . g . , as discussed below input / output ( I /O ) signals may be routed to and /or from the with reference to FIG . 8 ) . In embodiments in which the transistor ( s ) 808 of the device layer 818 through one or more semiconductor assembly 100 includes a flexible substrate 15 interconnect layers 820 and 822 disposed on the device layer 102 , the semiconductor assembly 200 may be able to bend 818 . For example, electrically conductive features of the and otherwise to form in a manner not achievable by device layer 818 such as, for example , the gate 812 and S / D conventional rigid substrates ( such as silicon wafers ) . Thus, contacts 814 may be electrically coupled with the intercon the range of applications of certain of the semiconductor nect structures 816 of the interconnect layers 820 and 822 assemblies disclosed herein may be broader than the range 20 ( e . g ., the source conductive contact 116 , the gate conductive of applications of conventional rigid circuits. contact 114 and the drain conductive contact 118 ) . The The semiconductor assemblies may provide improved interconnect structures 816 may be configured within the performance at smaller scales as compared to assemblies interconnect layers 820 and 822 to route electrical signals with conventional materials . For example , as the lateral according to a wide variety of designs and are not limited to dimensions e . g . , the direction 122 ) of transistor devices 25 the particular configuration of interconnect structures 816 decrease , transistor channels must typically be made center depicted in FIG . 8 . For example , in some embodiments, the in order to mitigate problematic short channel effects . How - interconnect structures 816 may include trench structures ever , as discussed above, single layers of conventional ( sometimes referred to as " lines" ) and / or via structures materials may exhibit mechanical and electrical perfor ( sometimes referred to as " holes” ) filled with an electrically mance weaknesses . However, due to the “ true ” two -dimen - 30 conductive material such as a metal. In some embodiments , sional nature of the layers of TMD materials , single - layer the interconnect structures 816 may comprise copper or TMD materials may be achieved . Such materials may have another suitable electrically conductive material. In some a thickness on the order of one nanometer, and may repre - embodiments , optical signals may be routed to and /or from sent a minimum achievable thickness for transistor channels . the device layer 818 instead of or in addition to electrical Such single - layer TMD materials and other TMD materials 35 signals . with small numbers of layers) may provide both physical The interconnect layers 820 and 822 may include the performance and electrical performance improvements over dielectric layer 824 disposed between the interconnect struc thin layers of conventional semiconductor materials . tures 816 , as can be seen . In some embodiments , a first The semiconductor assemblies and related techniques interconnect layer 820 (referred to as Metal 1 or “M1 ” ) may disclosed herein may be included in an IC device. FIG . 8 is 40 be formed directly on the device layer 818 . In some embodi a cross - sectional view of a portion of an IC device 800 ments , the first interconnect layer 820 may include some of including a device layer 818 (which may include one or the interconnect structures 816 , which may be coupled with more of the semiconductor assemblies disclosed herein ) , in contacts ( e . g . , the S / D contacts 814 ) of the device layer 818 . accordance with various embodiments. In some embodi- Additional interconnect layers (not shown for ease of ments , the IC device 800 may be a die (which may be 45 illustration , may be formed directly on the first interconnect produced , e . g . , in a batch of many dies on a substrate , then layer 820 and may include interconnect structures 816 to separated from other dies by cutting ) . couple with interconnect structures of the first interconnect The IC device 800 may be formed on a substrate 804 . The layer 820 . substrate 804 may include a flexible substrate material ( such The IC device 800 may have one or more bond pads 826 as the flexible substrate 102 ) or a rigid substrate material. 50 formed on the interconnect layers 820 and 822 . The bond In some embodiments , the IC device 800 may include a pads 826 may be electrically coupled with the interconnect device layer 818 disposed on the substrate 804 . The device structures 816 and configured to route the electrical signals layer 818 may include channels providing features of one or of transistor ( s ) 808 to other external devices . For example , more transistors 808 formed on the substrate 804 . The solder bonds may be formed on the one or more bond pads device layer 818 may include, for example , one or more 55 826 to mechanically and /or electrically couple a chip includ source and / or drain ( S / D ) 810 , a gate 812 to control current ing the IC device 800 with another component such as a flow in the transistor ( s ) 808 between the S / D regions 810 , circuit board . The IC device 800 may have other alternative and one or more S / D contacts 814 to route electrical signals configurations to route the signals from the interconnect to / from the S / D regions 810 . The transistor ( s ) 808 may layers 820 and 822 than depicted in other embodiments . In include additional features not depicted for the sake of 60 other embodiments , the bond pads 826 may be replaced by clarity , such as device isolation regions , gate contacts , and or may further include other analogous features ( e . g ., posts ) the like. In some embodiments , these features may be that route the signals to other external components . formed in accordance with any of the embodiments of these FIG . 9 is a flow diagram of a process 900 for forming an features discussed herein ( e . g . , with reference to FIG . 1 ) . IC device including a semiconductor assembly with TMD The transistor ( s ) 808 are not limited to the type and con - 65 materials , in accordance with various embodiments . In the figuration depicted in FIGS . 1 and 8 and may include a wide discussion of the process 900 below , many deposited mate variety of other types and configurations such as , for rials are described as being TMD materials . In some US 9 ,748 ,371 B2 12 embodiments , one or more of the deposit materials may not the operations of 912 may be performed by an entity be TMD materials , as desired , and may instead be conven different from an entity that performs the operations of tional semiconductor and /or metalmaterials . The operations 902- 910 . of the process 900 may be discussed below with reference to FIG . 10 schematically illustrates a computing device 1000 the semiconductor assembly 100 (FIG . 1 ) , but this is simply 5 that may include one or more of the semiconductor assem for ease of illustration and the process 900 may be applied blies 100 disclosed herein , in accordance with various so as to form any suitable IC device . In some embodiments , embodiments . In particular , substrates of any suitable ones the process 900 may be performed to manufacture an IC of the components of the computing device 1000 may include the semiconductor assemblies 100 disclosed herein . device included in the computing device 1000 discussed 10 The computing device 1000 may house a board such as below with reference to FIG . 10 . Various operations of the motherboard 1002 . The motherboard 1002 may include a process 900 may be repeated , rearranged , or omitted as number of components , including but not limited to a suitable . processor 1004 and at least one communication chip 1006 . At 902 , a TMD material may be deposited on a flexible The processor 1004 may be physically and electrically substrate to form a first barrier. The first barrier of 902- may 15 coupled to the motherboard 1002 . In some implementations , take the form of any of the embodiments of the barrier 104 , the at least one communication chip 1006 may also be for example . physically and electrically coupled to the motherboard 1002 . At 904 , a TMD material may be deposited on the first In further implementations , the communication chip 1006 barrier to form a transistor channel. The transistor channel of may be part of the processor 1004 . The term " processor ” 904 may take the form of any of the embodiments of the 20 may refer to any device or portion of a device that processes transistor channel 110 , for example . The transistor channel electronic data from registers and / or memory to transform of 904 may be formed such that the first barrier of 902 is that electronic data into other electronic data that may be disposed between the transistor channel of 904 and the stored in registers and / or memory . flexible substrate of 902 . In some embodiments , a bandgap Depending on its applications, computing device 1000 of the first barrier of 902 may be greater than a bandgap of 25 may include other components that may or may not be the transistor channel of 904 . physically and electrically coupled to the motherboard 1002. At 906 , a TMD material may be deposited on the tran - These other components may include , but are not limited to , sistor channel to form a second barrier. The second barrier volatile memory ( e . g . , dynamic random access memory ) , of 906 may take the form of any of the embodiments of the non - volatile memory ( e . g ., read - only memory ) , flash barrier 112 , for example . The second barrier of 906 may be 30 memory, a graphics processor, a digital signal processor, a formed such that the transistor channel of 904 is disposed crypto processor, a chipset , an antenna, a display, a touch between the second barrier of 906 and the first barrier of 902 . screen display, a touchscreen controller , a battery , an audio In some embodiments , a bandgap of the second barrier of codec , a video codec , a power amplifier, a global positioning 906 may be greater than a bandgap of the transistor channel system (GPS ) device , a compass, a Geiger counter, an of 904 . 35 accelerometer , a gyroscope, a speaker, a camera , and a mass At 908 , TMD materials may be deposited on the first storage device (such as hard disk drive, compact disk (CD ) , barrier of 904 to form a transistor source and a transistor digital versatile disk (DVD ), and so forth ) . drain . The transistor source and the transistor drain of 908 The communication chip 1006 may enable wireless com may take the form of any of the embodiments of the munications for the transfer of data to and from the com transistor source 106 and the transistor drain 108 , respec - 40 puting device 1000 . The term " wireless ” and its derivatives tively, for example . The transistor source and the transistor may be used to describe circuits , devices , systems, methods , drain of 908 may be disposed so as to be in contact with techniques , communications channels , etc . , that may com opposite sides of the transistor channel of 904 ( e . g . , as municate data through the use of modulated electromagnetic shown in FIG . 1 ) . radiation through a non - solid medium . The term does not At 910 , TMD materials may be deposited on the transistor 45 imply that the associated devices do not contain any wires, source and the transistor drain of 908 and the second barrier although in some embodiments they might not. The com of 906 to form a source conductive contact, a drain conduc - munication chip 1006 may implement any of a number of tive contact and a gate conductive contact, respectively . The wireless standards or protocols , including but not limited to source conductive contact, the drain conductive contact and Institute for Electrical and Electronic Engineers ( IEEE ) the gate conductive contact of910 may take the form of any 50 standards including Wi- Fi ( IEEE 802. 11 family ) , IEEE of the embodiments of the source conductive contact 116 , 802 . 16 standards ( e . g . , IEEE 802 . 16 - 2005 Amendment ) , the drain conductive contact 118 and the gate conductive Long - Term Evolution (LTE ) project along with any amend contact 114 , respectively , for example . In some embodi m ents , updates , and / or revisions ( e . g ., advanced LTE proj ments, the semiconductor assembly 100 may be formed ect, ultra mobile broadband (UMB ) project (also referred to upon the completion of 910 . 55 as 3GPP2 ) , etc . ) . IEEE 802 . 16 compatible Broadband Wire At 912 , one or more interconnects may be formed to route less Access (BWA ) networks are generally referred to as signals to and / or from the semiconductor assembly 100 . The WiMAX networks, an acronym that stands for Worldwide interconnects formed at 912 may route electrical, optical Interoperability for Microwave Access, which is a certifi and / or any other suitable signals to and /or from the semi- cation mark for products that pass conformity and interop conductor assembly 100 . The interconnects formed at 912 60 erability tests for the IEEE 802 . 16 standards . The commu may take the form of the interconnect structures 816 dis - nication chip 1006 may operate in accordance with a Global cussed above with reference to FIG . 8 , for example . The System for Mobile Communication (GSM ), General Packet process 900 may then end . Radio Service (GPRS ) , Universal Mobile Telecommunica As noted above, in some embodiments , one or more of the tions System (UMTS ) , High Speed Packet Access (HSPA ) , operations of the process 900 illustrated in FIG . 9 may be 65 Evolved HSPA ( E -HSPA ), or LTE network . The communi omitted . For example , in some embodiments , the operations cation chip 1006 may operate in accordance with Enhanced of 908 - 912 may not be performed . In some embodiments , Data for GSM Evolution (EDGE ), GSM EDGE Radio US 9 ,748 ,371 B2 13 14 Access Network (GERAN ), Universal Terrestrial Radio direction , a transistor source formed of a fourth TMD Access Network (UTRAN ), or Evolved UTRAN material and a transistor drain formed of a fifth TMD ( E -UTRAN ). The communication chip 1006 may operate in material . accordance with Code Division Multiple Access (CDMA ) , Example 4 may include the subject matter of Example 3 , Time Division Multiple Access ( TDMA ), Digital Enhanced 5 and may further specify that the second barrier is disposed Cordless Telecommunications (DECT ) , Evolution -Data between the transistor source and the transistor drain in the Optimized ( EV - DO ) , derivatives thereof, as well as any second direction . other wireless protocols that are designated as 3G , 4G , 5G , Example 5 may include the subject matter of any of and beyond . The communication chip 1006 may operate in Examples 3 - 4 , and may further include: a source conductive accordance with other wireless protocols in other embodi- contact formed of a sixth TMD material; and a drain ments . conductive contact formed of a seventh TMD material; The computing device 1000 may include a plurality of wherein the transistor source is disposed between the source communication chips 1006 . For instance , a first communi - conductive contact and the first barrier in the first direction , cation chip 1006 may be dedicated to shorter range wireless and the transistor drain is disposed between the drain communications such as Wi- Fi and Bluetooth and a second conductive contact and the first barrier in the first direction . communication chip 1006 may be dedicated to longer range Example 6 may include the subject matter of Example 5 , wireless communications such as GPS , EDGE , GPRS , and may further specify that the second barrier is disposed CDMA , WiMAX , LTE , EV - DO , and others. between the transistor source and the transistor drain in the The communication chip 1006 may also include an IC20 second direction . package assembly that may include a semiconductor assem Example 7 may include the subject matter of any of bly as described herein . In further implementations, another Examples 5 -6 , and may further specify that the sixth TMD component ( e . g ., memory device , processor or other inte material and the seventh TMD material are a same TMD grated circuit device ) housed within the computing device material. 1000 may contain a semiconductor assembly as described 25 Example 8 may include the subject matter of any of herein . Examples 3 - 7 , and may further specify that the transistor In various implementations, the computing device 1000 source is formed of multiple layers of the fourth TMD may be a laptop , a netbook , a notebook , an ultrabook , a material and the transistor drain is formed of multiple layers smartphone , a tablet, a personal digital assistant ( PDA ) , an of the fifth TMD material. ultra mobile PC , a mobile phone , a desktop computer , a 30 Example 9 may include the subject matter of any of server, a printer, a scanner , a monitor, a set- top box , an Examples 3 - 8 , and may further specify that the bandgaps of entertainment control unit, a digital camera , a portable music the first barrier and the second barrier are both greater than player, or a digital video recorder. In further implementa a bandgap of the transistor source and both greater than a tions , the computing device 1000 may be any other elec - bandgap of the transistor drain . tronic device that processes data . In some embodiments , the 35 Example 10 may include the subject matter of any of techniques described herein are implemented in a high - Examples 3 - 9 , and may further specify that the fourth TMD performance computing device . In some embodiments, the material and the fifth TMD material are a same TMD techniques described herein are implemented in handheld material. computing devices. In some embodiments , the techniques Example 11 may include the subject matter of any of described herein may be implemented in a wearable com - 40 Examples 1 - 10 , and may further include a gate conductive puting device . In particular, the wearable computing device contact formed of a fourth TMD material, wherein the may include a flexible substrate ( e . g . , a rubber or other second barrier is disposed between the gate conductive flexible wrist band ) and one or more flexible circuit com - contact and the transistor channel. ponents constructed in accordance with various ones of the Example 12 may include the subject matter of any of techniques disclosed herein . 45 Examples 1 - 11, and may further specify that the first TMD The following paragraphs provide a number of examples material and the third TMD material are a same TMD of the embodiments disclosed herein . Example 1 is a semi material. conductor assembly , including : a flexible substrate ; a first Example 13 is a method of forming a semiconductor barrier formed of a first TMD material; a transistor channel assembly, including : depositing a first TMD material on a formed of a second TMD material; and a second barrier 50 first surface of a flexible substrate to form a first barrier ; formed of a third TMD material; wherein the first barrier is depositing a second TMD material on the first barrier to disposed between the transistor channel and the flexible form a transistor channel ; and depositing a third TMD substrate , the transistor channel is disposed between the material on the transistor channel to form a second barrier ; second barrier and the first barrier, and a bandgap of the wherein the first barrier is disposed between the transistor transistor channel is less than a bandgap of the first barrier 55 channel and the flexible substrate , the transistor channel is and less than a bandgap of the second barrier. disposed between the second barrier and the first barrier , and Example 2 may include the subject matter of Example 1 , a bandgap of the transistor channel is less than a bandgap of and may further specify that the transistor channel formed of the first barrier and less than a bandgap of the second barrier. the second TMD material is a single layer of the second Example 14 may include the subject matter of Example TMD material. 60 13 , and may further specify that the flexible substrate is a Example 3 may include the subject matter of any of plastic substrate . Examples 1 - 2 , and may further specify that : the first barrier Example 15 may include the subject matter of any of is disposed between the transistor channel and the flexible Examples 13 - 14 , and may further specify that depositing the substrate in a first direction ; the transistor channel is dis - second TMD material comprises using a tape method . posed between the second barrier and the first barrier in the 65 Example 16 may include the subject matter of any of first direction ; and the transistor channel is disposed Examples 13 - 15 , and may further include depositing a between , in a second direction perpendicular to the first fourth TMD material to form a gate conductive contact such US 9 ,748 ,371 B2 15 16 that the second barrier is disposed between the gate con the transistor channel is disposed between the second ductive contact and the transistor channel. barrier and the first barrier in the first direction ; and Example 17 may include the subject matter of any of the transistor channel is disposed between , in a second Examples 13 - 16 , and may further specify that the first TMD direction perpendicular to the first direction , a transistor material and the third TMD material are a same TMD 5 source formed of a fourth TMD material and a transis material . tor drain formed of a fifth TMD material. Example 18 is an IC device, including a device layer 4 . The semiconductor assembly of claim 3 , wherein the including : a flexible substrate , a first barrier formed of a first TMD material, a transistor channel formed of a second TMD second barrier is disposed between the transistor source and material, a second barrier formed of a third TMD material, 10 the transistor drain in the second direction . a transistor source formed of a fourth TMD material , and a 5 . The semiconductor assembly of claim 3 , further com transistor drain formed of a fifth TMD material, wherein the prising: first barrier is disposed between the transistor channel and a source conductive contact formed of a sixth TMD the flexible substrate in a first direction , the transistor material; and channel is disposed between the second barrier and the first 15 a drain conductive contact formed of a seventh TMD barrier in the first direction , a bandgap of the transistor material; channel is less than a bandgap of the first barrier and less wherein the transistor source is disposed between the than a bandgap of the second barrier, the transistor channel source conductive contact and the first barrier in the is disposed between the transistor source and the transistor first direction , and the transistor drain is disposed drain formed in a second direction perpendicular to the first 20 between the drain conductive contact and the first direction . The IC device may also include one or more barrier in the first direction . interconnects to route electrical signals to and / or from the 6 . The semiconductor assembly of claim 5 , wherein the transistor source and the transistor drain . second barrier is disposed between the transistor source and Example 19 may include the subject matter of Example the transistor drain in the second direction . 18 , and may further specify that the device layer further 25 7 . The semiconductor assembly of claim 5 , wherein the includes : a gate conductive contact formed of a sixth TMD sixth TMD material and the seventh TMD material are a material ; a source conductive contact formed of a seventh same TMD material . TMD material , and a drain conductive contact formed of an 8 . The semiconductor assembly of claim 3, wherein the eighth TMD material ; wherein the second barrier is disposed transistor source is formed of multiple layers of the fourth between the gate conductive contact and the transistor 30 TM channel in the first direction , the transistor source is disposed 0 TMD material and the transistor drain is formed of multiple between the source conductive contact and the first barrier in layers of the fifth TMD material . the first direction , and the transistor drain is disposed 9 . The semiconductor assembly of claim 3 , wherein the between the drain conductive contact and the first barrier in bandgaps of the first barrier and the second barrier are both the first direction . greater than a bandgap of the transistor source and both Example 20 may include the subject matter of Example greater than a bandgap of the transistor drain . 19, and may further specify thatat the sixthsixth TMD material , the 10 . The semiconductor assembly of claim 3 , wherein the seventh TMD material, and the eighth TMD material are a fourth TMD material and the fifth TMD material are a same same TMD material. TMD material. Example 21 may include the subject matter of Example 40 11 . The semiconductor assembly of claim 1 , further 20 , and may further specify that the same TMD material is comprising : niobium disulfide , niobium diselenide, niobium ditelluride , a gate conductive contact formed of a fourth TMD mate tantalum disulfide , tantalum diselenide, or tantalum ditellu rial; ride . wherein the second barrier is disposed between the gate Example 22 may include the subject matter of any of 45 conductive contact and the transistor channel . Examples 18 - 21 , and may further specify that the IC device 12. The semiconductor assembly of claim 1 , wherein the is a die . first TMD material and the third TMD material are a same What is claimed is : TMD material. 1 . A semiconductor assembly, comprising : 13 . A method of forming a semiconductor assembly , a flexible substrate ; 50 comprising: a first barrier formed of a first transition metal dichalco depositing a first transition metal dichalcogenide ( TMD ) genide ( TMD ) material; material on a first surface of a flexible substrate to form a transistor channel formed of a second TMD material ; a first barrier; and depositing a second TMD material on the first barrier to a second barrier formed of a third TMD material; 55 form a transistor channel ; and wherein the first barrier is disposed between the transistor depositing a third TMD material on the transistor channel channel and the flexible substrate , the transistor chan to form a second barrier; nel is disposed between the second barrier and the first wherein the first barrier is disposed between the transistor barrier , and a bandgap of the transistor channel is less channel and the flexible substrate , the transistor chan than a bandgap of the first barrier and less than a 60 nel is disposed between the second barrier and the first bandgap of the second barrier. barrier, and a bandgap of the transistor channel is less 2 . The semiconductor assembly of claim 1 , wherein the than a bandgap of the first barrier and less than a transistor channel formed of the second TMD material is a bandgap of the second barrier . single layer of the second TMD material. 14 . The method of claim 13 , wherein the flexible substrate 3 . The semiconductor assembly of claim 1 , wherein : 65 is a plastic substrate . the first barrier is disposed between the transistor channel 15 . The method of claim 13 , wherein depositing the and the flexible substrate in a first direction ; second TMD material comprises using a tape method . US 9 ,748 , 371 B2 17 18 16 . The method of claim 13 , further comprising : one or more interconnects to route electrical signals to depositing a fourth TMD material to form a gate conduc and /or from the transistor source and the transistor tive contact such that the second barrier is disposed drain . between the gate conductive contact and the transistor 19 . The IC device of claim 18 , wherein the device layer channel. 5 further comprises : 17 . The method of claim 13 , wherein the first TMD a gate conductive contact formed of a sixth TMD mate material and the third TMD material are a same TMD rial; material. a source conductive contact formed of a seventh TMD 18 . An integrated circuit ( IC ) device, comprising: material; and a device layer comprising: 10 a drain conductive contact formed of an eighth TMD a flexible substrate , material; a first barrier formed of a first transition metal dichal wherein the second barrier is disposed between the gate cogenide ( TMD ) material, conductive contact and the transistor channel in the first a transistor channel formed of a second TMD material , direction , the transistor source is disposed between the a second barrier formed of a third TMD material, source conductive contact and the first barrier in the a transistor source formed of a fourth TMD material, first direction , and the transistor drain is disposed and between the drain conductive contact and the first a transistor drain formed of a fifth TMD material, barrier in the first direction . wherein the first barrier is disposed between the tran 20 . The IC device of claim 19 , wherein the sixth TMD sistor channel and the flexible substrate in a first+ 2020 material , the seventh TMD material, and the eighth TMD direction , the transistor channel is disposed between material are a same TMD material. the second barrier and the first barrier in the first 21 . The IC device of claim 20 , wherein the same TMD direction , a bandgap of the transistor channel is less material is niobium disulfide, niobium diselenide, niobium than a bandgap of the first barrier and less than a ditelluride , tantalum disulfide, tantalum diselenide , or tan bandgap of the second barrier, the transistor channel 23 al is disposed between the transistor source and the 22 . The IC device of claim 18 , wherein the IC device is transistor drain formed in a second direction perpen a die . dicular to the first direction ; and * * * *