Lawrence Butcher Reports on Recent Developments in ECU Technology and Their Impact on Engine Design

The main circuit board from a programmable competition ECU. The appearance of SoC (system on chip) devices will see the size and complexity of these units fall

New chips on the block Lawrence Butcher reports on recent developments in ECU technology and their impact on engine design

n RET 46 (May 2010), we gave you a general overview of ECU These advances have led to design challenges, however, such as technology, looking at the overall design and implementation of packaging the growing number of I/Os effi ciently – an ever-present control processes in a modern internal combustion engine context. challenge in the space- and weight-conscious world of motorsport. The intention here is to expand on that, and investigate some of the Research into engine control systems is extensive, to say the least, Ikey advances in ECU design in recent years. so this article is not intended to be comprehensive, but hopefully it As the control of the internal combustion engine becomes ever will provide an insight into some areas of improvement that are not more advanced, with processes such as gasoline direct injection and immediately obvious to the casual observer. constantly variable valve timing becoming common, ECUs have had to evolve to cope with these extra demands. Key to meeting these Processors demands has been an increase in processing power and speed, which The heart of an ECU is one or more CPUs (central processing units), have allowed not only a greater capacity for input and output (I/O) which are responsible for carrying out the calculations required to run an data (see glossary page 68), but also faster and more accurate control engine, as well as tasks such as managing integration with other vehicle of an engine’s operating parameters. systems and controlling processes such as data logging. The software

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instructions for these tasks are generally stored on dedicated memory chips, and the CPUs ‘read’ the instructions in order to carry out the tasks. “One modern processor As engine control strategies become more complex, requiring ECUs to have a growing number of I/Os, it is inevitable that more computing would be able to fulfil the power will be needed to handle the additional data and calculations. As one ECU specialist comments, “It is always nice to have more processing power, but we never have trouble finding ways to use it roles of all the processors up.” In terms of improving processing capability in an ECU, both the power of the CPU and the way it is used are important. in a 1980s Formula One An engineer from a manufacturer of motorsport ECUs recounts taking a look at a 1980s Formula One unit. Inside it was a host of different processors, each handling an individual task, with another ECU many times over” standalone processor to coordinate them. Given the technology at the time, each processor would have had, compared to today, a very low clock speed – the rate at which a processor can complete a processing a time, so scheduling one task at the wrong point can slow down the cycle – of less than 1 MHz; by comparison, modern microprocessors completion of another. Improvements in the operating systems that run in ECUs will normally have a clock speed of anything up to 300 MHz, the processors now allow for tasks to be scheduled in such a way that meaning that one modern processor would be able to fulfil the roles of the power of a particular chip is used optimally, meaning that a single- these multiple processors many times over. core processor can perform more efficiently than ever, although this is To clarify, a processor’s clock speed is normally determined by the not always enough. Enter the dual-core processor. frequency of an oscillator crystal, which typically produces a fixed As its name suggests, a dual-core processor has two cores integrated sinusoidal waveform called the reference frequency signal. Electronic into a single chip. This means that different computing tasks can be circuitry translates it into a square wave of the same frequency (or, in a carried out in parallel by the same chip, without them interfering CPU multiplier, some fixed multiple of the reference frequency) and a with each other. While the chip may have the same ‘clock speed’ as distribution network inside the CPU then carries the wave to all parts a single-core unit, its processing power is now far superior. Chips are of the chip that need it. In this context, the use of the word ‘speed’ (as also available with more than two cores – the most powerful CPUs in physical movement) should not be confused with frequency or its used in high-performance computing applications can have anything corresponding clock speed. Thus, the term ‘clock speed’ or ‘processor up to eight – but in terms of those used in ECUs, dual cores are speed’ is a misnomer. the current norm (although some control units used in mainstream A processor is programmed to look after tasks in a prescribed order, production cars do feature more than two cores). meaning that prioritising functions is vital when writing the code that There are a number of ways to use the additional processing power controls them. A single-core chip can carry out only one calculation at of a dual-core chip. The most obvious is for dealing with what are known as ‘embarrassingly parallel’ tasks. In parallel computing, an embarrassingly parallel workload (or problem) is one for which little or no effort is required to separate the problem to be solved into a number of parallel tasks. This is often the case where there is no dependency (or communication) between the two parallel tasks. These tasks present a relatively simple proposition from a coding perspective, thanks to the programmer not having to worry too much about scheduling the tasks between cores. The second approach is to use both cores simultaneously, allowing for a greater number of software tasks to be processed more quickly. This, however, means that the scheduling of processor operations needs to be very carefully managed to ensure that the available processing power is used efficiently. This in turn means that programs need to be written specifically for parallel computing A 32-bit dual-core microcontroller similar to those operations, presenting a greater coding workload and used in the current generation of Formula One

ECUs (Courtesy of Freescale Semiconductor) a higher chance of creating bottlenecks in the throughput of data. t

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from a single core, its complexity must increase fourfold. In general, the increased complexity essentially equals the increase in power consumption. As shown in the chart (left), the lowest power consumption increase results from using two CPUs running at the same frequency. The other options of increasing the number of logic gates in a chip or increasing the frequency (speed) all result in higher power consumption. From a packaging This chart shows the relationship between the power consumption and performance of different arrangements of processors. Note that as the speed and number of logic gates increases on a and integration perspective, a dual-core processor provides the best single processor, the power consumption increases at a far greater rate than computing power compromise in terms of processing speed and power consumption. (Courtesy of Freescale Semiconductor)

Programmable chips Where a dual-core processor is used in this way, the two cores will An ECU receives a plethora of information about engine operating generally share a single memory source, on which the relevant parameters and other events on a car, such as data from wheel speed programming data is stored. sensors for traction control purposes. This information will generally Two areas where multi-core processors have really proved a benefit be in analogue form, often as a voltage value of 0-5 V in the case of to ECU designers is in the implementation of data logging and in most automotive sensors, which needs to be converted to digital form error checking of systems. While the importance of data logging will so that the CPU can use it. be covered in more detail below, the use of a dual-core processor That means using a signal processor and other data handling

makes its integration into an ECU more straightforward than with a devices, which in the past would always have been custom-made t single-core device. In an ECU with only one, single-core processor, the CPU would WHAT IS AN FPGA? be responsible for looking after the myriad of engine calculations as well as running the programming relating to data logging functions. A field-programmable gate array (FPGA) is a semiconductor With a dual-core CPU, engine operations can be dealt with by one device that can be programmed after manufacturing. Instead of core while the data logging can be handled by the other, while still being restricted to a predetermined hardware function, it allows providing the data logging program access to the memory address you to program product features and functions, adapt to new containing the engine programming data. Not only does this make standards and reconfigure hardware for specific applications even after the product has been installed ‘in the field’. The use of FPGAs for simpler task scheduling for the programmers, it also makes it less in ECUs is by no means universal, but at the very high end, where likely that the data logging operations will interfere with the general rapid development is often necessary, they are fairly common. engine operation. You can use an FPGA to implement any logical function that an Redundancy and safety-specific operations can also benefit from ASIC (see glossary) could perform, but the ability to update the functionality is the key benefit. Unlike previous-generation FPGAs, the capability provided by a dual-core processor. For example, which only used I/Os with programmable logic and interconnects, both cores of a CPU could be running the same program, with the modern FPGAs consist of various mixes of configurable results of each set of calculations being checked against each other embedded SRAM, high-speed transceivers, high-speed I/Os, for errors. Alternatively, different programs that produce the same logic blocks and routing. end result can be run on each core, with the results again being Specifically, an FPGA contains programmable logic components called logic elements (LEs) and a hierarchy of reconfigurable compared to check for errors. With the ever-increasing complexity interconnects that allow the LEs to be physically connected. You of the programming required with these chips, often leading to tens can configure LEs to perform complex combinational functions, or of thousands of lines of software code, it is inevitable that errors will just simple logic gates such as AND and XOR. In most FPGAs, the creep in. Therefore, having the ability to constantly self-diagnose is logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. an invaluable benefit in an ECU. As FPGAs continue to evolve, the devices have become Another factor that has to be considered when designing a CPU for more integrated. Hard intellectual property blocks – aspects of an ECU is its power consumption. With rising processor clock speed functionality proprietary to a specific manufacturer – built into the comes higher power consumption and complexity, and Pollack’s FPGA provide rich functions while lowering power and cost, and freeing up logic resources for product differentiation. Newer FPGA Rule for microprocessor performance states that the increase in families are being developed with hard embedded processors, performance is roughly proportional to the square root of the increase transforming them into fully fledged System on Chip devices. in complexity. In other words, in order to get twice the performance

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RET51_LifeRacing_FP.indd 1 15/03/2012 21:33 microprocessors, each with a dedicated function. Otherwise known GLOSSARY as ASICs (application-specific integrated circuits), these chips are purpose designed for a specific set of tasks, and are often still used ADC: Analogue-to-digital converter, a device to convert an in mass-production engine controllers, where the considerable initial analogue signal, such as a voltage reading, into a digital signal that cost and complexity of development is offset by the scale can be processed by the ECU. of production. Once built, however, ASICs cannot be reprogrammed and so they ANN: Artificial neural network, a computational model based on the structure and functions of biological neural networks. limit the adaptability of the ECU into which they are embedded. One Information that flows through the network affects the structure solution is to use field-programmable gate arrays (FPGAs, see sidebar, of the ANN because a neural network changes – or learns, in a page 66), which fulfil the role of an ASIC yet can be reprogrammed sense – according to that input and output. ANNs are considered after manufacture to perform specific tasks. They allow the load on the non-linear statistical data modelling tools where the complex relationships between inputs and outputs are modelled or patterns main CPU to be reduced, so that its power can be concentrated on the are found. core role of running the engine control programs. The power of modern processors means that more basic engine ASIC: Application-specific integrated circuit. ASICs are the control systems can rely on the CPU’s capacity to control them, but predecessors to FPGAs and more recently the System on Chip where the number of I/Os is very high, a lot of pre-processors are (SoC, see below) devices. They consist of an integrated circuit designed specifically to achieve a single task, such as processing needed. High-end motorsport ECUs therefore use FPGAs to deal a wheel speed sensor signal. In the main, they have now been with this myriad of input information, while still allowing the ECU’s replaced by more powerful SoC devices or FPGAs. functionality to be updated or modified by reprogramming the FPGAs. CPU: Central processing unit, the component responsible for System on chip executing the programs required to run an engine, by processing inputs and sending signals to the various drivers and outputs. The Up to this point, the different processing systems of the ECU have been greater the power of the CPU, the more complex the tasks it can looked at as individual items but, increasingly, combined units known handle. as ‘system on chip’ (SoC) devices are becoming popular. Although similar in their operation to ASICs, the latest generation of SoC devices but overall manufacturing costs can often be reduced as well. This is are far more powerful and versatile. They can integrate a myriad of due to the reduction in tooling needed: silicon chips are made using components on one chip, including multi-core processors, signal special dies, which are expensive to manufacture. If the number of processors, filters and communications buses. chips needed is reduced, so too is the initial cost of tooling. By integrating them, not only can particular tasks be provided with In racing applications, SoC technology is often limited to uses dedicated processing power – reducing the load on the main CPU – such as dedicated signal processors for components such as strain gauge amplifiers. However, they feature extensively in ECUs based on mainstream production units, where production volumes offset the The current-spec ECU used in Formula One has 300 inputs initially high manufacturing costs, so they are also likely to be found and outputs, housed in only three high-density connectors in production-based engines used for competition.

Data logging Data logging in an ECU, as opposed to the more general logging of vehicle systems, is a key area of development in modern racing ECUs. By logging the operation of the unit, engineers can gain a clearer understanding of the effectiveness of the coding that operates the system, allowing for debugging and optimising these programs. One important requirement is that the logging takes place without compromising the core operation of the controller. The greater the volume of information that can be logged, the more programmers can ensure that their models for engine operating parameters match up to real-world performance. The actual data generated by an ECU is fairly simple when compared to, say, a program running on a home computer, so a small amount of logging memory – sometimes only a few Mbytes – will suffice for most basic engine set-ups. On more complex systems, such as those found in the current generation of Formula One cars

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DSP: Digital signal processor. A dedicated microprocessor designed I/O: The abbreviation used to refer to inputs and outputs from a to process digital signals converted from analogue sources. They processor or system. are particularly important for filtering out signal noise from analogue sensors. Logic gate: An idealised or physical device implementing a Boolean function – that is, it performs a logical mathematical operation on one EPROM: Erasable programmable read-only memory, a type of or more logic inputs and produces a single logic output. A gate array memory chip that retains its data when its power supply is switched circuit is a prefabricated silicon chip with no particular function in which off. In other words, it is non-volatile. It is an array of floating-gate transistors, standard NAND or NOR logic gates, and other devices are transistors, which differ from normal transistors by having an extra, placed at regular predefined positions and manufactured on a wafer, unconnected gate sandwiched between the normal (control) gate usually called a master slice. Creating a circuit with a specified function and the channel gate; individually programmed by an electronic is accomplished by adding a final surface layer or layers of metal device that supplies higher voltages than those normally used in interconnects to the chips on the master slice late in the manufacturing digital circuits. An EPROM can only be erased by removing it from a process, then joining these elements to allow the function of the chip to device and exposing it to UV light. be customised as desired.

EEPROM: Electrically erasable programmable read-only memory, System on Chip: An integrated circuit that integrates all the a type of non-volatile memory used to store small amounts of data components of a computer or other electronic system into a single chip. (such as calibration tables or device configuration) that must be It may contain digital, analogue, mixed-signal and often radio-frequency saved when power is removed. The memory can be erased and functions – all on a single chip substrate reprogrammed electronically with the chip still installed in a device.

Flash memory: A non-volatile storage chip that can be electrically Engine technology integration erased and reprogrammed. It was developed from EEPROM and must be erased in fairly large data blocks before being rewritten with new Gasoline direct injection (GDI) is not a new idea; the first systems data. appeared at the end of the 1930s, and were first used in the Mercedes 300SL, which featured a mechanical GDI system. The past decade where the ECU has several hundred I/Os, the memory requirement has seen the widespread adoption of the technology in both race and is far greater. In this particular case the spec ECU features 1 Gbyte of road applications, with OEMs developing advanced control systems to flash memory dedicated to logging ECU functions, enough to record a optimise efficiency. full race distance. Integrating GDI with existing ECU architectures has not in itself presented great challenges, but integrating a direct-injection capability Miniaturisation/connectors into a single controller chip (as opposed to several) has only recently With the growing number of I/Os on a modern ECU, the physical become possible. Replacing the more forgiving but less fuel-efficient task of accommodating the hard cabling into the unit becomes more port injection requires a step-change in improvement in processing complex. Clearly for motorsport applications the size and weight of power. Instead of a single pulse that is on or off for a period of time any component is of utmost importance, and wiring connectors are no and placed in one location in the combustion cycle, the CPU must exception. handle a complex ‘peak and hold’ waveform, as well as process data The range of connections required for an ECU is diverse, and on inlet and exhaust valve motion. while most I/Os will be low-voltage/current, some functions such as The process involves precise current measurements and significant injector drivers will be much higher power. Whereas previously these high-speed switching to develop an electrical current profile, and it is would have required separate connectors, this problem can now be common to have more than one injection event per cycle. As a result, circumvented thanks to the availability of connectors with a mix of the raw calculation power and timing requirements have increased contacts, capable of accommodating a range of wire gauges in the exponentially. One of the latest microprocessors designed with the same connector shell. needs of GDI in mind features three 96-channel enhanced timing The density of connections that can be packaged into a particular units, each with 45k of dedicated RAM incorporated into a dual-core shell size has also risen, thanks to systems that now allow for very processor, allowing it to execute the complex algorithms reliably. fine-gauge wiring (down to AWG32) to be used reliably in autosport To give an idea of the accuracy needed to control GDI properly, a systems. Before, the use of wire this thin was not considered practical mechanically geared system can typically achieve accuracy to within due to the harsh environment a racing loom has to face; however, 6º of crank rotation; however, for GDI an accuracy of 0.1º is required the development of improved jointing and protection techniques for optimal control of fuel spray and spark. This presents a problem now makes it feasible. This has led to a fall in the number and size because measuring the crank rotation with this degree of accuracy is not of external connections needed, with a subsequent reduction in ECU practical, so the ECU must predict when the injection event is needed. packaging size. A good example here is the current-generation control This can be achieved using an enhanced time processor unit ECU specified for use in Formula One, which features 300 I/Os housed incorporated into the CPU, which calculates the precise timing of the

in only three 100-pin connectors. injection and compensates for limitations in the mechanical systems. t

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Timing this injection operation involves a complex calculation where the unit measures the time between two teeth (on either the crank or cam trigger wheel), then carries out an ‘angle to time’ conversion, in effect creating a virtual crank signal. Although it may seem initially like a simple calculation, on an engine running at moderate speed (about 7000 rpm), the processor has to make this conversion 36,000 times per second, per cylinder, hence the considerable increase in processing power required over a port-injection controller. In an internal combustion engine, accurate knock detection and control can help improve effi ciency by anything up to 5%, which in racing terms translates into more power or lower fuel consumption. Given the growing trend towards more fuel-effi cient or ‘greener’

racing, an optimised knock detection system is a valuable tool for the Direct-injection systems in motorsport are often operated by separate controllers, but the engine designer. increased processing power of the latest generation of microprocessors means this control can be integrated into the main ECU (Courtesy of Life Racing) To date, control techniques for knock detection include vibration sensors and spark plug ionisation to sense the onset of knock. In most current systems, a dedicated ASIC typically identifi es the knock sensors for knock/misfi re detection, mass airfl ow and manifold absolute signal from other engine noise within a few milliseconds of the event pressure sensing. However, the task of acquiring up to eight pressure occurring. The analogue signal from the knock detection sensor (or profi les over a full 720º of engine revolution – one sensor per cylinder sensors) is typically sampled at 150 kHz and applied as an input for an eight-cylinder engine – provides a challenge for current closed- parameter to the spark control system. loop combustion control systems. One possible solution provided by a The process of knock detection requires a lot of digital fi ltering major processor producer involves using a dual-core processor: one core and subsequent calculation to isolate relevant signals from other is dedicated to fi ltering the input signals, while the other core runs the engine noise. As engineers seek to make full use of the gains to be actual application strategy. This avoids the need for multiple processors, made from lean-burn combustion, the accuracy of knock prevention and simplifi es the programming needed to operate the system. systems becomes increasingly important. This equates to a need for The increase in complexity of the control systems used on engines greater accuracy and speed in processing the signals from sensors, and has spurred engineers and programmers to start looking at alternative therefore a subsequent increase in computing load. methods of executing the basic operations the systems use to process Several component manufacturers now offer dedicated SoC units information. One area of research involves the use of artifi cial neural with dual-core processors that will support the most complex knock networks (ANNs) as an alternative to traditional data processing

control systems, removing the computational load from the ECU’s methods. An ANN is a mathematical or computational model inspired t main processor.

Continuously variable valve systems such Future developments as the Fiat/Chrysler Multi Air system place considerable demands on ECU As the capability of the chipsets processing power. It is inevitable that used in ECUs continues to these systems will begin to appear in motorsport (Courtesy of Schaeffl er Group) advance, the control of complex engine functions can not only be accommodated but incorporated into simpler (in terms of the number of components used) and more integrated controllers. The increased capacity also means that additional future functionality can be added, without the need to add further controllers. One avenue being investigated by roadcar manufacturers, which has been made possible by this increase in computing power, is in-cylinder pressure sensing as a potential alternative to individual

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SOME EXAMPLES OF ECU AND RELATED SUPPLIERS

AUStRALIA UK Haltech Cosworth Electronics +612 9729 0999 www.haltech.com +44 1954 253600 www.cosworth.com Motec DC Electronics +61 3 9761 5050 www.motec.com.au +44 1621 856 451 www.wiringlooms.com Wolf Engine Management DtA +613 9761 3161 www.wolfems.co.au +44 161 877 1419 www.dtafast.co.uk Emerald FRANCE +44 1953 889110 www.emeraldM3D.com e-RACE GEMS +33 3 20 79 11 22 www.e-race.fr +44 1784 470525 www.gems.co.uk Life Racing GERMANy +44 1268 274421 www.liferacing.com Bosch M-tech +49 711 8110 www.bosch.com +44 1451 822458 www.m-techautomotive.co.uk McLaren Electronic Systems GREECE +44 1483 261400 www.mclarenelectronics.com Plex tuning Ole Buhl Racing +30 693 2284 040 www.plex-tuning.com +44 1425 478 822 www.obr-motorsport.co.uk Omex ItALy +44 1242 260656 www.omextechnology.com Magneti Marelli St. Cross Electronics +39 0297 227738 www.magnetimarelli.com +44 23 8022 7636 www.st-cross-electronics.co.uk MtA Stack +39 0377 4181 www.mta.it +44 1869 240 404 www.stackltd.com

NEtHERLANDS USA Kronenburg Management Systems AEM-Advanced Engine Management +31 402 854 064 www.van-kronenburg.nl +1 310 484 2322 www.aemelectronics.com Bazzaz NEW ZEALAND +1 909 628 8616 www.bazzazperformance.com Link Electro Systems Big Stuff +64 334 88854 www.link-electro.co.nz +1 248 887 5636 www.bigstuff3.com BMRS Wired +1 704 793 4319 www.bmrs.net by the structure and/or functional aspects of biological neural EFI technology networks. The network itself consists of an interconnected group of +1 310 793 2505 www.efitechnology.com artificial neurons, and it processes information using a connectionist EngineLab Corporation +1 408 642 4535 www.enginelab.net approach to computation. In most cases an ANN is an adaptive system Electomotive that changes its structure based on external or internal information that +1 703 331 0100 www.emi.cc flows through the network during a learning phase of programming. Sakata One area here of particular relevance to race engines is research +1 714 446 9473 www.sakatamotorsport.com into the use of ANN-based signal processing for calculating the volumetric efficiency (VE) of an engine in real time (see Reference). do not currently allow such technologies, they are becoming more This looked at the practicalities of replacing the usual VE calibration common in road vehicles. As motorsport is pushed further down a look-up tables used in ECUs with an ANN-based algorithm. more environmentally friendly path, it seems inevitable that these The motive for the research was the extra complexity that systems systems will begin to appear in racing, both in dedicated race engines such as variable valve timing introduce into traditional look-up tables, and road-based units. These new systems will in turn place further highlighting potential problems relating to scalability of these systems. demands on engine control electronics, and the current advances in The use of ANNs allowed for a far greater range of factors to be taken the power of these systems will need to be harnessed to accommodate

into account, with the system being scalable to incorporate future these challenges. n increases in complexity. Although very much in the early stages of research and development, ANNs could well play a key role in the Reference future development of ECUs. Malaczynski, G.W., Mueller, M., and Pfeiffer, J., In the shorter term, developments in CPU processing power will “Replacing Volumetric Efficiency Calibration Lookup Tables benefit the integration of emerging engine technologies such as with Artificial Neural Network-based Algorithm for Variable Valve constantly variable valve timing. Although series such as Formula One Actuation”, SAE Paper 2010-01-0158

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