Features • High-performance DirectSound™ Direct3DSound™ Operation – Direct Access to Audio Data as PCI Master – Uses PCI Bursts with Patented Proprietary Cache RAM to Minimize PCI Bandwidth – Mixes up to 64 Audio Channels at 48 kHz (Streaming Audio and/or Static Buffers) – Up to Eight Audio Channels in Record – Interactive Audio Includes per Channel Doppler, 4-speaker Output and Filter – Audio Effects: Reverb, Chorus, Echo, Pitch Shifting, 4-band Equalizer, Surround • Top-quality Wavetable Synthesis – 16-bit Samples @ 48 kHz Sampling Rate – Up to 64-voice Polyphony by Hardware Sound – Internal Computations on 28 Bits, DAC Support up to 22 Bits – Alternate Loop, 24 dB Digital Filter for Each Voice – Roland GS™ Format-compliant Synthesis – Sample Sets under Roland® License, rSounds © Roland Corporation 1996 – DirectMusic™ Accelerator, Downloadable Sounds DLS1 Support, DLS2 Ready • Multiple Audio Inputs and Outputs – AC97 Codec-compliant Interface ATSAM9777 – Three I2S Outputs (Six Audio Channels) – Four I2S inputs (Eight Audio Channels) PCI Bus – Home PC-ready for Dolby® AC-3 Six-speaker output – Dual Joystick Game Port Single-chip • Multi-platform – Windows® 95/98 Drivers Multimedia – Windows® 2000 WDM Drivers • Fully Programmable Sound System – Firmware Resides in PC Memory and in On-chip RAM – Evolutive Firmware Open to Third-party Developers • Designed for PC Motherboards and Notebooks – 3.3V or 5V Operation – Choice of Standard 100-lead PQFP or Space-saving 100-lead TQFP Package
Description The highly-integrated architecture of ATSAM9777 is derived from the ATSAM9407 but contains significant improvements. The ATSAM9777 combines a specialized high-performance RISC-based digital signal processor (synthesis/DSP) and a general-purpose 16-bit CISC-based control proces- sor on a single chip. A PCI interface with bus mastering capability enables the synthesis/DSP and the control processor to directly access external PC memory. A local program/data RAM, independent synthesis/DSP and control processor cache RAM, as well as PCI transfers on a PC CPU-cache line basis allow a dramatic reduc- tion in PCI bandwidth. An intelligent peripheral I/O interface function handles other I/O interfaces such as controls received from the PCI interface in target mode, the on-chip MIDI UART, and three timers with minimum intervention from the control processor. The PCI interface also implements a legacy joystick.
Rev. 1716B-DRMSD–11/02
1 Block Diagram
Figure 1. Functional Overview Block Diagram
Synthesis/DSP Codecs
RISC DSP Core Includes: 512 x 16 ALG RAM DSP PCI Interface 128 x 28 MA1 RAM Cache RAM 256 x 32 MA2 RAM 96 x 256 256 x 32 MB RAM 128 x 16 MX RAM 256 x 16 MY RAM 64 x 13 ML RAM
Initiator Config EEPROM (optional)
P16 Processor P16 Processor 16-bit CISC Processor Cache RAM Core Includes: 20 x 256 PCI BUS 256 KB x 16 Data RAM 16 x 16 Boot ROM
Local Legacy Program/Data Joystick RAM 1K x 16 Joystick
Target
I/O Functions
Include: MIDI UART Timers Target FIFO
MIDI
2 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
Pin Description
PCI Bus Group
Table 1. PCI Bus Group (All signals PCI-compliant) Pin Pin Name Count Type Function AD[31:0] 32 I/O Multiplexed address/data C/BE[3:0] 4 I/O Command and byte enables PAR 1 I/O Parity FRAME 1 I/O Cycle Frame IRDY 1 I/O Initiator ready TRDY 1 I/O Target ready STOP 1 IN Indicates target requests ATSAM9777 to stop transaction DEVSEL 1 I/O Device select IDSEL 1 IN Initialization device select PERR 1 I/O Parity error PME 1 OD Power Management Event (Open drain) REQ 1 TS OUT Request bus for master operation GNT 1 IN Master access to bus granted CLK 1 IN PCI timing clock RST 1 IN System reset INTA 1 OD Open drain signal, interrupt request Note: Pin names exhibiting an overbar (PME for example) indicate that the signal is active low.
Digital Audio Group
Table 2. Digital Audio Group Pin Pin Name Count Type Function AC_RES 1 OUT AC 97 Master reset, can also be used as buffered RESET for DAC/ADC AC_SYNC 1 OUT AC 97 48 kHz fixed sampling rate AC_DOUT Multi-function pin. Configured by firmware. Serial audio stream to AC 97 or I2S data out 1OUT SD_OUT_0 channel 0. AC_DIN Multi-function pin. Configured by firmware. Serial audio stream from AC 97 or I2S data 1IN SD_IN_0 in channel 0. BCK_OUT 1 OUT I2S bit clock for audio-out and master mode audio-in WS_OUT Multi-function pin. 1OUT Output, I2S data word select for audio-out and audio-in. SD_OUT_1 Multi-function pin. 1OUT Output I2S auxiliary stereo-out channel #1 data @ 32 bits per sample (22 useful bits).
3 1716B–DRMSD–11/02 Table 2. Digital Audio Group (Continued) Pin Pin Name Count Type Function SD_OUT_2 Multi-function pin. 1OUT Output I2S auxiliary stereo-out channel #2 data @ 32 bits per sample (22 useful bits). SD_IN_1P1 1 Multi-function pin. IN or I/O Configuration by firmware. I2S data in channel 1 or general-purpose I/O pin. SD_IN_2P2 1 Multi-function pin. IN or I/O Configuration by firmware. I2S data in channel 2 or general-purpose I/O pin. SD_IN_3P3 1 Multi-function pin. IN or I/O Configuration by firmware. I2S data in channel 3 or general-purpose I/O pin.
Joystick, MIDI and Miscellaneous Group Table 3. Joystick, MIDI and Miscellaneous Group Pin Pin Name Count Type Function JSX1, JSY1 2 AIN Joystick 1 coordinates JSB11, JSB12 2 IN Joystick 1 buttons 1 & 2 JSX2, JSY2 2 AIN Joystick 2 coordinates JSB21, JSB22 2 IN Joystick 2 buttons 1 & 2 JSREF 1 AIN Joystick reference voltage MIDI_IN 1 IN Serial MIDI_IN MIDI_OUT 1 OUT Serial MIDI_OUT P0 Multi-function pin. 1 I/O or OD General-purpose I/O pin CKIN 1 – 12.288 MHz master clock input (256xFs). Normally connected to AC 97 BIT_CLK LFT 1 – PLL decoupling TEST[1:0] 1 IN Test pins, should be grounded for normal operation. SCL, SDA 1 Optional Serial configuration EEPROM connection.
Power Supply Group
Table 4. Power Supply Group Pin Name Pin Count Function GND 9 Digital ground pins. All pins should be connected to a ground plane below the IC. VC3 9 3.3V ± 10% digital power. All pins should be connected. VCC 3V to 5.5V periphery power. Determines the operation level of the Codec EEPROM and MIDI 1 signals. AGND 1 Analog ground for the joystick analog pins JSXn/JSYn AVC3 1 Analog power for the joystick pins JSXn/JSYn, 3.3V ± 10%
4 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
Pinout by Pin
Table 5. Pinout for 100-lead PQFP Package (ref. ATSAM9777-PQ) Pin Pin Pin Pin Number Pin Name Number Pin Name Number Pin Name Number Pin Name 1 AD19 26 AD10 51 VCC 76 RST 2 GND 27 AD9 52 GND 77 CLK 3 GND 28 VC3 53 GND 78 VC3 4 AD18 29 VC3 54 SD_OUT_2 79 VC3 5 AD17 30 AD8 55 SD_OUT_1 80 GNT 6 AD16 31 C/BE0 56 WS_OUT 81 REQ 7 C/BE2 32 GND 57 BCK_OUT 82 NC 8FRAME33 AD7 58 AC_RES 83 GND 9IRDY34 AD6 59 AC_SYNC 84 GND AC_DIN, 10 TRDY 35 AD5 60 85 AD31 SD_IN_0 11 GND 36 AD4 61 CKIN 86 AD30 AC_DOUT, 12 VC3 37 AD3 62 87 AD29 SD_OUT_0 13 VC3 38 VC3 63 JSB22 88 AD28 14 DEVSEL 39 AD2 64 JSB21 89 AD27 15 STOP 40 AD1 65 JSB12 90 VC3 16 TEST1 41 AD0 66 JSB11 91 AD26 17 PERR 42 SCL 67 AGND 92 AS25 18 PAR 43 SDA 68 JSY2 93 AD24 19 C/BE1 44 TEST0 69 JSX2 94 C/BE3 20 AD15 45 P0 70 JSREF 95 IDSEL 21 AD14 46 SD_IN_1, P1 71 JSY1 96 AD23 22 GND 47 SD_IN_2, P2 72 JSX1 97 AD22 23 AD13 48 SD_IN_3, P3 73 AVC3 98 VC3 24 AD12 49 MIDI OUT 74 INTA 99 AD21 25 AD11 50 MIDI IN 75 LFT 100 AD20
5 1716B–DRMSD–11/02 .
Table 6. Pinout for Space-saving 100-lead TQFP Package (ref ATSAM9777-TQ) Pin Pin Pin Pin Number Pin Name Number Pin Name Number Pin Name Number Pin Name 1 GND 26 VC3 51 GND 76 VC3 2 AD18 27 VC3 52 SD_OUT_2 77 VC3 3 AD17 28 AD8 53 SD_OUT_1 78 GNT 4 AD16 29 C/BE0 54 WS_OUT 79 REQ 5 C/BE2 30 GND 55 BCK_OUT 80 PME 6FRAME31 AD7 56 AC_RES 81 GND 7IRDY32 AD6 57 AC_SYNC 82 GND AC_DIN, 8TRDY33 AD5 58 83 AD31 SD_IN_0 9 GND 34 AD4 59 CKIN 84 AD30 AC_DOUT, 10 VC3 35 AD3 60 85 AD29 SD_OUT_0 11 VC3 36 VC3 61 JSB22 86 AD28 12 DEVSEL 37 AD2 62 JSB21 87 AD27 13 STOP 38 AD1 63 JSB12 88 VC3 14 TEST1 39 AD0 64 JSB11 89 AD26 15 PERR 40 SCL 65 AGND 90 AS25 16 PAR 41 SDA 66 JSY2 91 AD24 17 C/BE1 42 TEST0 67 JSX2 92 C/BE3 18 AD15 43 P0 68 JSREF 93 IDSEL 19 AD14 44 SD_IN_1, P1 69 JSY1 94 AD23 20 GND 45 SD_IN_2, P2 70 JSX1 95 AD22 21 AD13 46 SD_IN_3, P3 71 AVC3 96 VC3 22 AD12 47 MIDI OUT 72 INTA 97 AD21 23 AD11 48 MIDI IN 73 LFT 98 AD20 24 AD10 49 VCC 74 RST 99 AD19 25 AD9 50 GND 75 CLK 100 GND
6 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings Ambient Temperature (Power applied) ...... -40°C to + 85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- Storage Temperature...... -65°C to + 150°C age to the device. This is a stress rating only and functional operation of the device at these or any
Voltage on any pin ...... -0.5V to VCC + 0.5V other conditions beyond those indicated in the operational sections of this specification is not VCC Supply Voltage...... -0.5V to + 6.5V implied. Exposure to absolute maximum rating condtions for extended periods may affect device VC3 Supply Voltage...... -0.5V t0+ 4.5V reliability.
Maximum IOL per I/O pin ...... 10mA Note: All voltages with respect to 0V, GND = 0V.
Recommended Operating Conditions
Table 8. Recommended Operating Conditions Symbol Parameter/Condition Min Typ Max Unit
(1) VCC Supply Voltage 3 3.3/5.0 5.5 V
VC3 Supply Voltage 3 3.3 3.7 V
TA Operating Ambient Temperature 0 70 °C
Note: 1. When using 3.3V supply, care must be taken that voltage applied on pin does not exceed VCC + 0.5V.
DC Characteristics
Table 9. DC Characteristics (TA = 25°C, VC3 = 3.3V ± 10%)
Symbol Parameter/Condition VCC Min Typ Max Unit 3.3 -0.5 1.0 V V Low-level Input Voltage IL 5.0 -0.5 1.7 V 3.3 2.3 3.8 V V High-level Input Voltage IH 5.0 3.3 5.5 V 3.3 mA I Power Supply Current TBD CC 5.0 mA Power Down Supply Current TBD µA
7 1716B–DRMSD–11/02 Functional Overview
Synthesis/DSP The synthesis/DSP engine operates on a frame-timing basis with the frame subdivided into 64 Engine process slots. Each process is itself divided into 16 micro-instructions known as “algorithms”. Up to 32 synthesis/DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be programmed for a number of audio signal generation/processing applications. The synthesis/DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for each voice. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. A typical multimedia application will use part of the capacity of the synthesis/DSP engine for fixed resource functions such as reverberation, chorus, echo, pitch-shifting, surround, equal- izer, etc. The remaining capacity will typically be dynamically allocated between direct-sound play/record and wavetable synthesis. With all fixed-resource functions removed, 64-voice syn- thesis or 32 direct-sound channels can be achieved. Frequently-accessed synthesis/DSP parameter data are stored in five banks of on-chip RAM memory. Sample data or delay lines that are accessed relatively infrequently are stored in external PC memory and accessed through the synthesis/DSP cache RAM. The combination of localized micro-program memory and localized parameter data allows micro-instructions to execute in 20 ns (50 MIPS). Separate buses from each of the on-chip parameter RAM memory banks allow highly-parallel data movement to increase the effectiveness of each micro-instruction. With this architecture, a single micro-instruction can accomplish up to eight simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 400 million operations per second (MOPS). Compared to the ATSAM9407, the synthesis/DSP engine now offers the following significant enhancements: • 24 x 16 multiplier • Direct support of 8-/16-bit mono/stereo Microsoft wave formats • No “bank” limitation • 32-bit word size for delay lines, giving virtually noise-free reverb • Pan steps of 0.75 dB • Audio data in on 20 bits • Six channels audio-out
P16 Control The P16 control processor is a general-purpose 16-bit CISC processor core that runs from a Processor and I/O local program/data RAM or from PC memory through the P16 processor cache RAM. A boot Functions ROM is included that allows the PC to upload an initial program into the local program/data RAM at power-up. The P16 also includes 256 words of local RAM data memory. The first 16 words of this RAM hold general-purpose registers; the next eight words hold segment and I/O registers. The remaining part of the RAM is free to store frequently-used variables and the stack. The P16 control processor writes to the parameter RAM blocks within the synthesis/DSP core in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART or from the PCI interface and then controls the synthesis/DSP by writing into the parameter RAM banks in the DSP core.
8 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
Slowly-changing synthesis functions such as LFOs are implemented in the P16 control pro- cessor by periodically updating the DSP parameter RAM variables. The P16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the PCI interface through specialized “intelligent” peripheral I/O logic. This I/O logic automates many of the system I/O transfers to minimize the amount of overhead processing required from the P16.
PCI Interface The PCI interface can operate in both initiator and target mode. In initiator mode, the PCI interface is a PCI bus master. It can access any address in the 32-bit PC RAM space. Two base registers provide different segments for the P16 program/data and the synthesis/DSP RAM. This allows simple relocation of the synthesis/DSP address space without interrupting the P16 program. Most PCI transfers occur on a PC cache line basis, i.e., as a burst of eight 32-bit words. Such a burst will typically take 13 cycles on the PCI bus, which is about 390 ns. When playing audio at 48 kHz mono 16 bits, this means that 16 audio samples are read in 390 ns, taking only 0.12% of the PCI bandwidth. In target mode, the PCI interface is assigned I/O or memory range as defined by the plug-and- play BIOS or operating system. 16 consecutive bytes of I/O or memory space are required and a single interrupt line INTA. At power-up, the legacy devices are hidden (they do not partici- pate in the plug-and-play enumeration). A specific configuration program is required to enable the legacy devices. Legacy devices are implemented in the PCI configuration registers according to Intel® recommendations. An optional serial EEPROM can be connected to the ATSAM9777. It allows the default config- uration registers setting to be overridden. This allows the ATSAM9777 to be customized for different vendors, giving the possibility of distinguishing an ATSAM9777 mounted on the moth- erboard from a ATSAM9777 mounted on an audio add-in card.
9 1716B–DRMSD–11/02 Additional Information
PCI Bus The PCI bus bandwidth utilized by a PCI sound card is a major concern, as it determines criti- Bandwidth cal parameters such as the number of streaming audio that can be mixed together or the maximum video frame rate for a game. Unlike most PCI sound accelerators, the ATSAM9777 processes everything on-chip. This includes MIDI data parsing and processing and effects like reverb, chorus, echo, equalizer, surround, filter, pitch shifting and 3-D positioning. Another unique feature of the ATSAM9777 device is that the built-in 16-bit processor (P16) executes instructions from a built-in local RAM and from PC memory (through a built-in cache). Thor- ough testing has been conducted in order to determine the PCI bus bandwidth utilization of such a structure. The results are given in Table 10 for a worst-traffic case from a typical application.
Table 10. PCI Bus Bandwidth Instruction Execution Functional Block Average PCI Burst Access/Synthesis Frame 32 mono 16-bit waves @ 48 kHz, 3-D positioning 2 (read) Reverb with 13 delay lines 0.8 (read) 0.8 (write) Equalizer 4 bands 0 P16 (worst case = 10% out of PC memory) 0.2 (read) 0.1 (write) Total 3 (read) 0.9 (write)
With: • Synthesis frame = 20833 ns • PCI burst read = 390 ns • PCI burst write = 630 ns This gives a total PCI load due to the ATSAM9777 of 8.3%. On this load, only 0.7% is related to the P16. Note that this computation only takes into account the load due to the ATSAM9777 itself. The total load for audio depends on PC implementation (secondary cache size, DRAM configura- tion and speed) and on the software application implementation (wave data located in main memory or on disk). Also the load assumes that there are no retries on the PCI bus.
10 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
PCI Configuration The reader is assumed to be familiar with the PCI bus specification as defined in the document Space published by the PCI Special Interest Group PCI Local Bus Specification. Rev 2.1 June 1st, 1995.
Configuration Space Overview
Table 11. Configuration Space Overview 00H Device ID = 9777/EEP(1) Vendor ID = Atmel-Dream® ID/EEP(1) 04H Status Register Command Register 08H Class Code = 04 01 00 (Multimedia Audio) Revision ID = 0 0CH BIST = 00 Header Type = 00 Latency Timer Cache Line = 00 10H Base Memory Mode 14H Base I/O Mode 18H 00 00 00 00 1CH 00 00 00 00 20H 00 00 00 00 24H 00 00 00 00 00 00 00 00 28H 2CH Subsystem ID = 00 00/EEP(1) Subsystem Vendor ID = 00 00/EEP(1) 30H 00 00 00 00 34H 00 00 00 00 Cap_ptr = 00/EEP(1) 38H 00 00 00 00 3CH Max_Lat = 00 Min_Gnt = 00 Interrupt Pin = 01 Interrupt Line 40H – LACR 44H – DMACFG 48H – 4CH – 50H – 54H – 58H – 5CH – 60H – 64H Joystick Base (default 200 - 207H) 68H – 6CH – 70H – 74H – 78H – 7CH –
11 1716B–DRMSD–11/02 Table 11. Configuration Space Overview (Continued) 80H – 84H – O 88H 00 00 00 00 Notes: 1. EEP means that value can be replaced by EEPROM content. 2. Addresses 00H to 3FH hold the standard PCI configuration.
Configuration Registers Description
PCI Standard Registers
Vendor ID: 00H - 01H, Read-only
15141312111098a76543210 1438H or EEPROM
Identifies the manufacturer of the device. If no EEPROM is connected, then it holds the Atmel-Dream® PCI ID = 1438H, oth- erwise it holds bytes 2 and 3 of the EEPROM.
Device ID: 02H - 03H, Read-only
15 14 13 12 11 10 9 8a 7 6 5 4 3 2 1 0 9777H or EEPROM
Identifies the device. It reads as 9777H if no EEPROM or bytes 4 and 5 from the EEPROM.
Command: 04H - 05H, partial Read/Write
15141312111098a76543210 Reserved 0000000BMMSIO
Bits IO, MS, BM are read/write, all other bits are read-only and return zero. • IO: If 1, allows the device to respond to I/O space accesses (reads zero after reset). • MS: If 1, allows the device to respond to memory space accesses (reads zero after reset). • BM: If 1, allows the device to act as a master on the PCI bus (reads zero after reset).
12 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
Status: 06H - 07H, Partial Read/Write
15141312111098a76543210 DPE SSE RMA RTA STA Speed MPE BTB UDF 66M Reserved
According to the PCI specification, implemented bits can only be set by device. They can be reset by writing the corre- sponding bit at 1. • Reserved: read-only, returns 00000 • 66M: 66 MHz-capable, read-only, returns zero • UDF: UDF supported, read-only, returns zero • BTB: Fast back-to-back capable, read-only, returns zero • MPE: Master Parity Error detected, implemented • Speed: DEVSEL timing, read-only, returns 01 (medium speed device) • STA: Signaled target abort, read-only, returns 0 • RTA: Received target abort, implemented • RMA: Received master abort, implemented • SSE: Signaled system error, read-only, returns 0 • DPE: Detected Parity Error, implemented
Revision ID: 08H, Indicates revision of device, returns 0 Read-only
Class Code: 09H - 0BH, Indicates Multimedia Audio Device, returns 04H 01H, 00H Read-only
Cache Line Size: 0CH, Not applicable, returns zero Read-only
Latency Timer 0DH, Reads zero after reset Read/Write
Header Type 0EH, Returns zero (single function device) Read-only
BIST 0FH, Read-only BIST not supported, returns zero
Base Memory Mode 10H - 13H, Partial Read/Write
3130292827...8a76543210 Base Address 0000
Bits 0 - 3 always read back as zero, indicating memory mode, locate anywhere in 32-bit address space, not prefetchable, size 16 bytes.
13 1716B–DRMSD–11/02 Base I/O Mode: 14H - 17H Partial Read/Write)
3130292827...8a76543210 Base Address 0001
Bits 0 - 3 always read back as 0001, indicating I/O mode, size 16 bytes.
Subsystem Vendor ID: Returns zero if no EEPROM, or bytes 6 and 7 from the EEPROM 2CH - 2DH, Read-only
Subsystem ID: 2EH - 2FH Returns zero if no EEPROM, or bytes 8 and 9 from the EEPROM Read-only
Interrupt Line: 3CH Used by the operating system to indicate interrupt routing. Read/Write
Interrupt Pin: 3DH Returns 01H indicating that the device needs one interrupt (INTA). Read-only
Min_Gnt: 3EH Minimum Grant, returns zero (no major requirement). Read-only
Max_Lat: 3FH Maximum Latency, returns zero (no major requirement). Read-only
Legacy Audio Control Registers
LACR, Legacy Audio Configuration Register: 40H - 41H Read/Write
15141312111098a76543210 LAD JE
The reset value of LACR is 907FH. LAD: Legacy audio disable: if 1, all legacy audio functions are disabled JE: Enable joystick function at I/O address specified by Joystick base
I/O Registers The base address mechanism provides 16 bytes of I/O to the device. These 16 bytes can be located in memory or I/O space.
Write Mode Writing a byte from base + 0 to base + 15 will send it to the P16 FIFO for further processing by the P16. Actions taken are totally firmware-dependent. Additionally, base + 2 is reserved for external EEPROM programming as follows:
76543210 SDA SCL
14 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
SDA and SCL are write-only. Writing to these bits will be immediately reflected in the corre- sponding SDA and SCL pins.
Read Mode Two byte registers, data and status, are implemented respectively at base + 0 and base + 1. When the P16 writes to the data register, an interrupt request is sent to the host processor. This request is cleared by the host reading the data register. The status register format is as follows:
76543210 Dsr Drr Sx2 Sx1 Sx0 0 0 0 Dsr: 0 if data pending (asserts INTA), set by read data (de-asserts INTA) Drr: 0 if ready to accept data, 1 if P16 FIFO full Sx2, Sx1, Sx0: bits which can be programmed by the P16, indicating the type of data pending.
EEPROM Format
Table 12. EEPROM Format Address Data 00H 55H - First byte of EEPROM identification 01H AAH - Second byte of EEPROM identification 02H Vendor ID low byte (Config @ 00H) 03H Vendor ID high byte (Config @ 01H) 04H Device ID low byte (Config @ 02H) 05H Device ID high byte (Config @ 03H) 06H Subsystem Vendor ID low byte (Config @ 2CH) 07H Subsystem Vendor ID high byte (Config @ 2DH) 08H Subsystem Device ID low byte (Config @ 2EH) 09H Subsystem Device ID high byte (Config @ 2FH) 0AH PMI Capability ID (Config @ 80H) 0BH PMI Next Item Ptr (Config @ 81H), normally zero 0EH PMI PMCSR low byte (Config @ 84H), only bits 2 to 7 used 0FH PMI PMCSR high byte (Config @ 85H), only bits 5 and 6 used 10H PMI PMCSR_BSE (Config @ 86H), normally zero 11H - 1FH PMI Data
15 1716B–DRMSD–11/02 Timings All timings conditions: VCC = 5V, VC3 = 3.3V, TA = 25°C The ATSAM9777 complies with the PCI bus and AC-97 timings. For PCI bus timings, please refer to PCI Local Bus Specification. Rev 2.1, June 1, 1995, pub- lished by the PCI Special Interest Group. For AC-97 codec timing, please refer to Audio Codec 97 Component Specification. Rev 1.03, Sept. 15, 1996, published by Audio '97 Working Group; Audio Codec 97, Rev 2.0, Sept. 29, 1997, published by Intel Corporation.
I2S Digital Audio These timings refer to pins SD_OUT_0 to SD_OUT_2, SD_IN_0 to SD_IN_3, BCK_OUT, WS_OUT.
tCK refers to the period of the CKIN clock (typically 81.38 ns).
Figure 2. Digital Audio Timing
tCW tCW tCLBD
WS_OUT
BCK_OUT
tSOD tSOD SD_OUT_x SD_IN_x
Table 13. Timing Parameters Symbol Parameter Min Typ Max Unit
tCW BCK_OUT rising to WS_OUT change 8 x tCK-10 ns
tSOD SD_OUT_x valid prior/after BCK_OUT rising 8 x tCK-10 ns
tCLBD BCK_OUT cycle time 16 x tCK ns
16 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
Digital Audio Frame
Figure 3. Digital Audio Frame Format
32 periods
WS_OUT
BCK_OUT
SD_OUT_x SD_IN_x (1)
LSB LSB MSB LSB (22 bits) MSB (16 bits) (20 bits) LSB (18 bits)
Note: 1. SD_IN_x digital audio data is truncated to 20 bits.
EEPROM Timing The ATSAM9777 complies with the Atmel AT24Cxx serial CMOS EEPROM. A low-to-high transition of RST initiates the read EEPROM by sequentially reading addresses 0 to 31 from the EEPROM and storing corresponding data into internal registers. The first two EEPROM bytes should be 55H AAH in order for the remaining 29 bytes of the loaded internal registers to be validated. The serial clock SCL for the EEPROM is derived from the PCI bus clock CLK divided by 1024 (nominal 32.2 kHz). The total read time for the EEPROM is 316 cycles (9.8 ms). The EEPROM can be written to by directly controlling the SCL and SDA data lines at I/O byte base + 2. It is the responsibility of the programmer to generate the appropriate SCL and SDA timing.
Power-up/ The ATSAM9777 has a built-in PLL, allowing multiplication by 4 of an incoming clock fre- Reset/Power-down quency to provide the internal clock, the DSP clock and the P16 system clock. When RST is low or if no clock signal is detected on the AC 97 CKIN, then the incoming clock frequency is CLK divided by 3 (11 MHz), which is raised by the PLL at 44 MHz. When RST is high and a clock signal is detected on the AC'97 CKIN, then the incoming clock frequency is CKIN (12.288 MHz), which is raised by the PLL at 49.152 MHz. Additionally, the P16 has the possibility of entering a soft power-down mode by dividing the system clock by 32. Depending on the firmware, the P16 can decide to enter this mode by itself in the case when there is no audio activity or do it under control of the host processor. After a low-to-high transition of RST, the P16 starts executing instructions from a built-in boot- strap ROM. This allows the upload of an initial firmware to the P16 local program/data RAM. This firmware communicates with the host to establish the mapping with the host memory. Firmware execution can then start from host memory.
17 1716B–DRMSD–11/02 Recommended The pinout of the ATSAM9777 has been organized for direct trace connection to the PCI con- Board Layout, LFT nector with no need for a four-layer printed circuit board. Filter As per PCI specification, signal traces should be limited to 1.5 inches (37.5mm). The trace length for the PCI CLK signal should be 2.5 inches ± 0.1 inch (62.5mm ± 2.5mm). •GND, VCC, VC3 distribution, decouplings
All GND, VCC, VC3 pins should be connected. GND + VC3 planes are strongly recommended below the ATSAM9707. The planes should be connected to all ground/+3.3V pins from the PCI connector. Recommended decoupling is 0.1 µF at each corner of the IC with an additional 10 µF bulk decoupling. VCC requires a single 0.1 µF decoupling close to the IC. •LFT The paths between the LFT filter R-C-R and the ATSAM9777 should be short and shielded. The ground return from the LFT filter should be the GND plane from ATSAM9777. The typical LFT filter is shown in Figure 4.
Figure 4. LFT Filter
LFT
C2 R1 2.2 nF 100Ω
C3 10 nF
18 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
Typical Design D C B A of J6 11 1 2 3 1 1 MIC IN J5 J7 LINE IN LINE OUT C34 10uF 5 4 3 2 1 5 4 3 2 1
+
1 2 R17 47K C33 100pF 2.2K 2.2uF 100 2 2 2 2 AGND
R14 R16
47K
+ + + + C32 10nF C9 2.2uF C35 2.2uF R15 C10 2.2uF 1 1 1 1 C36 Tuesday, October 01, 2002 AT SAM9777-TQ EVALUATION BOARD 9777PC1.SHT 1 C31 VREF AGND 0.1uF C ATMEL - DREAM SOUND IC DIVISION Title Size Document NumberDate: Sheet Rev 2 2 J4 1 2 3 HEAD_3 1 2 3 AGND
2 2 AGND
+ + C29 2.2uF 2.2uF C28 1 1 C30 0.1uF 0.1uF AGND 0.1uF 0.1uF AGND 0.1uF 0.1uF R19 0 C22C23 0.1uF C25 C24 C26 C27 GND IC1 AD1819 15 18 13 12 37 24 21 22 19 16 17 23 20 14 36 35 3 3 MIC1 MIC2 CD_L CD_R AUX_L AUX_R CD_GND VIDEO_L VIDEO_R PC_BEEP LINE_IN_L LINE_IN_R PHONE_IN VCC GND MONO_OUT LINE_OUT_L LINE_OUT_R C21 10uF
+
10uF
2 1 2 C8 1
+
AVCC1 VCC1
25 1
AGND1 GND1
26 4
+
2 1 2
+ 1
AVCC2 VCC2
38
9 C20
C7 AGND2 10uF GND2 10uF
42 7 - 24dB digital filter- / Roland voice GS format- compliant Sample sets under- Roland DLS1 license support, ready- for Legacy DLS2 audio support : SoundBlaster(r), Adlib(r), MPU-401, Joystick - Up to 64- Direct3Dsound(tm) Audio channels effects at : 48kHz - reverb, Up chorus, to echo, 64 pitch voices shifting, hardware equalizer, wavetable surround synthesis C19 22pF L2 47uH MAIN FEATURES : 24.576MHz GND RESET SYNC BIT_CLK SDATA_OUT SDATA_IN CS0 CS1 CHAIN_IN CHAIN_CLK VREFOUT VREF AFILT2 AFILT1 FILT_L FILT_R CX3D RX3D XTL_OUT XTL_IN 4 4 VCC 6 5 8 3 2 X1 10 45 46 47 48 28 27 30 29 32 31 34 33 11 AGND C18 22pF PCI BUS SINGLE CHIP MULTIMEDIA SOUND SYSTEM C16 0.1uF VREF VCC GND C17 47nF
+
1 2 VC3 1uF C15
+
1 2 C40 33uF C14 1uF
+
1 2 C13 270pF 2 270pF C37 2.2nF C12
+
VO 1 2
C38 10nF
AGND
GND C11 3 10uF GND GND 5 VC3 5 IC3 VI VCC R18 100 LM3940IMP-3.3 1 GND GND C39 96 88 77 76 36 27 26 11 10 40 49 58 42 14 59 52 53 41 54 55 100 82 81 51 50 30 20 9 1 46 45 44 43 57 73 60 56 P3 P2 P1 P0 LFT VC3 VC3 VC3 VC3 VC3 VC3 VC3 VC3 VC3 SCL SDA VCC GND GND GND GND GND GND GND GND GND CKIN AC_DIN TEST_0 TEST_1 47nF WS_OUT AC_RES# AC_SYNC BCK_OUT AC_DOUT SD_OUT_2 SD_OUT_1 VCC 6 6 IC2 MIDI_OUT MIDI_IN JSB11 JSB21 JSB12 JSB22 JSX1 JSX2 JSY2 JSY1 A_VC3 JSREF A_GND AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C/BE3# C/BE2# C/BE1# C/BE0# PME# IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# PAR GNT# REQ# RST# CLK INTA# SAM9777TQ 2 3 4 5 6 7 8 47 48 64 62 63 61 70 67 66 69 71 68 65 83 84 85 86 87 89 90 91 94 95 97 98 99 18 19 21 22 23 24 25 28 31 32 33 34 35 37 38 39 92 17 29 80 93 12 13 15 16 78 79 74 75 72 47 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 47 C/BE3# C/BE2# C/BE1# C/BE0# PME# IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# PAR GNT# REQ# RST# CLK INTA# R12 R11 10K R13 10K VCC C6 R10 2 0.1uF CLK REQ# AD7 AD5 AD3 AD1 D1 AD31 AD29 AD27 AD25 AD23 AD21 AD19 AD17 IRDY# PERR# C/BE1# AD14 AD12 AD10 GND VCC VCC GND GND GND GND GND GND GND GND GND GND GND VCC VCC C/BE3# C/BE2# DEVSEL# AD8 1 1N4148 10nF C5 4.7K R3 R4 4.7K 7 7 10nF 4 25 31 36 41 43 54 19 59 2 40 42 1 49 16 10 14 9 11 5 6 61 62 20 21 23 24 27 29 30 32 45 47 48 52 53 55 56 58 8 3 15 17 22 28 34 38 46 57 18 26 33 35 44 7 60 37 39 VCC C4 +5V +5V +5V +5V CLK TCK RSD RSD -12V TDO GND GND GND GND GND GND GND GND GND 10nF +VIO +VIO C3 AD31 AD29 AD27 AD25 AD23 AD21 AD19 AD17 AD14 AD12 AD10 AD08 AD07 AD05 AD03 AD01 +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V REQ# INTB# INTD# IRDY# LOCK# PERR# SERR# M66EN R2 4.7K C/BE3# C/BE2# C/BE1# ACK64# DVSEL# PRSNT1 PRSNT2 C2 J3 PCIB 10nF R1
+
2 2.2K 1 4.7K VCC 2.2K 2.2K C1 10uF R8 R9 R6 R7 2.2K GND L1 47uH R5 47 J2 TRST# +12V TMS TDI +5V INTA# INTC# +5V RSD +VIO RSD RSD RST# +VIO GNT# GND PME# AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +VIO REQ64# +5V +5V PCIA 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 GND VC3 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 VCC VCC VCC VCC GND GND GND GND GND GND GND GND IDSEL J1 DB15 PLEASE REFER TO ATSAM9777 DATA SHEET AD30 AD28 AD26 AD24 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# PAR AD15 AD13 AD11 AD9 C/BE0# AD6 AD4 AD2 AD0 8 8 INTA# RST# GNT# PME# WARNING : DECOUPLING CAPS NOT SHOWN ! D C B A
19 1716B–DRMSD–11/02 Mechanical Dimensions
Figure 5. 100-lead Plastic Quad Flat Pack – Rectangular
Package Dimensions (in millimeters) Table 14. 100-lead Plastic Quad Flat Pack – Rectangular Dimension Min Typ Max A3.40 A1 0.25 A2 2.55 2.8 3.05 D23.90 D1 20.00 E17.90 E1 14.00 L 0.65 0.88 1.03 P0.65 B 0.22 0.38
20 ATSAM9777 1716B–DRMSD–11/02 ATSAM9777
Table 15. 100-lead Thin PQFP Package – Square Dimension Min Typ Max A 1.401.501.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 D16.00 D1 14.00 E16.00 E1 14.00 L 0.450.600.75 P0.65 B 0.170.220.27
21 1716B–DRMSD–11/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory RF/Automotive 2325 Orchard Parkway 2325 Orchard Parkway Theresienstrasse 2 San Jose, CA 95131 San Jose, CA 95131 Postfach 3535 TEL 1(408) 441-0311 TEL 1(408) 441-0311 74025 Heilbronn, Germany FAX 1(408) 487-2600 FAX 1(408) 436-4314 TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Europe Microcontrollers Atmel Sarl 2325 Orchard Parkway 1150 East Cheyenne Mtn. Blvd. Route des Arsenaux 41 San Jose, CA 95131 Colorado Springs, CO 80906 Case Postale 80 TEL 1(408) 441-0311 TEL 1(719) 576-3300 CH-1705 Fribourg FAX 1(408) 436-4314 FAX 1(719) 540-1759 Switzerland TEL (41) 26-426-5555 La Chantrerie Biometrics/Imaging/Hi-Rel MPU/ FAX (41) 26-426-5500 BP 70602 High Speed Converters/RF Datacom 44306 Nantes Cedex 3, France Avenue de Rochepleine Asia TEL (33) 2-40-18-18-18 BP 123 Room 1219 FAX (33) 2-40-18-19-60 38521 Saint-Egreve Cedex, France Chinachem Golden Plaza TEL (33) 4-76-58-30-00 77 Mody Road Tsimhatsui ASIC/ASSP/Smart Cards FAX (33) 4-76-58-34-80 East Kowloon Zone Industrielle Hong Kong 13106 Rousset Cedex, France TEL (852) 2721-9778 TEL (33) 4-42-53-60-00 FAX (852) 2722-1369 FAX (33) 4-42-53-60-01
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© Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.
AT ME L ®, Dream® and CleanWave® are the registered trademarks of Atmel. Windows®95/98 and Windows®2000 are the registered trademarks of Microsoft Corporation. GS® Roland® and rSounds® are the registered trademarks of the Roland Company. Dolby® is the registered trademark of Dolby Laboratory Licensing Corporation. Direct Music™, Direct3DSound™ and Direct Sound™ are the trademarks of Printed on recycled paper. Microsoft Corporation. Other terms and product names may be the trademarks of others. 1716B–DRMSD–11/02 0M