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E200z6 Powerpc ™ Core e200z6RM 6/2004 Rev. 0 e200z6 PowerPC™ Core Reference Manual Contents SectionParagraph Page Number Title Number ChapterContents 1 e200z6 Overview 1.1 Overview of the e200z6....................................................................................... 1-1 1.1.1 Features............................................................................................................ 1-3 1.2 Programming Model ............................................................................................ 1-4 1.2.1 Register Set...................................................................................................... 1-4 1.3 Instruction Set ...................................................................................................... 1-6 1.4 Interrupts and Exception Handling ...................................................................... 1-7 1.4.1 Exception Handling ......................................................................................... 1-8 1.4.2 Interrupt Classes .............................................................................................. 1-8 1.4.3 Interrupt Types................................................................................................. 1-9 1.4.4 Interrupt Registers............................................................................................ 1-9 1.5 Microarchitecture Summary .............................................................................. 1-12 1.5.1 Instruction Unit Features ............................................................................... 1-13 1.5.2 Integer Unit Features ..................................................................................... 1-13 1.5.3 Load/Store Unit (LSU) Features.................................................................... 1-14 1.5.4 L1 Cache Features ......................................................................................... 1-14 1.5.5 MMU Features............................................................................................... 1-14 1.5.6 e200z6 System Bus (Core Complex Interface) Features............................... 1-15 1.5.7 Nexus3 Module Features ............................................................................... 1-15 1.6 Legacy Support of PowerPC Architecture......................................................... 1-15 1.6.1 Instruction Set Compatibility......................................................................... 1-16 1.6.1.1 User Instruction Set ................................................................................... 1-16 1.6.1.2 Supervisor Instruction Set.......................................................................... 1-16 1.6.2 Memory Subsystem ....................................................................................... 1-16 1.6.3 Exception Handling ....................................................................................... 1-16 1.6.4 Memory Management.................................................................................... 1-17 1.6.5 Reset............................................................................................................... 1-17 1.6.6 Little-Endian Mode........................................................................................ 1-17 Contents iii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number Chapter 2 Register Model 2.1 PowerPC Book E Registers ................................................................................. 2-3 2.2 e200z6-Specific Registers.................................................................................... 2-5 2.3 Processor Control Registers................................................................................. 2-7 2.3.1 Machine State Register (MSR) ........................................................................ 2-7 2.3.2 Processor ID Register (PIR) ............................................................................ 2-9 2.3.3 Processor Version Register (PVR)................................................................... 2-9 2.3.4 System Version Register (SVR)..................................................................... 2-10 2.4 Registers for Integer Operations ........................................................................ 2-11 2.4.1 General-Purpose Registers (GPRs)................................................................ 2-11 2.4.2 Integer Exception Register (XER)................................................................. 2-11 2.5 Registers for Branch Operations........................................................................ 2-12 2.5.1 Condition Register (CR) ................................................................................ 2-12 2.5.1.1 CR Setting for Integer Instructions............................................................ 2-14 2.5.1.2 CR Setting for Store Conditional Instructions........................................... 2-14 2.5.1.3 CR Setting for Compare Instructions ........................................................ 2-14 2.5.2 Link Register (LR)......................................................................................... 2-15 2.5.3 Count Register (CTR).................................................................................... 2-16 2.6 SPE and SPFP APU Registers ........................................................................... 2-16 2.6.1 Signal Processing/Embedded Floating-Point Status and Control Register (SPEFSCR).................................................................................. 2-16 2.6.2 Accumulator (ACC)....................................................................................... 2-19 2.7 Interrupt Registers.............................................................................................. 2-19 2.7.1 Interrupt Registers Defined by Book E.......................................................... 2-19 2.7.1.1 Save/Restore Register 0 (SRR0)................................................................ 2-20 2.7.1.2 Save/Restore Register 1 (SRR1)................................................................ 2-20 2.7.1.3 Critical Save/Restore Register 0 (CSRR0)................................................ 2-20 2.7.1.4 Critical Save/Restore Register 1 (CSRR1)................................................ 2-21 2.7.1.5 Data Exception Address Register (DEAR)................................................ 2-21 2.7.1.6 Interrupt Vector Prefix Register (IVPR).................................................... 2-22 2.7.1.7 Interrupt Vector Offset Registers (IVORs) ................................................ 2-22 2.7.1.8 Exception Syndrome Register (ESR) ........................................................ 2-24 2.7.2 e200z6-Specific Interrupt Registers............................................................... 2-25 2.7.2.1 Debug Save/Restore Register 0 (DSRR0) ................................................. 2-25 2.7.2.2 Debug Save/Restore Register 1 (DSRR1) ................................................. 2-26 2.7.2.3 Machine Check Syndrome Register (MCSR)............................................ 2-26 2.8 Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ....................................... 2-27 2.9 Timer Registers.................................................................................................. 2-28 2.9.1 Timer Control Register (TCR)....................................................................... 2-29 2.9.2 Timer Status Register (TSR).......................................................................... 2-31 iv e200z6 PowerPC Core Reference Manual PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number 2.9.3 Time Base (TBU and TBL) ........................................................................... 2-32 2.9.4 Decrementer Register .................................................................................... 2-34 2.9.5 Decrementer Auto-Reload Register (DECAR).............................................. 2-34 2.10 Debug Registers................................................................................................. 2-35 2.10.1 Debug Address and Value Registers.............................................................. 2-35 2.10.1.1 Instruction Address Compare Registers (IAC1–IAC4)............................. 2-35 2.10.1.2 Data Address Compare Registers (DAC1–DAC2).................................... 2-36 2.10.2 Debug Counter Register (DBCNT) ............................................................... 2-36 2.10.3 Debug Control and Status Registers (DBCR0–DBCR3)............................... 2-37 2.10.3.1 Debug Control Register 0 (DBCR0).......................................................... 2-37 2.10.3.2 Debug Control Register 1 (DBCR1).......................................................... 2-40 2.10.3.3 Debug Control Register 2 (DBCR2).......................................................... 2-42 2.10.3.4 Debug Control Register 3 (DBCR3).......................................................... 2-43 2.10.4 Debug Status Register (DBSR)...................................................................... 2-50 2.11 Hardware Implementation-Dependent Registers............................................... 2-51 2.11.1 Hardware Implementation-Dependent Register 0 (HID0)............................. 2-52 2.11.2 Hardware Implementation-Dependent Register 1 (HID1)............................. 2-54 2.12 Branch Target Buffer (BTB) Registers .............................................................
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