SPARC Joint Programming Specification 1 Implementation Supplement: Sun Ultrasparc III
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SPARC Joint Programming Specification 1 Implementation Supplement: Sun UltraSPARC III Sun Microsystems Proprietary/Need-to-Know JRC Contributed Material Working Draft 1.0.5, 10 Sep 2002 Part No.: 806-6754-1 Working Draft 1.0.5, 10 Sep 2002 Copyright 2001 Sun Microsystems, Inc., 901 San Antonio Road, Palo Alto, California 94303 U.S.A. All rights reserved. Portions of this document are protected by copyright 1994 SPARC International, Inc. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Third-party software, including font technology, is copyrighted and licensed from Sun suppliers. Parts of the product may be derived from Berkeley BSD systems, licensed from the University of California. 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Sun détient une licence non exclusive de Xerox sur l’interface d’utilisation graphique Xerox, cette licence couvrant également les licenciés de Sun qui mettent en place l’interface d’utilisation graphique OPEN LOOK et qui en outre se conforment aux licences écrites de Sun. CETTE PUBLICATION EST FOURNIE "EN L’ETAT" ET AUCUNE GARANTIE, EXPRESSE OU IMPLICITE, N’EST ACCORDEE, Y COMPRIS DES GARANTIES CONCERNANT LA VALEUR MARCHANDE, L’APTITUDE DE LA PUBLICATION A REPONDRE A UNE UTILISATION PARTICULIERE, OU LE FAIT QU’ELLE NE SOIT PAS CONTREFAISANTE DE PRODUIT DE TIERS. CE DENI DE GARANTIE NE S’APPLIQUERAIT PAS, DANS LA MESURE OU IL SERAIT TENU JURIDIQUEMENT NUL ET NON AVENU. Please Recycle Contents 1. Overview 1 1.1 Navigating the UltraSPARC III Implementation Supplement 1 1.2 Fonts and Notational Conventions 2 1.3 The UltraSPARC III Processor 2 1.3.1 Component Overview 2 1.3.2 Instruction Issue Unit (IIU) 4 1.3.3 Integer Execution Unit (IEU) 5 1.3.4 Data Cache Unit (DCU) 5 1.3.5 Floating Point and Graphics Unit (FGU) 6 1.3.6 External Memory Unit (EMU) 6 1.3.7 System Interface Unit (SIU) 7 1.4 Chip Differences from UltraSPARC I, II 7 1.4.1 Bootbus Limitations 8 1.4.2 Instruction Set Extensions 8 VIS Extensions 8 Interval Arithmetic Support 9 1.4.3 Instruction Differences 9 1.4.4 Memory Subsystem 10 Caches 10 Cache Flushing 11 Translation Lookaside Buffers (TLBs) 12 1.4.5 Interrupts 13 1.4.6 Address Space Size 13 1.4.7 Error Correction 13 Contents iii Sun Microsystems Proprietary/Confidential – JRC Contributed Material 1.4.8 Registers 14 Address Space Identifier (ASI) Registers 14 Ancillary State Registers (ASRs) 15 1.4.9 Noncacheable Store Compression 15 1.4.10 Summary of Differences 16 2. Definitions and Acronyms 19 3. Architectural Overview 23 4. Data Formats 25 4.2.3 Floating-Point, Quad-Precision 25 4.3 Graphics Data Formats 25 5. Registers 27 5.1.7 Floating-Point State Register (FSR) 27 FSR_nonstandard_fp (NS) 27 FSR_floating-point_trap_type (ftt) 28 FSR_current_exception (cexc) 28 5.2.1 PSTATE Register 29 5.2.9 Version (VER) Register 29 5.2.11 Ancillary State Registers (ASRs) 30 Performance Control Register (PCR) (ASR 16) 30 Performance Instrumentation Counter (PIC) Register (ASR 17) 30 Dispatch Control Register (DCR) (ASR 18) 30 5.2.12 Registers Referenced Through ASIs 33 Data Cache Unit Control Register (DCUCR) 33 Data Watchpoint Registers 35 Instruction Trap Register 36 6. Instructions 37 6.1 Processor Pipeline 37 6.1.1 Instruction-Fetch Stages 39 A-stage (Address Generation) 39 P-stage (Predictor Address Generation) 39 F-stage (Fetch) 39 iv SPARC V9 JPS1 Implementation Supplement: Sun UltraSPARC-III • Working Draft 1.0.5, 10 Sep 2002 Sun Microsystems Proprietary/Confidential – JRC Contributed Material B-stage (Branch Target Computation) 39 6.1.2 Instruction Issue Stages 40 I-stage (Instruction Issue) 40 R-stage (Register) 40 6.1.3 Integer Instruction Execution: E-stage (Execute) 41 6.1.4 Floating-Point and VIS Instruction Execution 42 C-stage (Cache) 42 M-stage (Miss) 42 W-stage (Write) 42 X-stage (Extend) 43 6.1.5 Trap (T) and Done (D) Stages 43 T-stage (Trap) 43 D-stage (Done) 43 6.2 Grouping Rules 43 6.2.1 Execution Order 44 6.2.2 Integer Register Dependencies to Instructions in the MS Pipeline 44 6.2.3 Integer Instructions Within a Group 45 6.2.4 Same-Group Bypass 45 6.2.5 Floating Point Unit Operand Dependencies 45 Latency and Destination Register Addresses 45 PDIST Special Cases 46 Helpers 46 Floating-Point Grouping Rules 47 6.3 Conditional Moves 51 6.4 Instruction Latencies and Dispatching Properties 52 7. Traps 61 7.1.2 Error_state 61 7.4.2 Trap Type (TT) 61 8. Memory Models 63 8.1 Programmer-Visible Properties of Models 64 8.1.1 Differences Between Memory Models 64 8.1.2 Current Memory Model 65 8.2 Memory Location Identification 65 Working Draft 1.0.5, 10 Sep 2002 Contents v Sun Microsystems Proprietary/Confidential – JRC Contributed Material 8.3 Memory Accesses and Cacheability 65 8.3.1 Coherence Domains 66 Cacheable Accesses 66 Noncacheable and Side-Effect Accesses 66 8.3.2 Global Visibility and Memory Ordering 67 8.4 Memory Synchronization 68 8.4.1 MEMBAR #Sync 68 8.4.2 MEMBAR Rules 68 8.5 Atomic Operations 69 8.6 Nonfaulting Load 71 8.7 Prefetch Instructions 71 8.8 Block Loads and Stores 72 8.9 I/O and Accesses with Side Effects 72 8.9.1 Instruction Prefetch to Side-Effect Locations 73 8.9.2 Instruction Prefetch Exiting Red State 73 8.9.3 UltraSPARC III Internal ASIs 74 8.10 Store Compression 74 A. Instruction Definitions: UltraSPARC III Extensions 77 A.2 Alignment Instructions (VIS I) 78 A.3 Three-Dimensional Array Addressing Instructions (VIS I) 78 A.4 Block Load and Store Instructions (VIS I) 79 A.5 Byte Mask and Shuffle Instructions (VIS II) 83 A.13 Floating-Point Add and Subtract 83 A.26 Load Floating-Point 84 A.27 Load Floating-Point Alternate 84 A.30 Load Quadword, Atomic 84 A.33 Logical Operate Instructions (VIS I) 85 A.35 Memory Barrier 86 A.42 Partial Store (VIS I) 91 A.43 Partitioned Add/Subtract (VIS I) 91 A.44 Partitioned Multiply (VIS I) 92 A.47 Pixel Formatting (VIS I) 92 A.47.5 FPMERGE Instruction 92 A.49 Prefetch Data 93 A.49.1 SPARC V9 Prefetch Variants 93 vi SPARC V9 JPS1 Implementation Supplement: Sun UltraSPARC-III • Working Draft 1.0.5, 10 Sep 2002 Sun Microsystems Proprietary/Confidential – JRC Contributed Material A.55 Set Interval Arithmetic Mode (VIS II) 94 A.59 SHUTDOWN Instruction (VIS I) 94 A.61 Store Floating Point 94 A.62 Store Floating Point into Alternate Space 95 B.