EOS and ESD on ADC TI Precision Labs

EOS and ESD on ADC TI Precision Labs – ADCs

Presented by Alex Smith Prepared by Dale Li

1 ESD vs. EOS – What’s the Difference?

ESD EOS • Electrostatic discharge • Electrical overstress • Short duration event (1-100ns) • Longer duration event • High voltage (kV) – Milliseconds or more – Can be continuous • Fast edges • Lower voltage • Both “in-circuit” and “out-of-circuit” – May be just beyond absolute maximum ratings • “In-circuit” event only

2 EOS from Fault or Overdriven

Fault Conditions  Harsh electrical environment Transient  High voltage circuit in the system Transient

 Improper power up sequencing Ground  Hot-swap connection and disconnection  Loss of power supply but input signal is applied  Apply bipolar signal to unipolar input ADC  Miswiring  Other conditions violating the absolute maximum specifications

3 Internal Clamp/Protection on Data Converters

1. Input Steering diodes: 2. Back-to-Back Zener diode: 3. SCR-Based input:

AVDD or VREF Input Clamp SCR - Based Protection ESD Protection*

AIN_P AIN_nP AIN_nP

ADC ADC ADC AFE AFE Core Core Core

AIN_M AIN_nGND AIN_nGND

*Bi-directional SCR example 4 SCR-Based ESD Structure and Latch-up VDD

I2 RNWELL

Q1 (PNP) Equivalent circuit of SCR I/O I/O Q2 (NPN)

RSUB I1

GND Cross section of typical SCR design structure Current • SCR (silicon controlled rectifier) is a parasitic structure. Overshoot and undershoot outside the normal operating voltage and current levels can cause Latch-up and damage the device. • Trigger Latch-up: Triggering Tholding Voltage  Applied voltage > VH and applied current > IH Current • Terminate Latch-up state: IH  A latch-up remains even after applied signal has been removed and IT requires a power supply shut down to remove the low impedance path. VH VT Voltage

* Source: 1. www.ti.com/lit/wp/scaa124/scaa124.pdf. 2. https://en.wikipedia.org/wiki/Latch-up Why use SCR-Based ESD protection

• Input Signal Voltage > Power Supply. 7 Forward Diode • SCR is used as effective input ESD 6 GGNMOS protection element to sustain a higher

) 5

A ESD level within a smaller layout area ( 4 because:

Current Current 3  Lower holding voltage

2 Reverse  Significantly lower power dissipation Diode SCR 1  Robust ESD protection

0 0 5 10 15 20 25 Voltage (V) Vhold

* Electrostatic Discharge Protection Circuit for High-Speed Mixed-Signal Circuits by Hossein Sarbishaei. 6 Input Diode to REF/AVDD

ADS8860 Input Stage ADS9224R Input Stage

96 120 AINP AINP 1p 16p 4p Vref 55p AVDD

4p 55p 1p 16p 96 120 AINN AINN

• Internal diodes are connected to REF: ADS8860,ADS9110,ADS8900B… • Internal diodes are connected to AVDD: ADS9224R,ADS8168… • Absolute Maximum Input Range:  Analog input voltage is limited to -0.3V to REF+0.3V (or AVDD+0.3V)  Input current is generally limited to -10mA to 10mA 7 Input ESD Diode turns on and Impacts Voltage Reference

Vin_ADC

REF6050 4.06V 5.0V REF (Scope Check) Reference ADC_min: +3V +3V - 300mV +12V - 800mV Vin_ADC Rflt 19mV - AVDD DVDD

+ + OPA828 Vg Cfilt -12V ADS8860 -16mV Rflt Overdriven signal GND REF

• When input signal is overdriven, a disturbance is found on REF signal (or AVDD) which can degrade the performance if the REF (or AVDD) is shared.

• The higher overdriven signal, the worse disturbance impact. 8 Input Protection on ADC with AFE

ADS8588S Input Stage: AVDD DVDD ADS8688/81 Input Stage: AVDD DVDD

RFB RFB SCR - Based Input Clamp 2.5V 4.096V Buffer ESD Protection Buffer Protection Reference AVDD Reference

1M AIN_nP 1M AIN_nP

AVDD 16-Bit 16-Bit ADC 3rd-Order ADC PGA LPF SAR SAR Driver PGA LPF Driver ADC ADC 1M 1M AIN_nGND AIN_nGND

RFB RFB VB

AGND DGND AGND DGND

• Typically 5V supply voltage and ±12V input range, so ESD diode to supply will not work • Clamp is implemented with back-to-back Zener diodes or SCR input.  ABS MAX Input voltage limit: ±15V on ADS8588S, and ±20V on ADS8681/8688

 ABS MAX Input current Max Limit = ±10mA 9 Thanks for your time! Please try the quiz.

10 Questions: EOS and ESD on ADC

1. For the circuit shown below, what kind of internal ESD structure is NOT practical? 3.3V a. Input ESD steering diodes 5V b. Back-to-back Zener diodes AVDD DVDD RFB 2.5V c. SCR type ESD structure Buffer Reference

1MΩ

16-Bit 3rd-Order ADC PGA SAR ±10V LPF Driver ADC 1MΩ

RFB

AGND DGND

11 Questions: EOS and ESD on ADC

2. (T/F) The internal ESD protection structures are designed primarily to protect the device during assembly and test (i.e. out of circuit events). a. True b. False

3. Which type of ESD structure will trigger on and remain on until power is cycled? a. Input ESD steering diodes b. Back-to-back Zener diodes c. SCR type ESD structure

12 Questions: EOS and ESD on ADC

4. Which of the following does NOT apply to ESD? a. High voltage (kV) b. Fast edges c. Long duration event of milliseconds or more. d. Both “in-circuit” and “out-of-circuit” REF6050 5.0V 5. For the circuit below, what is the maximum input voltage? Reference +3V +3V

a. 5.0V AVDD DVDD b. 5.3V c. 7V Vin(AbsMax) ADS8860 d. 12V GND

13 Thanks for your time!

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