Vivado Customer Overview with 4 Modules
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Announcing Vivado™ Built from the Ground Up for the Next Decade of ‘All Programmable’ Devices © Copyright 2012 Xilinx Announcing Vivado Design Suite IP & System Centric Next Generation Design Environment For the Next Decade of ‘All Programmable’ Devices Accelerating Integration & Implementation up to 4X Built from the Ground Up for the Next Decade of Programmable Design Page 3 © Copyright 2012 Xilinx Why Now? Programmable Logic Devices ALL Programmable Devices Enables Programmable Enables Programmable ‘Logic’ Systems ‘Integration’ Page 4 © Copyright 2012 Xilinx Bottlenecks are Shifting System Integration Bottlenecks – Design and IP reuse – Integrating algorithmic and RTL level IP – Mixing DSP, embedded, connectivity, logic – Verification of blocks and “systems” Implementation Bottlenecks – Hierarchical chip planning – Multi-domain and multi-die physical optimization – Predictable ‘design’ vs. ‘timing’ closure – Late ECOs and rippling effect of changes Page 5 © Copyright 2012 Xilinx Vivado: Accelerating Productivity up to 4X Accelerating Integration IP & System-centric Vivado Next up to Integration with Fast Generation 4X Verification Design System RTL to Bit-stream with Iterative Approach 1X Fast, Hierarchical and Deterministic Closure Accelerating Automation w/ ECO Implementation 1X up to 4X Page 6 © Copyright 2012 Xilinx Vivado Design Suite Elements Integrated Design Environment Shared Scalable Data Model Data Scalable Shared Accelerating IP & System-centric Integration Integration with Fast Analysis and Debug Verification Fast, Hierarchical and Accelerating Deterministic Closure Implementation Automation w/ ECO Scalable to 100M Gates Page 7 © Copyright 2012 Xilinx Vivado Key Enabling Technologies Shared, Scalable Data Model Progressive estimation accuracy across the entire flow Reduced iterations late in the cycle Estimation IP RTL Design Synthesis Place & Route Integration Shared, Scalable Data Model Shares design information between RTL Schematics Placement implementation steps entity FIR is port (clk : in – Ensures fast convergence and timing closure rst : in din : in Tool Highly efficient memory utilization Code Settings – Scalable to future families > 10M logic cells Changes Placement Edits (100M Gates) Timing Report Timing Path #1 Timing Path #2 Enables cross-probing across the Timing Path #3 entire design Reports Page 8 © Copyright 2012 Xilinx Vivado Design Suite Elements Integrated Design Environment ESL Algorithm Shared Scalable Data Model Data Scalable Shared IP Synthesis Accelerating IP & System-centricSystems Debug and Analysis Analysis and Debug Integration IntegrationIP Assembly with Integration Fast Stds Based IP ReuseVerification Fast Simulation & HW Co-sim Scalable to 100M Gates Page 9 © Copyright 2012 Xilinx IP-Centric Integration with Fast Verification Hand-coded Vivado HLS Memory Interface VHDL C Design Time 12 1 Memory Interfaces (weeks) Processor PCIe Display Latency 37 21 System (ms) Memory 134 (16%) 10 (1%) (RAMB18E1) Embedded Interconnect Memory 273 (65%) 138 (33%) rd (RAMB36E1) User IP Xilinx IP 3 Party IP Registers 29686 (9%) 14263 (4%) Processing Datapath LUTs 28152 (18%) 24257 (16%) ESL Algorithm IP Synthesis IP & System-centricIP & HW-SW IntegrationIP Assembly with Integrator Fast Stds Based IP ReuseVerification Runtime Runtime Tcl SDC Fast Simulation & HW Co-Sim w/ HW Co-sim Vivado ISim Page 10 © Copyright 2012 Xilinx Package Designs into System-Level IP for Reuse Memory Standardized IP-XACT Interface representation Memory Interfaces Processor PCIe Display Vivado IP IntegratorSystem Source (C, RTL, IP, etc) Embedded Interconnect Simulation Models User IP Xilinx IP 3rd Party IP Xilinx IP Documentation IP Packager Processing Datapath Example Designs 3rd Party IP Test Bench User IP Share IP within your team, project or company 3rd party IP delivered with a common look and feel Reuse IP at any point in the implementation process Reuse in different designs – Source, placed, or placed and routed Reuse multiple times Page 11 © Copyright 2012 Xilinx Seamless IP Access and Customization Integrated IP catalog – Powerful search capabilities – Single-click access to IP functionality and collateral IP customization and generation – Instant access to customization GUI – Generate output products in project or remote directory – Customize graphically or via Tcl Page 12 © Copyright 2012 Xilinx Selectable IP Targets Flexible output targets – On-demand generation of IP output targets – Generate testbench, example, etc. Integrated example designs – Evaluate IP directly as an instantiated source in a Vivado project Multiple options for IP synthesis – IP sources with overall design – IP pre-synthesized as a netlist prior to design synthesis Page 13 © Copyright 2012 Xilinx IP Packager: IP-XACT IEEE 1685 IP-XACT is an industry standard way to represent data about IP (meta-data) – Port information – Latency – Configurable parameters – Etc. ASCII XML based Enables IP to be used in multiple vendor tools flows Page 14 © Copyright 2012 Xilinx IP Packager: Generate IP-XACT for your IP Wizard-based flow automates generation of IP-XACT IP Prepare an IP for distribution to customers or colleagues Many pieces of meta-data automatically inferred Users can add additional meta-data Page 15 © Copyright 2012 Xilinx IP Packager: Create System-Level IP 1. Run IP Packager from Tools menu 2. Package sources from Vivado project as IP 3. Provide information to uniquely identify your IP Page 16 © Copyright 2012 Xilinx Extensible IP Catalog: Add Packaged IP 1. Unzip IP to a local directory 2. Right-click on IP Catalog 3. Add directory to IP Catalog Page 17 © Copyright 2012 Xilinx Vivado IP Integrator A graphical design environment to enable rapid and accurate connection of complex IP – Connections made at the interface level, not the individual signal level – Automatic setting and propagation of IP parameters – Automated generated of RTL – Full support for arbitrary levels of design hierarchy – Capable of processor-based or non-processor based design creation Tight integration with Vivado IP Packager flow for rapid IP and subsystem reuse Page 18 © Copyright 2012 Xilinx IP Integrator User Interface Hierarchy Support System Hierarchy Interface Connections View with Real-time DRCs TCL Console Page 19 © Copyright 2012 Xilinx IP Integrator Real-time DRCs IP and system configuration rules can be very complex – User will require help to correctly connect IPs IP Integrator provides immediate feedback on design errors/optimization Page 20 © Copyright 2012 Xilinx IP Integrator Real-time DRCs (cont) All IP Integrator automation services can issue DRCs from: – IP configuration XGUI – IP specific automation services – Built-in automation services – System optimization services Not just errors: Intelligent DRCs may also include solutions – Goal: Proposed solutions can be actual Tcl code, not just passive text GUI collects, prioritize and reports DRCs to the user so they can make informed choices Apply solution 1 Page 21 © Copyright 2012 Xilinx Vivado IP Integrator – Demo Memory Interface Memory Interfaces Processor PCIe Display Graphical design to enable rapid and System accurate connection of complex IP Embedded Interconnect – Connections made at the interface level, User IP Xilinx IP 3rd Party IP not the individual signal level Processing Datapath – Automatic setting and propagation of IP parameters – Automated generation of RTL – Full support for arbitrary levels of design hierarchy – Capable of processor-based or non-processor based design creation Tight integration with Vivado IP Packager flow for rapid IP and subsystem reuse Start Demo > Page 22 © Copyright 2012 Xilinx Vivado High-Level Synthesis Accelerates IP Development and Design Space Exploration Ideal for DSP, video and high performance compute applications QoR that rivals hand coded RTL – Fast compilation and design exploration – Algorithm/architecture feasibility Comprehensive coverage – C/C++/SystemC – Arbitrary precision – Floating-point Accelerated verification – 2 to 3 orders of magnitude faster than RTL for larger design BDTI certified and production proven at 20+ customer sites Page 23 © Copyright 2012 Xilinx ESL Design Methodology Functionality High-Level Synthesis Model Model-Based ESL Design Architecture Synthesis RTL Gates Place & Route Netlist Silicon Layout Page 24 © Copyright 2012 Xilinx ESL Solutions Electronic System Level ESL High-Level Synthesis Model-Based Design HLS MBD Language Structure Input Method C-based (functions) C-based (bus-functional Simulation models) Behavior Signals Operation Level (no clocks/resets) High-Level Synthesis IP Implementation Method (allocation/scheduling) • Flexibility • Available libraries • Architecture exploration • Result analysis/visualization Benefits Portability Verification speed Quality of results Page 25 © Copyright 2012 Xilinx Model Based Design – System Generator Easily create System Generator DSP sources Add existing files or create new Simulink models Page 26 © Copyright 2012 Xilinx Model Based Design – System Generator Fully integrated into the Vivado IDE – Launch System Generator from the Vivado IDE Page 27 © Copyright 2012 Xilinx HLS: What’s different? Established specification language – C/C++/SystemC standards Quality of Results – Extracting parallel execution from sequential specification Accommodates datapath and control Complement RTL-based tools Acknowledgement of verification needs Consideration for physical interfaces Source: IEEE Design&Test of Computers (2009) Volume: 26, Issue: 4, Publisher: IEEE Computer