View of Methodology 21

KNOWLEDGE-GUIDEDMETHODOLOGYFOR SOFTIPANALYSIS BY BHANUPRATAPSINGH Submitted in partial fulfillment of the requirements For the degree of Doctor of Philosophy Dissertation Advisor: Dr. Christos Papachristou Department of Electrical Engineering and Computer Science CASEWESTERNRESERVEUNIVERSITY January 2015 CASEWESTERNRESERVEUNIVERSITY SCHOOLOFGRADUATESTUDIES we hereby approve the thesis of BHANUPRATAPSINGH candidate for the PH.D. degree. chair of the committee DR.CHRISTOSPAPACHRISTOU DR.FRANCISMERAT DR.DANIELSAAB DR.HONGPINGZHAO DR.FRANCISWOLFF date AUG 2 1 , 2 0 1 4 ∗ We also certify that written approval has been obtained for any propri- etary material contained therein. Dedicated to my family and friends. CONTENTS 1 introduction1 1.1 Motivation and Statement of Problem . 1 1.1.1 Statement of Problem . 6 1.2 Major Contributions of the Research . 7 1.2.1 Expert System Based Approach . 7 1.2.2 Specification Analysis Methodology . 9 1.2.3 RTL Analysis Methodology . 9 1.2.4 Spec and RTL Correspondence . 10 1.3 Thesis Outline . 10 2 background and related work 11 Abstract . 11 2.1 Existing Soft-IP Verification Techniques . 11 2.1.1 Simulation Based Methods . 11 2.1.2 Formal Techniques . 13 2.2 Prior Work . 15 2.2.1 Specification Analysis . 15 2.2.2 Reverse Engineering . 17 2.2.3 IP Quality and RTL Analysis . 19 2.2.4 KB System . 20 3 overview of methodology 21 Abstract . 21 3.1 KB System Overview . 21 3.1.1 Knowledge Base Organization . 24 3.2 Specification KB Overview . 26 3.3 RTL KB Overview . 29 iv contents v 3.4 Confidence and Coverage Metrics . 30 3.5 Introduction to CLIPS and XML . 31 3.5.1 CLIPS Expert System Shell . 31 3.5.2 XML ............................... 32 4 specification knowledge base 36 Abstract . 36 4.1 Spec-KB . 36 4.2 Specification Knowledge Representation Scheme . 37 4.2.1 Specification Ontology . 37 4.2.2 Automating Ontology Generation . 43 4.3 Specification Knowledge Extraction Scheme . 47 4.3.1 Spec-Extractor Tool . 47 4.3.2 Specification Rule-Base . 50 4.3.3 Metrics for Specification Analysis . 53 5 rtl knowledge base 57 Abstract . 57 5.1 RTL-KB . 57 5.2 RTL Knowledge Representation Scheme . 58 5.2.1 RTL-CLIPS . 58 5.2.2 Property Based Model . 59 5.3 RTL Knowledge Extraction . 62 5.3.1 RTL Rule Base . 62 5.3.2 RTL Evaluation in CLIPS . 67 5.3.3 RTL Analysis Example . 68 6 specification and rtl correspondence 70 Abstract . 70 6.1 Back Annotation . 70 6.1.1 Specification Tabular Objects . 71 6.1.2 Specification Drawing Objects . 78 contents vi 6.2 Results: Spec and RTL correspondence . 82 7 conclusion and future work 85 i appendix 87 a processing tabular objects 88 a.1 HTML Register Table and Register Test-bench Generation . 88 b processing drawing objects 102 b.1 Extraction of FSM Specfication from SVG . 102 bibliography 110 LISTOFFIGURES Figure 1 Design completion time compared to the project original schedule [1]........................... 2 Figure 2 Functional Bugs Resulting in Increasing ASIC Respins . 2 Figure 3 Verification effort in a project [1].............. 4 Figure 4 Cost of fixing bug vs Time [2]................ 5 Figure 5 Components of an Expert System [3]............ 8 Figure 6 Simulation Based Verification . 12 Figure 7 Formal verification process . 14 Figure 8 Knowledge Base Generation . 22 Figure 9 Knowledge Base Application for third-Party IP Analysis 23 Figure 10 OMAP4470 application processor from Texas Instruments [4]................................ 24 Figure 11 Marvell ARMADA 510 (88AP510) Application Processor [5]................................ 25 Figure 12 FreeScale i.MX25 Application Processor [6]........ 26 Figure 13 Knowledge Base organization overview . 27 Figure 15 Confidence factor merging using parallel combination formula . 30 Figure 14 Fragment of semantic network for peripheral interface domain . 35 Figure 16 Spec Analysis Flow . 38 Figure 17 Fragment of ontology model for FPU design domain . 40 Figure 18 Tabular representation of IEEE-754 Floating point ontology 42 Figure 19 Overview of Ontology Automation system . 44 vii List of Figures viii Figure 20 Frequency and Location based visualization of words in a FPU Spec . 45 Figure 21 Ontology Construction: Statistics of Generated Sugges- tions [7]............................. 46 Figure 22 Iteration: Saturation Point [7]................ 46 Figure 23 Spec Word classification based on Lexical, Syntactic and Spatial Attributes . 49 Figure 24 Fragment of ARM2 design composition knowledge . 52 Figure 25 RTL Analysis Overview . 58 Figure 26 Property based model of a FIFO design . 61 Figure 27 Fragment of pdg for floating point add function . 66 Figure 28 Html annotation report . 69 Figure 29 Back Annotation overview . 71 Figure 30 Proposed IO Description Template . 73 Figure 31 Block diagram generated for ARM2 Core using GraphViz package . 74 Figure 32 Register Specification Template . 76 Figure 33 HTML view of register specification . 77 Figure 34 Register Verification Test bench . 78 Figure 35 FSM diagram drawn in Dia Tool [8]............. 79 Figure 36 FSM specification extraction from SVG diagram . 80 Figure 37 Example Timing Diagram . 81 Figure 38 Corresponding fragment of TDML XML . 81 Figure 39 Wishbone Interface timing diagram drawn using TDML tool and verification of generated assertions in simulation 82 LISTOFTABLES Table 1 Fragment of Signal Description table from an Opencores FPU Spec . 33 Table 2 Spec word clusters . 56 Table 3 Specification analysis results using Spec rule base . 56 Table 4 Examples of HDL represented in Knowledge Base . 59 Table 5 Example - Template RTL code fragments and their an- notations . 60 Table 6 Test results for six ITC99 Benchmarks [9]. State names and CLIPS rules fired per machine cycle. 68 Table 7 RTL Analysis results using RTL rule-base . 69 Table 8 Spec Analysis Results . 84 Table 9 RTL Analysis and Back Annotation Results . 84 ix ACRONYMS SoC System on Chip NEFCIS Neuro-fuzzy Concept based Inference System for Specification Mining UAG Undirected Acyclic Graph DAG Directed Acyclic Graph CRV Constrained Random Verification FPU Floating Point Unit CLIPS C Language Integrated Production System HDL Hardware Description Language HVL Hardware Verification Language RTL Register Transfer Level XML Extensible Markup Language DTD Document Type Definition NLP Natural Language Processing KB Knowledge Base TDML Timing Diagram Markup Language UVM Universal Verification Methodology x ACKNOWLEDGEMENTS First and foremost, I would like to thank my advisor Dr. Christos Papachris- tou for accepting me as his PhD student and guiding me in my research. He has always inspired me with his optimism and his creative ideas. The proposed methodology in this work has been conceptualized by him. His ability to quickly understand an issue and ask relevant questions around it has several times helped me to think afresh. He always encouraged me and appreciated my efforts, which kept me motivated during project implementation. Secondly, I would like to thank Prof. Frank Merat, Prof. Daniel Saab and Prof. Hong Ping Zhao, and Dr. Francis Wolff for serving on my dissertation committee, for their time and valuable comments. Especially, I would like to thank Dr. Francis Wolff, who has been closely involved in my research throughout my graduate career. My research at Case would not have been possible without the help and support of my teammates, with whom I have collaborated in my research. I am thankful to Dr. Lawrence Leinweber, Dr. Yuriy Shivanosiki, and Arun- prasath Shankar for numerous interesting project discussions. I would also like to thank my friends at CWRU especially Mike Labarbera, Aswin Krishna, Maryam Hashemian and Moussa Souare, because of whom I had wonderful time at Case. I would like to thank Rockwell Automation (Mayfield Heights) for giving me an internship opportunity and to my manager Dan Weyer, who was very sup- portive. I am also thankful to Steve Clay, with whom I interacted at Rockwell and who has increased my knowledge in IC design. I would like to thank my family for all their love and support. My parents have instilled in me the value of hardwork and patience. Their unconditional xi acknowledgements xii love for me, and pride in me keeps me motivated in life. My brothers Vishav and Rishabh, who have always been my support system. I would like to ex- press my deepest gratitude to my wife and my friend, Smriti, for her support and understanding during the past few years. Her support and encouragement made this dissertation possible. Finally, I acknowledge my daughter, Advika, and my son, Aaditya, who had to adjust with their father’s busy schedule and are my bundles of joy. knowledge-guided methodology for soft ip analysis by bhanu pratap singh ABSTRACT Demand for increasing functionality in handheld devices is driving integration of more functions (IPs) into System-on-Chip (SoC) designs. The development of such complex designs poses new challenges to the semiconductor industry in terms of productivity gaps and risks meeting quality and time-to-market goals. In SoC design, these goals are critical as rapid advances in process and product technology have shortened product life cycles with a limited feasible marketing window. SoC design teams have been employing IP reuse methodology to increase their productivity and often integrate third party IPs into their systems. Verification has developed into a major bottleneck in SoC design and has now reached crisis proportions. Verification involves building a complex test environment and the productivity gap affecting verification means that thor- ough verification of third party IPs is generally not done. In practice, there are risks involved in using a third party IP as bugs may creep in due to versioning issues, poor documentation, and mismatches between specification and RTL. As a result of this, third party IP specification and RTL must be carefully eval- uated. The current state-of-the-art lacks a methodology that captures the exper- tise of a design expert by providing knowledge representation, extraction and reuse schemes.

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