All-NDR Crossbar Logic Dmitri B

Total Page:16

File Type:pdf, Size:1020Kb

All-NDR Crossbar Logic Dmitri B All-NDR Crossbar Logic Dmitri B. Strukov, Member, IEEE, and Konstantin K. Likharev, Fellow, IEEE Abstract—We propose new crossbar circuits in which the hybrid CMOS/nanocrossbar circuits do, resulting in a logic functionality, signal restoration, and connectivity are all significant footprint overhead – see, e.g., reviews [8-10]. performed by similar bistable two-terminal devices with For that, however, the gate insulation problem should be negative differential resistance (NDR) in one of the states. The solved. Namely, in all earlier NDR logic circuits we are gate isolation challenge is met by using device’s nonlinearity aware of, Goto pair connection has been performed using together with a multiphase clocking scheme. A preliminary evaluation shows that for at least some applications, the all- some other two-terminal devices – see, e.g., Refs. 11, 12. In NDR approach enables circuit density and data throughput simple (two-wire-layer, uniform) crossbars, this is not an higher than those of hybrid CMOL FPGA ICs. option. In this paper, we propose a solution of the gate isolation problem, based on a multiphase clocking scheme and a specifically engineered device nonlinearity. I. INTRODUCTION ttempts to utilize the negative differential resistance II. ALL-NDR LOGIC CIRCUITS A (NDR) effect in two-terminal devices (based, e.g., on Figure 1a shows an example of the device capable of band-to-band tunneling in Esaki diodes [1] or on resonant performing all the functions we need. Its stack consists of tunneling through quantum wells [2]) for computing have a two back-to-back Esaki diodes (which ensure a symmetric long history. Perhaps the most serious of them were based on NDR characteristic in ON state), in series with a tunnel so-called Goto pairs [3]. Unfortunately, because of inferior barrier to suppress current at small voltages (the feature performance characteristics of NDR-based circuits (such as crucial for gate isolation, see below), and a bistable density and/or power) to those based on CMOS technology, (“memristive switch”) layer [13]. Figure 1b shows simulated the Goto pair logic did not go mainstream. However, the I-V curves based on a crude model of the stack. In particular, impending end of CMOS scaling may give NDR logics each Esaki diode was simulated using Eqs. 1a-c and specific another chance, because two-terminal NDR devices have parameters listed in Ref. 14, with current scaled down by a only one critical dimension which may be controlled by layer factor of 104 corresponding to ~25×25 nm2 germanium thickness, so that their lateral dimension reduction may be junctions. The tunnel barrier was approximated using pursued much more aggressively than that of MOSFETs. expression I = 10-15×sinh[40V] (in SI units), roughly The most plausible way to sustain high density of two- corresponding to a 6-nm TiO2 tunnel barrier of the same terminal devices is to build crossbars incorporating them at area. For simplicity, the ON resistance of the switch was each crosspoint. The regular topology of crossbars allows assumed to be much smaller, and its OFF resistance much their fabrication using such advanced patterning technologies larger than the resistance scale of the rest of the stack. (For as nanoimprint [4, 5], interference lithography [6], and scaling to sub-10-nm lateral dimensions, other means of block-copolymer lithography [7] which may be scaled down combining the NDR effect with bistability, such as self- beyond the 10-nm frontier without using prohibitively assembled molecular monolayers with single-electron expensive equipment. However, in order to use this tunneling [15], may be more realistic.) opportunity, effective ways to form arbitrary logic circuits Figure 2 shows results of simulation of the transfer curve from the regular crossbar fabric have to be found. (Vclk vs. Vout) for a Goto pair, based on two NDR devices A possible way here is to use bistable crosspoint devices shown in Fig. 1a-b, with no input current injected into its which could be switched between their low-current (OFF) central node, voltage-biased with a symmetric clock signal. state and high-current (ON) state which would feature an Similarly to the conventional case [3, 11, 12], two stable NDR branch. Such circuits can perform signal restoration, states of the Goto pair correspond to either high (Vout = V0 , and thus avoid using for that purpose a CMOS subsystem or in our case V0 ≈ 0.5 V) or low (Vout = -V0) output voltage. other three-terminal devices - as all previously proposed Figure 3a shows the transfer curve for a buffer gate whose symmetry is broken during the clock ramp-up. More general, reconfigurable threshold gates [16] with the Boolean th Manuscript received April 18 , 2011. This work was supported by the function National Science Foundation grants CCF-1017579 and CCF-0829947. D.B. Strukov is with the Electrical and Computer Engineering Department, University of California at Santa Barbara, Santa Barbara, CA, y = V0×sgn[Σixi – Θ] (1) 93106 USA (phone: 805-893-2971; fax: 805-893-3262; e-mail: strukov@ ece.ucsb.edu). (where x , y = {-V , V } are digital inputs and output, K.K. Likharev is with the Physics and Astronomy Department, Stony i 0 0 Brook University, Stony Brook, NY 11794-3800 USA (phone: 631-632- respectively, and Θ is switching threshold) may be also 8159; fax: 631-632-4976; e-mail: [email protected]). readily implemented by feeding the Goto pair with several computation is performed in a systolic (a) (b) ON state top electrode fashion, with the direction determined by tunnel barrier 0.55 the clocking sequence, similar to n-type OFF state back- ) p-type to-back mA 0 reversible parametron-like logic circuits μA ( -4 Esaki I I 0.00110 n-type 105 [17-19] (some of them referred to as diodes -87 -0.55 10109 memristive layer “on” “off” 10 “quantum-dot cellular automata”, QCA), 10-10 state 0.1 0.3 1 bottom electrode 0.1 0.3 1 and adiabatic CMOS circuits [20]. -22 -11 00 11 2 The gate isolation is quite sufficient due V(Volts)Volts to the high nonlinearity of the NDR Fig. 1. Resistive switching devices (also known as “memristive switch” or “latching switch”) devices at low voltages. For example, for with symmetric negative differential characteristics: (a) device stack with the NDR effect due the Goto pair being evaluated, the current to back-to-back Esaki diodes and energy diagram (schematically) and (b) its simulated I-V characteristics. The inset of panel (b) shows the same I-V curve in a log-log scale. from its output pair is negligible (below 100 pA even for a fan-out of 10) given the maximum bias of V = 0.5 V applied over input currents. For each gate, Θ is set by properly biasing 0 one NDR device connected in series with several other NDR Goto pair, i.e. by connecting its central node, with an devices (Fig. 4a). In addition, if necessary, the reference additional NDR device, to corresponding bias voltages V or up Goto pair can be reinforced with more NDR devices to V . For example, Fig. 3b shows an example of a 2-input down minimize the effect of the output current on its state – see gate with a switching thresholds of Θ = - V , i.e. 2-input OR 0 gray lines in Fig. 4a. In this case each evaluation stage gate. Figs. 3c and d show 3-input gates with Θ = -2V and Θ 0 should be followed by an reinforcement phase (in Fig. 4a, = 0, correspondingly, and results of their numerical provided by clock V ). simulations. RE Figure 4 shows the idea of multiphase clocking used for III. DISCUSSION gate isolation. There are four distinct phases of each clock signal. Every clock voltage is set to ±VDD/2 during one of The proposed all-NDR logic scheme maps naturally to phases (REF). During this phase, outputs of the Goto pairs hybrid CMOL IC circuits ([9, 10], Fig. 5), with CMOS driven by this clock are either high or low (either +V0 or - circuitry used only for configuration, clock distribution, and I/O purposes. For example, Fig. 6 shows a full adder V0) and serve as references for the next, “evaluation” pairs whose clock voltage is being ramped up from zero to VDD/2 implementation using an all-NDR crossbar circuit. (Note the (Fig. 4b). The Goto pairs driven by the evaluation clock are dual-rail implementation which is necessity due to the lack of forced to calculate a certain Boolean function of its inputs. the signal inversion by a Goto pair.) With such During the next two phases, the clock voltage is set to zero, implementation, the full adder comprises two logic levels disabling the corresponding Goto pairs. The resulting and total of 8 gates (i.e. 8 CMOS cells in CMOL circuits). (a) 6 (b) 0.4 V = 0 V 2 CLK A 0 0 VCLK G 2 0.40.4 -0.4 4 I U 6 6 2 1 0 1 I (V -V 2) 0.4 V = 0.55 V D OUT CLK 4 CLK V OUT 2 0.2 B 0.2 0 I 0 D D 2 -V IU(VCLK -VOUT) CLK ) -0.4 4 A I A B E μ 6 0.0 ( 6 0.0 ( Volts) I E 0.4 VCLK = 0.67 V 4 C D OUT 2 C V 0 VCLK 0 -0.20.2 2 -0.4 4 V t 6 DD 6 0.4 V = 1.05 V 4 CLK -0.4 0.4 F I G 2 F 0 0 2 -0.44 0.00.0 0.2 0.2 0.4 0.6 0.6 0.80.8 1.0 1.0 6 V (Volts) -22 -11 0 0 1 2 CLK V (Volts) Fig.
Recommended publications
  • Magnonic Logic Circuits
    IOP PUBLISHING JOURNAL OF PHYSICS D: APPLIED PHYSICS J. Phys. D: Appl. Phys. 43 (2010) 264005 (10pp) doi:10.1088/0022-3727/43/26/264005 Magnonic logic circuits Alexander Khitun, Mingqiang Bao and Kang L Wang Device Research Laboratory, Electrical Engineering Department, Focus Center on Functional Engineered Nano Architectonics (FENA), Western Institute of Nanoelectronics (WIN), University of California at Los Angeles, Los Angeles, California, 90095-1594, USA Received 23 November 2009, in final form 31 March 2010 Published 17 June 2010 Online at stacks.iop.org/JPhysD/43/264005 Abstract We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed. 1. Introduction interest in spin waves as a potential candidate for information transmission. The situation has changed drastically as the There is an immense practical need for novel logic devices characteristic distance between the devices on the chip entered capable of overcoming the constraints inherent to conventional the deep-submicrometre range.
    [Show full text]
  • ERSFQ 8-Bit Parallel Arithmetic Logic Unit
    1 ERSFQ 8-bit Parallel Arithmetic Logic Unit A. F. Kirichenko, I. V. Vernik, M. Y. Kamkar, J. Walter, M. Miller, L. R. Albu, and O. A. Mukhanov Abstract— We have designed and tested a parallel 8-bit ERSFQ To date, the reported superconductor ALU designs were arithmetic logic unit (ALU). The ALU design employs wave- implemented using RSFQ logic following bit-serial, bit-slice, pipelined instruction execution and features modular bit-slice ar- chitecture that is easily extendable to any number of bits and and parallel architectures. adaptable to current recycling. A carry signal synchronized with The bit-serial designs have the lowest complexity; however, an asynchronous instruction propagation provides the wave- their latencies increase linearly with the operand lengths, hard- pipeline operation of the ALU. The ALU instruction set consists of ly making them competitive for implementation in 32-/64-bit 14 arithmetical and logical instructions. It has been designed and processors [17], [18]. Bit-serial ALUs were used in 8-bit simulated for operation up to a 10 GHz clock rate at the 10-kA/cm2 fabrication process. The ALU is embedded into a shift-register- RSFQ microprocessors [19]-[24], in which an 8 times faster based high-frequency testbed with on-chip clock generator to allow internal clock is still feasible. As an example, an 80 GHz bit- for comprehensive high frequency testing for all possible operands. serial ALU was reported in [25]. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has In order to alleviate the high-clock requirements and long 2 been fabricated with MIT Lincoln Lab’s 10-kA/cm SFQ5ee fabri- latencies of bit-serial design while keeping moderate hardware cation process featuring eight Nb wiring layers and a high-kinetic inductance layer needed for ERSFQ technology.
    [Show full text]
  • Japan's ERATO and PRESTO Basic Research Programs
    Japanese Technology Evaluation Center JTEC JTEC Panel Report on Japan’s ERATO and PRESTO Basic Research Programs George Gamota (Panel Chair) William E. Bentley Rita R. Colwell Paul J. Herer David Kahaner Tamami Kusuda Jay Lee John M. Rowell Leo Young September 1996 International Technology Research Institute R.D. Shelton, Director Geoffrey M. Holdridge, WTEC Director Loyola College in Maryland 4501 North Charles Street Baltimore, Maryland 21210-2699 JTEC PANEL ON JAPAN’S ERATO AND PRESTO PROGRAMS Sponsored by the National Science Foundation and the Department of Commerce of the United States Government George Gamota (Panel Chair) David K. Kahaner Science & Technology Management Associates Asian Technology Information Program 17 Solomon Pierce Road 6 15 21 Roppongi, Harks Roppongi Bldg. 1F Lexington, MA 02173 Minato ku, Tokyo 106 Japan William E. Bentley Tamami Kusuda University of Maryland 5000 Battery Ln., Apt. #506 Dept. of Chemical Engineering Bethesda, MD 20814 College Park, MD 20742 Jay Lee Rita R. Colwell National Science Foundation University of Maryland 4201 Wilson Blvd., Rm. 585 Biotechnology Institute Arlington, VA 22230 College Park, MD 20740 John Rowell Paul J. Herer 102 Exeter Dr. National Science Foundation Berkeley Heights, NJ 07922 4201 Wilson Blvd., Rm. 505 Arlington, VA 22230 Leo Young 6407 Maiden Lane Bethesda, MD 20817 INTERNATIONAL TECHNOLOGY RESEARCH INSTITUTE WTEC PROGRAM The World Technology Evaluation Center (WTEC) at Loyola College (previously known as the Japanese Technology Evaluation Center, JTEC) provides assessments of foreign research and development in selected technologies under a cooperative agreement with the National Science Foundation (NSF). Loyola's International Technology Research Institute (ITRI), R.D.
    [Show full text]
  • A Stochastic-Computing Based Deep Learning Framework Using
    A Stochastic-Computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron Superconducting Technology Ruizhe Cai Olivia Chen Ning Liu Ao Ren Yokohama National University Caiwen Ding Northeastern University Japan Northeastern University USA [email protected] USA {cai.ruiz,ren.ao}@husky.neu.edu {liu.ning,ding.ca}@husky.neu.edu Xuehai Qian Jie Han Wenhui Luo University of Southern California University of Alberta Yokohama National University USA Canada Japan [email protected] [email protected] [email protected] Nobuyuki Yoshikawa Yanzhi Wang Yokohama National University Northeastern University Japan USA [email protected] [email protected] ABSTRACT increases the difficulty to avoid RAW hazards; the second is The Adiabatic Quantum-Flux-Parametron (AQFP) supercon- the unique opportunity of true random number generation ducting technology has been recently developed, which achieves (RNG) using a single AQFP buffer, far more efficient than the highest energy efficiency among superconducting logic RNG in CMOS. We point out that these two characteristics families, potentially 104-105 gain compared with state-of-the- make AQFP especially compatible with the stochastic com- art CMOS. In 2016, the successful fabrication and testing of puting (SC) technique, which uses a time-independent bit AQFP-based circuits with the scale of 83,000 JJs have demon- sequence for value representation, and is compatible with strated the scalability and potential of implementing large- the deep pipelining nature. Further, the application of SC scale systems using AQFP. As a result, it will be promising has been investigated in DNNs in prior work, and the suit- for AQFP in high-performance computing and deep space ability has been illustrated as SC is more compatible with applications, with Deep Neural Network (DNN) inference approximate computations.
    [Show full text]
  • Nonconventional Computer Arithmetic Circuits, Systems and Applications Leonel Sousa, Senior Member, IEEE
    1 Nonconventional Computer Arithmetic Circuits, Systems and Applications Leonel Sousa, Senior Member, IEEE Abstract—Arithmetic plays a major role in a computer’s basic levels and leads to high power consumption. Hence, performance and efficiency. Building new computing platforms the research on unconventional number systems is of the supported by the traditional binary arithmetic and silicon-based utmost interest to explore parallelism and take advantage of technologies to meet the requirements of today’s applications is becoming increasingly more challenging, regardless whether we the characteristics of emerging technologies to improve both consider embedded devices or high-performance computers. As a the performance and the energy efficiency of computational result, a significant amount of research effort has been devoted to systems. Moreover, by avoiding the dependencies of binary the study of nonconventional number systems to investigate more systems, nonconventional number systems can also support efficient arithmetic circuits and improved computer technologies the design of reliable computing systems using the newest to facilitate the development of computational units that can meet the requirements of applications in emergent domains. available technologies, such as nanotechnologies. This paper presents an overview of the state of the art in non- conventional computer arithmetic. Several different alternative computing models and emerging technologies are analyzed, such A. Motivation as nanotechnologies, superconductor devices, and biological- and quantum-based computing, and their applications to multiple The Complementary Metal-Oxide Semiconductor (CMOS) domains are discussed. A comprehensive approach is followed transistor was invented over fifty years ago and has played in a survey of the logarithmic and residue number systems, a key role in the development of modern electronic devices the hyperdimensional and stochastic computation models, and and all that it has enabled.
    [Show full text]
  • Computer Aided Systems Theory – EUROCAST 2019
    Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya B Radomir S. Stankovi´c1( ), Tsutomu Sasao2, Jaakko T. Astola3, and Akihiko Yamada4 1 Mathematical Institute of SASA, Belgrade, Serbia [email protected] 2 Department of Computer Science, Meiji University, Kawasaki, Kanagawa 214-8571, Japan 3 Department of Signal Processing, Tampere University of Technology, Tampere, Finland 4 Computer Systems and Media Laboratory, Tokyo, Japan Abstract. This paper presents some less known details about the work of Yasuo Komamiya in development of the first relay computers using the theory of computing networks that is based on the former work of Oohashi Kan-ichi and Mochiori Goto at the Electrotechnical Laboratory (ETL) of Agency of Industrial Science and Technology, Tokyo, Japan. The work at ETL in the same direction was performed under guidance of Mochinori Goto. Keywords: Digital computers · Relay-based computers · Parametron computers · Transistorised computers · History · Arithmetic circuits 1 Introduction In the first half of the 20th century, many useful algorithms were developed to solve various problems in different areas of human activity. However, most of them require intensive computations, due to which their applications, espe- cially wide applications, have been suppressed by the lack of the correspond- ing computing devices. Even before that, already in late thirties, it was clear that discrete and digital devices are more appropriate for such applications that require complex computations. Therefore, in fifties of the 20th century, the work towards development of digital computers was a central subject of research at many important national level institutions. This research was performed equally in all technology leading countries all over the world, notably USA, Europe, and Japan.
    [Show full text]
  • Theory, Synthesis, and Application of Adiabatic and Reversible Logic
    University of South Florida Scholar Commons Graduate Theses and Dissertations Graduate School 11-23-2013 Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications Matthew Arthur Morrison University of South Florida, [email protected] Follow this and additional works at: https://scholarcommons.usf.edu/etd Part of the Computer Engineering Commons Scholar Commons Citation Morrison, Matthew Arthur, "Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications" (2013). Graduate Theses and Dissertations. https://scholarcommons.usf.edu/etd/5082 This Dissertation is brought to you for free and open access by the Graduate School at Scholar Commons. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Scholar Commons. For more information, please contact [email protected]. Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications by Matthew A. Morrison A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Computer Science and Engineering College of Engineering University of South Florida Major Professor: Nagarajan Ranganathan, Ph.D. Sanjukta Bhanja, Ph.D. Srinivas Katkoori, Ph.D. Jay Ligatti, Ph.D. Kandethody Ramachandran, Ph.D. Hao Zheng, Ph.D. Date of Approval: November 22, 2013 Keywords: Charge Based Computing, DPA Attacks, Encryption, Memory, Power Copyright © 2014, Matthew A. Morrison DEDICATION To my parents, Alfred and Kathleen Morrison, and to my grandparents, Arthur and Betty Kempf, and Alfred and Dorothy Morrison, for making all the opportunities I have possible. ACKNOWLEDGMENTS I would like to thank my advisor, Dr.
    [Show full text]
  • Some Key Issues in Microelectronic Packaging
    G. V. CLATTERBAUGH, P. VICHOT, AND H. K. CHARLES, JR. Some Key Issues in Microelectronic Packaging Guy V. Clatterbaugh, Paul Vichot, and Harry K. Charles, Jr. Military and space electronics are tending toward increased system perfor- mance, i.e., higher speed, higher circuit density, and higher functionality. Recent reductions in government spending on space and military hardware have also made cost reduction a key consideration. As electronics approach physical size and performance limits, practical considerations such as wireability, thermal management, electromagnetic compatibility, and system reliability become dominant issues in system design. Resolving such issues requires the use of sophisticated analysis and computational methods. (Keywords: Electronic packaging, Multiconductor transmission line analysis, Printed circuit board thermal analysis, Wireability.) INTRODUCTION In recent years, the electronics industry has discov- functionality and performance while reducing volume ered that the major economic advances made in high- and weight. performance electronic circuitry have come with in- The quest to achieve better performance (higher creased integration. The industry is rapidly converging speed and integration) has placed pressure on manu- toward true wafer-scale integration, i.e., toward an facturers and has forced integrated circuits (ICs) closer entire system fabricated on one silicon substrate. Every together. High-speed computer systems require that 5 years or so, we see wafer foundries processing larger the central processing unit and the memory and con- silicon wafers with smaller line geometries. Today, 12- trollers be proximal to minimize interconnection de- in. wafers are being processed with 0.35-mm lines. By lays. The increased functionality of these chips has the year 2010, 16-in.
    [Show full text]
  • Superconducting Nanowire Electronics for Alternative Computing
    Superconducting nanowire electronics for alternative computing by Emily Toomey Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY May 2020 © Massachusetts Institute of Technology 2020. All rights reserved. Author................................................................ Department of Electrical Engineering and Computer Science May 14, 2020 Certified by. Karl K. Berggren Professor of Electrical Engineering Thesis Supervisor Accepted by........................................................... Leslie A. Kolodziejski Professor of Electrical Engineering and Computer Science Chair, Department Committee on Graduate Students 2 Superconducting nanowire electronics for alternative computing by Emily Toomey Submitted to the Department of Electrical Engineering and Computer Science on May 14, 2020, in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering Abstract With traditional computing systems struggling to meet the demands of modern tech- nology, new approaches to both hardware and architecture are becoming increasingly critical. In this work, I develop the foundation of a power-efficient alternative com- puting system using superconducting nanowires. Although traditionally operated as single photon detectors, superconducting nanowires host a suite of attractive charac- teristics that have recently inspired their
    [Show full text]
  • Adiabatic Quantum-Flux-Parametron with Delay-Line Clocking: Logic Gate Demonstration and Phase Skipping Operation
    Adiabatic quantum-flux-parametron with delay-line clocking: logic gate demonstration and phase skipping operation Taiki Yamae,1,2 Naoki Takeuchi,3,4,* and Nobuyuki Yoshikawa1,4 1 Department of Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501, Japan 2 Research Fellow of Japan Society for the Promotion of Science, 5-3-1 Kojimachi, Chiyoda, Tokyo 102-0083, Japan 3 Research Center for Emerging Computing Technologies, National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba 305-8568, Japan 4 Institute of Advanced Sciences, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501, Japan * [email protected] Abstract. Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. 1 AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments.
    [Show full text]
  • Single-Electron Logic and Memory Devices
    INT. J. ELECTRONICS, 1999, VOL. 86, NO. 5, 511± 547 Single-electron logic and memory devices ALEXANDER N. KOROTKOV² ³ Single-electronics is believed to be the leading candidate for future digital electronics which will be able to operate at 10 nm size scale and below. How- ever, the problems of integrated single-electronics are quite serious whereby the future prospects are still uncertain. In this paper we discuss the operation principles and required parameters of several proposed families of single-electron logic, including the logic based on single-electron transistors, wireless single-electron logic and single-electron parametron. We also brie¯ y discuss the single-electron memory which is easier to implement than logic and, hence, is more important from the practical point of view. As an example, we consider the background- charge-insensitive hybrid SET/FET memory. 1. Introduction More than 10 years has past since the beginning of the active theoretical and experimental study of correlated single-electron tunnelling (for reviews see, e.g. [1± 6]). This is already a su ciently long period of time to ask a question if the applied single-electronics is only a dream or we can expect the creation of really useful single- electron devices in the not too distant future. However, there is still no simple answer to this question. On the one hand, the practical value of several non-integrated application s have been already proven. On the other hand, for the integrated digital single-electron devices which are the most important potential application of single- electronics, the prospects are still not so clear.
    [Show full text]
  • Design Tools for Oscillator-Based Computing Systems
    Design Tools for Oscillator-based Computing Systems Tianshi Wang‡ and Jaijeet Roychowdhury ∗Department of Electrical Engineering and Computer Science, The University of California, Berkeley, CA, USA ‡Contact author. Email: [email protected] ABSTRACT ers based on Parametrons were once popular in Japan but quickly gave way to transistor-based computers with level-based logic encod- Recently, general-purpose computing schemes have been proposed ing. Later versions of Goto’s Parametron employed superconducting that use phase relationships to represent Boolean logic levels and em- Josephson junctions to improve speed and energy consumption; how- ploy self-sustaining nonlinear oscillators as latches and registers. Such ever, they still remained unsuitable for large-scale integration and phase-based systems have superior noise immunity relative to tradi- have been limited in application. tional level-encoded logic, hence are of interest for next-generation computing using nanodevices. However, the design of such systems Recently, the phase logic idea has been revisited with new mecha- poses special challenges for existing tools. We present a suite of tech- nisms and schemes proposed in [18, 15]. The new phase logic frame- niques and tools that provide designers with efficient simulation and work is termed PHLOGON: PHase-based LOGic using Oscillatory convenient visualization facilities at all stages of phase logic system Nano-systems. Instead of passive resonant circuits driven by AC design. We demonstrate our tools through a case study of the design power, PHLOGON uses DC-powered self-sustaining nonlinear oscilla- of a phase logic finite state machine (FSM). We build this FSM and tors as phase logic components.
    [Show full text]