All-NDR Crossbar Logic Dmitri B. Strukov, Member, IEEE, and Konstantin K. Likharev, Fellow, IEEE Abstract—We propose new crossbar circuits in which the hybrid CMOS/nanocrossbar circuits do, resulting in a logic functionality, signal restoration, and connectivity are all significant footprint overhead – see, e.g., reviews [8-10]. performed by similar bistable two-terminal devices with For that, however, the gate insulation problem should be negative differential resistance (NDR) in one of the states. The solved. Namely, in all earlier NDR logic circuits we are gate isolation challenge is met by using device’s nonlinearity aware of, Goto pair connection has been performed using together with a multiphase clocking scheme. A preliminary evaluation shows that for at least some applications, the all- some other two-terminal devices – see, e.g., Refs. 11, 12. In NDR approach enables circuit density and data throughput simple (two-wire-layer, uniform) crossbars, this is not an higher than those of hybrid CMOL FPGA ICs. option. In this paper, we propose a solution of the gate isolation problem, based on a multiphase clocking scheme and a specifically engineered device nonlinearity. I. INTRODUCTION ttempts to utilize the negative differential resistance II. ALL-NDR LOGIC CIRCUITS A (NDR) effect in two-terminal devices (based, e.g., on Figure 1a shows an example of the device capable of band-to-band tunneling in Esaki diodes [1] or on resonant performing all the functions we need. Its stack consists of tunneling through quantum wells [2]) for computing have a two back-to-back Esaki diodes (which ensure a symmetric long history. Perhaps the most serious of them were based on NDR characteristic in ON state), in series with a tunnel so-called Goto pairs [3]. Unfortunately, because of inferior barrier to suppress current at small voltages (the feature performance characteristics of NDR-based circuits (such as crucial for gate isolation, see below), and a bistable density and/or power) to those based on CMOS technology, (“memristive switch”) layer [13]. Figure 1b shows simulated the Goto pair logic did not go mainstream. However, the I-V curves based on a crude model of the stack. In particular, impending end of CMOS scaling may give NDR logics each Esaki diode was simulated using Eqs. 1a-c and specific another chance, because two-terminal NDR devices have parameters listed in Ref. 14, with current scaled down by a only one critical dimension which may be controlled by layer factor of 104 corresponding to ~25×25 nm2 germanium thickness, so that their lateral dimension reduction may be junctions. The tunnel barrier was approximated using pursued much more aggressively than that of MOSFETs. expression I = 10-15×sinh[40V] (in SI units), roughly The most plausible way to sustain high density of two- corresponding to a 6-nm TiO2 tunnel barrier of the same terminal devices is to build crossbars incorporating them at area. For simplicity, the ON resistance of the switch was each crosspoint. The regular topology of crossbars allows assumed to be much smaller, and its OFF resistance much their fabrication using such advanced patterning technologies larger than the resistance scale of the rest of the stack. (For as nanoimprint [4, 5], interference lithography [6], and scaling to sub-10-nm lateral dimensions, other means of block-copolymer lithography [7] which may be scaled down combining the NDR effect with bistability, such as self- beyond the 10-nm frontier without using prohibitively assembled molecular monolayers with single-electron expensive equipment. However, in order to use this tunneling [15], may be more realistic.) opportunity, effective ways to form arbitrary logic circuits Figure 2 shows results of simulation of the transfer curve from the regular crossbar fabric have to be found. (Vclk vs. Vout) for a Goto pair, based on two NDR devices A possible way here is to use bistable crosspoint devices shown in Fig. 1a-b, with no input current injected into its which could be switched between their low-current (OFF) central node, voltage-biased with a symmetric clock signal. state and high-current (ON) state which would feature an Similarly to the conventional case [3, 11, 12], two stable NDR branch. Such circuits can perform signal restoration, states of the Goto pair correspond to either high (Vout = V0 , and thus avoid using for that purpose a CMOS subsystem or in our case V0 ≈ 0.5 V) or low (Vout = -V0) output voltage. other three-terminal devices - as all previously proposed Figure 3a shows the transfer curve for a buffer gate whose symmetry is broken during the clock ramp-up. More general, reconfigurable threshold gates [16] with the Boolean th Manuscript received April 18 , 2011. This work was supported by the function National Science Foundation grants CCF-1017579 and CCF-0829947. D.B. Strukov is with the Electrical and Computer Engineering Department, University of California at Santa Barbara, Santa Barbara, CA, y = V0×sgn[Σixi – Θ] (1) 93106 USA (phone: 805-893-2971; fax: 805-893-3262; e-mail: strukov@ ece.ucsb.edu). (where x , y = {-V , V } are digital inputs and output, K.K. Likharev is with the Physics and Astronomy Department, Stony i 0 0 Brook University, Stony Brook, NY 11794-3800 USA (phone: 631-632- respectively, and Θ is switching threshold) may be also 8159; fax: 631-632-4976; e-mail: [email protected]). readily implemented by feeding the Goto pair with several computation is performed in a systolic (a) (b) ON state top electrode fashion, with the direction determined by tunnel barrier 0.55 the clocking sequence, similar to n-type OFF state back- ) p-type to-back mA 0 reversible parametron-like logic circuits μA ( -4 Esaki I I 0.00110 n-type 105 [17-19] (some of them referred to as diodes -87 -0.55 10109 memristive layer “on” “off” 10 “quantum-dot cellular automata”, QCA), 10-10 state 0.1 0.3 1 bottom electrode 0.1 0.3 1 and adiabatic CMOS circuits [20]. -22 -11 00 11 2 The gate isolation is quite sufficient due V(Volts)Volts to the high nonlinearity of the NDR Fig. 1. Resistive switching devices (also known as “memristive switch” or “latching switch”) devices at low voltages. For example, for with symmetric negative differential characteristics: (a) device stack with the NDR effect due the Goto pair being evaluated, the current to back-to-back Esaki diodes and energy diagram (schematically) and (b) its simulated I-V characteristics. The inset of panel (b) shows the same I-V curve in a log-log scale. from its output pair is negligible (below 100 pA even for a fan-out of 10) given the maximum bias of V = 0.5 V applied over input currents. For each gate, Θ is set by properly biasing 0 one NDR device connected in series with several other NDR Goto pair, i.e. by connecting its central node, with an devices (Fig. 4a). In addition, if necessary, the reference additional NDR device, to corresponding bias voltages V or up Goto pair can be reinforced with more NDR devices to V . For example, Fig. 3b shows an example of a 2-input down minimize the effect of the output current on its state – see gate with a switching thresholds of Θ = - V , i.e. 2-input OR 0 gray lines in Fig. 4a. In this case each evaluation stage gate. Figs. 3c and d show 3-input gates with Θ = -2V and Θ 0 should be followed by an reinforcement phase (in Fig. 4a, = 0, correspondingly, and results of their numerical provided by clock V ). simulations. RE Figure 4 shows the idea of multiphase clocking used for III. DISCUSSION gate isolation. There are four distinct phases of each clock signal. Every clock voltage is set to ±VDD/2 during one of The proposed all-NDR logic scheme maps naturally to phases (REF). During this phase, outputs of the Goto pairs hybrid CMOL IC circuits ([9, 10], Fig. 5), with CMOS driven by this clock are either high or low (either +V0 or - circuitry used only for configuration, clock distribution, and I/O purposes. For example, Fig. 6 shows a full adder V0) and serve as references for the next, “evaluation” pairs whose clock voltage is being ramped up from zero to VDD/2 implementation using an all-NDR crossbar circuit. (Note the (Fig. 4b). The Goto pairs driven by the evaluation clock are dual-rail implementation which is necessity due to the lack of forced to calculate a certain Boolean function of its inputs. the signal inversion by a Goto pair.) With such During the next two phases, the clock voltage is set to zero, implementation, the full adder comprises two logic levels disabling the corresponding Goto pairs. The resulting and total of 8 gates (i.e. 8 CMOS cells in CMOL circuits). (a) 6 (b) 0.4 V = 0 V 2 CLK A 0 0 VCLK G 2 0.40.4 -0.4 4 I U 6 6 2 1 0 1 I (V -V 2) 0.4 V = 0.55 V D OUT CLK 4 CLK V OUT 2 0.2 B 0.2 0 I 0 D D 2 -V IU(VCLK -VOUT) CLK ) -0.4 4 A I A B E μ 6 0.0 ( 6 0.0 ( Volts) I E 0.4 VCLK = 0.67 V 4 C D OUT 2 C V 0 VCLK 0 -0.20.2 2 -0.4 4 V t 6 DD 6 0.4 V = 1.05 V 4 CLK -0.4 0.4 F I G 2 F 0 0 2 -0.44 0.00.0 0.2 0.2 0.4 0.6 0.6 0.80.8 1.0 1.0 6 V (Volts) -22 -11 0 0 1 2 CLK V (Volts) Fig.