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Some Key Issues in Microelectronic Packaging G. V. CLATTERBAUGH, P. VICHOT, AND H. K. CHARLES, JR. Some Key Issues in Microelectronic Packaging Guy V. Clatterbaugh, Paul Vichot, and Harry K. Charles, Jr. Military and space electronics are tending toward increased system perfor- mance, i.e., higher speed, higher circuit density, and higher functionality. Recent reductions in government spending on space and military hardware have also made cost reduction a key consideration. As electronics approach physical size and performance limits, practical considerations such as wireability, thermal management, electromagnetic compatibility, and system reliability become dominant issues in system design. Resolving such issues requires the use of sophisticated analysis and computational methods. (Keywords: Electronic packaging, Multiconductor transmission line analysis, Printed circuit board thermal analysis, Wireability.) INTRODUCTION In recent years, the electronics industry has discov- functionality and performance while reducing volume ered that the major economic advances made in high- and weight. performance electronic circuitry have come with in- The quest to achieve better performance (higher creased integration. The industry is rapidly converging speed and integration) has placed pressure on manu- toward true wafer-scale integration, i.e., toward an facturers and has forced integrated circuits (ICs) closer entire system fabricated on one silicon substrate. Every together. High-speed computer systems require that 5 years or so, we see wafer foundries processing larger the central processing unit and the memory and con- silicon wafers with smaller line geometries. Today, 12- trollers be proximal to minimize interconnection de- in. wafers are being processed with 0.35-mm lines. By lays. The increased functionality of these chips has the year 2010, 16-in. wafers and 0.10-mm lines will increased the number of inputs and outputs (I/Os). likely be the standard. This, in turn, has imposed routing demands that have Even with the increased ability to build larger chips changed the way we think about fabricating printed with greater functionality, very few systems function as wiring boards (PWBs) and building IC packages. The a single chip. Instead, the trend is to take advantage higher speeds and higher densities also create thermal of recent technology advances in electronic packaging and thermal stress problems that challenge the limits to pack chips side by side, sometimes even in three- of today’s microelectronic materials and manufactur- dimensional stacks, to achieve still higher levels of ing methods. 34 JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) SOME KEY ISSUES IN MICROELECTRONIC PACKAGING In this era of dwindling federal budgets, cost is a material integrity, and protecting the circuit from en- major concern. Previously, high performance and high vironmental hazards. reliability were demanded of military and space elec- Almost all of the methods for packaging ICs include tronic systems; cost was often not an issue. However, the use of a PWB with connectors that provide the the military now mandates as much use of commercial real-world I/Os to an electronic circuit. The traditional off-the-shelf hardware as possible, and the watchword packaging approach involves the use of single packag- from NASA is “smaller, lighter, and cheaper.” So while es. The chief advantage of single-chip packages is the the emphasis on cost has increased, the emphasis on ability to fully test the IC before interconnecting it to performance and reliability has remained high. With the underlying substrate. Such packaged devices are this heightened demand for more complexity, cost- either through-hole mounted or surface mounted to reduction opportunities are being strained. the PWB. The primary objective of microelectronic packaging Surface-mounted components do not require via is to design an electronic system that will satisfy the holes to go through the entire board. Instead, packages requirements for a particular application at a reason- and other surface-mounted components can be sol- able cost. Because of the many options available to dered to both sides of the PWB, thereby increasing interconnect and house an electronic system, the circuit density. This approach is called surface-mount choice of a packaging technology for a given applica- technology (SMT). The addition of area-array–style tion is not always straightforward. Selection criteria packages such as ball-grid arrays (BGAs) and chip- may include one or more technology drivers: scale packages (CSPs) is making SMT competitive with the highest-density packaging technologies, al- • Wireability though the reliability of some area-array packages is • Yield still questionable. • Cost A newer packaging technology involves the attach- • Heat transfer characteristics ment of more than one device onto a high-density • Electromagnetic performance interconnection substrate, which is then mounted in • Mechanical toughness a large package. This provides both I/O pins and en- • Reliability vironmental protection. This so-called multichip mod- These fundamental design considerations affect ule (MCM) technology is further characterized by the speed, functionality, junction temperatures, volume, substrate technologies used to interconnect the at- and weight. The primary goal is to select the most cost- tached ICs. effective yet reliable interconnection technology, MCM-D represents thin film “deposited” metal and which requires a quantification of the technology dielectric multilayers. MCM-D substrates have the drivers. The resolution of these key design issues often highest wiring densities of all MCM technologies depends on the use of sophisticated analysis methods. owing to the sophisticated semiconductor processing This article discusses some of the quantitative tools equipment used to manufacture them. MCM-C refers developed and used at APL to assist the electronic to multilayered “ceramic” substrates, fired from stacked packaging engineer in selecting reliable, cost-effective alternating layers of screened metal inks and unfired solutions for packaging high-performance electronic ceramic sheets. This technology yields a moderately systems. After briefly examining various packaging dense wiring capacity. MCM-L refers to multilayer options, we will detail five of the seven selection cri- substrates made from stacked, metallized PWB “lami- teria already noted: wireability, yield, cost, heat trans- nates,” which are individually patterned and then lam- fer, and electromagnetic performance. inated. Once considered a low-density interconnect technology, MCM-L is rapidly approaching the density MICROELECTRONIC PACKAGING of MCM-C and MCM-D technologies. Direct chip attach (DCA) or chip-on-board OPTIONS (COB) technology entails mounting the ICs directly Microelectronic packaging is a branch of engineer- to the PWB. A plastic encapsulant, which is “globbed” ing that deals with the design of methods for the fab- over the bare IC and then cured, provides environmen- rication and manufacture of interconnected miniature tal protection. ICs can be interconnected to the sub- electronic systems (e.g., ICs and discrete and integrat- strate using either flip-chip, tape-automated bonding, ed passive devices) and the reliability of those systems. or wire bonding methods. DCA technology is partic- Specifically, microelectronic packaging involves rout- ularly economical for systems that are limited to 10 or ing signals while maintaining signal integrity, dis- fewer ICs, since larger numbers of chips can affect tributing ground and power to ICs, dispersing dissipat- system yield and DCA assemblies can be difficult to ed thermal energy while maintaining structural and rework. JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 35 G. V. CLATTERBAUGH, P. VICHOT, AND H. K. CHARLES, JR. An advantage common to both the DCA and MCM packaging options is the elimination of the IC package interconnection level, which allows closer proximity (shorter propagation delays) and reduced lead inductance. The pri- mary disadvantage with both meth- Figure 1. High-density surface-mount assembly with multichip carrier modules. ods is the difficulty in purchasing fully tested ICs (the “known good die” problem; see the section enti- tled Yield). Other disadvantages of DCA and MCM- available for interconnection. Wiring demand is relat- L technologies include poor thermal management ed to wiring capacity through the equation owing to the low thermal conductivity of PWB lam- inates and a poor coefficient of thermal expansion D = «C , (1) match between the die and the substrate. Solving the last problem usually requires an interposer substrate such as molybdenum for wire bonded die and an where « is wiring efficiency. Typically, wiring efficiency underfill epoxy for flip-chip die. is near 50%, since a substrate cannot be wired using The multichip carrier module (MCCM, Fig. 1) 100% of its available capacity. attempts to marry all the positive aspects of DCA with Wiring capacity, which is a function of the minimum MCM technology. The MCCM is simply a small MCM signal line pitch Ps that can be fabricated on a given on a thin metal carrier that can be bonded or mechan- substrate technology, is usually normalized to a given ically attached to a PWB. The metal bottom acts as square dimension such as 1 in. or 1 cm. Sometimes it both a heat spreader and a stress interposer for the is normalized to the size of pitch Pp of the chip carrier MCM substrate. The MCCM has peripheral
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