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Sifive E21 Core Complex Manual 21G2.01.00 SiFive E21 Core Complex Manual 21G2.01.00 Copyright © 2021 by SiFive, Inc. All rights reserved. SiFive E21 Core Complex Manual Proprietary Notice Copyright © 2021 by SiFive, Inc. All rights reserved. SiFive E21 Core Complex Manual by SiFive, Inc. is licensed under Attribution-NonCommer- cialNoDerivatives 4.0 International. To view a copy of this license, visit: http://creativecom- mons.org/licenses/by-nc-nd/4.0 Information in this document is provided “as is,” with all faults. SiFive expressly disclaims all warranties, representations, and conditions of any kind, whether express or implied, including, but not limited to, the implied warranties or conditions of mer- chantability, fitness for a particular purpose and non-infringement. SiFive does not assume any liability rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation indirect, incidental, spe- cial, exemplary, or consequential damages. SiFive reserves the right to make changes without further notice to any products herein. Copyright © 2021 by SiFive, Inc. All rights reserved. SiFive E21 Core Complex Manual 21G2.01.00 Contents List of Tables .................................................................................................................. 8 List of Figures ..............................................................................................................12 1 Introduction ...........................................................................................................15 1.1 About this Document ...............................................................................................15 1.2 About this Release..................................................................................................16 1.3 E21 Core Complex Overview ...................................................................................16 1.4 E2 RISC‑V Core .....................................................................................................17 1.5 Interrupts ...............................................................................................................18 1.6 Debug Support .......................................................................................................18 1.7 Compliance ............................................................................................................18 2 List of Abbreviations and Terms ................................................................19 3 E2 RISC‑V Core ....................................................................................................21 3.1 Supported Modes ...................................................................................................21 3.2 Instruction Memory System......................................................................................21 3.2.1 Execution Memory Space ..............................................................................21 3.2.2 Instruction Fetch Unit.....................................................................................22 3.3 Execution Pipeline ..................................................................................................22 3.4 Data Memory System..............................................................................................23 3.4.1 Tightly-Integrated Memory (TIM).....................................................................24 3.5 Atomic Memory Operations......................................................................................24 3.6 Local Interrupts.......................................................................................................24 3.7 Physical Memory Protection (PMP)...........................................................................24 3.7.1 PMP Functional Description ...........................................................................25 3.7.2 PMP Region Locking .....................................................................................25 3.7.3 PMP Registers..............................................................................................25 Copyright © 2021 by SiFive, Inc. All rights reserved. 1 SiFive E21 Core Complex Manual 21G2.01.00 3.7.4 PMP and PMA ..............................................................................................28 3.7.5 PMP Programming Overview .........................................................................28 3.7.6 PMP and Paging ...........................................................................................30 3.7.7 PMP Limitations ............................................................................................30 3.7.8 Behavior for Regions without PMP Protection ..................................................30 3.7.9 Cache Flush Behavior on PMP Protected Region.............................................31 3.8 Hardware Performance Monitor................................................................................31 3.8.1 Performance Monitoring Counters Reset Behavior ...........................................31 3.8.2 Fixed-Function Performance Monitoring Counters ............................................31 3.8.3 Event-Programmable Performance Monitoring Counters...................................32 3.8.4 Event Selector Registers................................................................................32 3.8.5 Event Selector Encodings ..............................................................................32 3.8.6 Counter-Enable Registers ..............................................................................34 3.9 Ports...................................................................................................................... 34 3.9.1 Front Port .....................................................................................................34 3.9.2 Peripheral Port..............................................................................................34 3.9.3 System Port..................................................................................................34 4 Physical Memory Attributes and Memory Map ...................................36 4.1 Physical Memory Attributes Overview .......................................................................36 4.2 Memory Map ..........................................................................................................37 5 Programmer’s Model.........................................................................................39 5.1 Base Instruction Formats .........................................................................................39 5.2 I Extension: Standard Integer Instructions .................................................................40 5.2.1 R-Type (Register-Based) Integer Instructions...................................................41 5.2.2 I-Type Integer Instructions..............................................................................42 5.2.3 I-Type Load Instructions.................................................................................43 5.2.4 S-Type Store Instructions ...............................................................................44 5.2.5 Unconditional Jumps .....................................................................................45 5.2.6 Conditional Branches.....................................................................................46 5.2.7 Upper-Immediate Instructions.........................................................................47 5.2.8 Memory Ordering Operations .........................................................................47 Copyright © 2021 by SiFive, Inc. All rights reserved. 2 SiFive E21 Core Complex Manual 21G2.01.00 5.2.9 Environment Call and Breakpoints ..................................................................48 5.2.10 NOP Instruction...........................................................................................48 5.3 M Extension: Multiplication Operations......................................................................48 5.3.1 Division Operations .......................................................................................49 5.4 A Extension: Atomic Operations ...............................................................................49 5.4.1 Atomic Memory Operations (AMOs)................................................................49 5.5 C Extension: Compressed Instructions......................................................................50 5.5.1 Compressed 16-bit Instruction Formats ...........................................................50 5.5.2 Stack-Pointed-Based Loads and Stores ..........................................................51 5.5.3 Register-Based Loads and Stores...................................................................52 5.5.4 Control Transfer Instructions...........................................................................53 5.5.5 Integer Computational Instructions..................................................................54 5.6 B Extension: Bit Manipulation Instructions .................................................................57 5.6.1 Zba Extension...............................................................................................57 5.6.2 Zbb Extension...............................................................................................57 5.7 Zicsr Extension: Control and Status Register Instructions ...........................................60
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