Openrisc 1200

Practical System-on-Chip

OSHUG #17: 29 March 2012 Julius Baxter, Jeremy Bennett, opencores.org

● Introduction

● Systems On A Chip, IP cores, HDL, Implementation technologies (FPGA) ● OpenCores & OpenRISC Project ● Using ORPSoC ● Compiling software for OpenRISC bare metal

● Integrate many functions onto a single silicon die

● Result of increased IC consolidation

● Enabled by improvements in VLSI process

● Modern high-end SoCs integrate:

● µ/DSP/graphics processors

● Memory controllers

● DRAM, flash

● Communications

● USB, ethernet, i2c

● Bespoke processing, I/O Image source: http://spectrum.ieee.org/semiconductors/design/crossroads-for-mixedsignal-chips

● ASIC: Application- Specific Integrated Circuit

● Modern process for purely digital ASICs (no major analog circuitry on chip) relatively straight forward

● Most chip design houses are fabless – they do not own and operate own manufacturing facility

Copyright © 2012 Julius Baxter and Jeremy Bennett. Sources: http://www.geek.com/images/procspecs/p4/p4-13wafer.jpg Freely available under a Creative Commonshttp://www.cadence.com/products/di/soc_encounter/pages/default.aspx license Fabless ASIC Development Process

Project Develop or buy IP? Selection/Specification ?

Determine implementation based on divide-and-conquer approach. Emphasis on re-use of existing IP or most efficient development stratergy

Design implementation, verification. A digital design engineer hard at work, RTL description in synthesisable HDL overlooked by expectant management

Process into manufacturable format. Source: http://www.ipod.org.uk/reality/reality_universe_computer.asp RTL -> gatelevel netlist -> EDA tool vendor-specific database for many and varied processing stages

Generate final layout, transfer to fab. Usually GDSII format (largely just planar geometric shapes and metadata) Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative CommonsSource: http://freecode.com/projects/socgdslicense FPGA Development Process, In Comparison

Front-end ASIC FPGA Design implementation, verification. RTL description in synthesisable HDL

Back-end

Process into manufacturable format. Process into FPGA configuration file. RTL -> gatelevel netlist -> RTL -> FPGA netlist -> EDA tool vendor-specific database FPGA bitstream for many and varied processing stages

Generate final layout, transfer to fab. Program/Configure FPGA Usually GDSII format (largely just planar Download generated bitstream geometric shapes and metadata)

● Decide on function and Develop or buy IP? rough breakdown of how to achieve that ? ● Select units of semiconductor intellectual property (IP cores) for the job at hand IP cores are units intended to provide a specific functionality and: ● usually provide a control mechanism via a standardised protocol (typically over a memory-mapped bus) ● are delivered in an electronic format (normally files with hardware description language, or HDL, code) which can be built and tested with the rest of the system ● are ultimately synthesised (combined) into the overall chip design so become part of the whole chip Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license IP Cores

● IP core design houses ● Along with reuse and aim to design IP for configurability are maximum reuse (an requirements for: industry mantra) this means: ● a demonstrably verified and 'proven' design ● Very configurable (heavy (bugs causing a re-fab use of parameterised can cost $10k->$1M+) options) ● Maximum area and ● Try to be application- generic power efficiency

● Typically µ-processor based, with on-chip µ-processor µ-processor communication done via Bus master Bus master internal bus

● Highly configurable bus arbiter ● Many on-chip bus standards:

● Wishbone

● ARM AMBA Non-volatile DSP memory I/O controller ● OCP memory Bus slave Logic Bus slave Bus slave 0x0000-0xf000 Bus slave 0xf100-0xf200 ● IBM CoreConnect 0xfc00-0xff00 0xf000-0xf100

● The SoC interconnect is what ties the IP blocks together ● Usually a memory- mapped bus providing access to control registers and memories

Copyright © 2012 Julius Baxter and JeremySource: http://www.design-reuse.com/articles/14612/future-trends-in-soc-interconnect.html Bennett. Freely available under a Creative Commons license SoC Development Summary

● A large part of SoC design work is combination and verification (testing) of a set of IP

● Confirm it's implementable

● Confirm it works in your particular configuration

● Confirm it has sufficient capacity for the intended application

Source: http://www.eurekatech.com/

● IP blocks for implementation in modern digital VLSI process are usually designed using a hardware description language

● VHDL

● Verilog

● SystemVerilog increasingly

● Crucially allow the ● Synchronous elements such as registers (flip-flops) description of store the state of the incoming signal based on ● Synchronous the rising/falling of the elements clock

● Combinatorial ● Combinatorial elements logic comprise the logical functions between synchronous elements

● Always sampling on each rising edge of the clock, output to 'D' wire logic_a_output; /* assigned elsewhere */ after a short time afterward, valid wire logic_b_input; until next rising clock edge reg q; ● The simplest memory element, also considered a 1-cycle delay always @(posedge clock) q <= logic_a_output; /* the 'D' input */

assign logic_b_input = q;

Logic A D Q Logic B

falling edge rising edge D-type flip-flop clock t (period), freq = 1/t Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Combinatorial logic in Verilog

● Essentially any logic, arithmetic, conditional operator

assign d = !(a | b);

F assign e = b & c;

assign q = d | e;

Assign f = e ? a : q;

● Provides ways of describing the propagation of time and signal dependencies (sensitivity) ● Block-based structure

● As design for re-use is emphasised, modular design is important.

● Abstraction and organisation is achieved by organising smaller, repeatable parts of a design into modules, much like functions in any other language

● Verilog could be used to ● Higher level design is describe a design at a low or achieved through the use high level of abstraction of Verilog's arithmetic ● An example of quite low level operators which can infer Verilog is a gatelevel netlist rather complex logic which describes each and (multipliers, adders) or every atomic cell and their case statements on wide interconnections in a design busses which can also infer large amounts of logic (multiplexors)

● Most common level at which ● Synchronous, or clock-based design is described is the register behaviour, results in flip- transfer level (RTL) flops/registers being used to implement the design ● Synthesisable Verilog is commonly referred to as RTL ● Combinatorial logic, or descriptions of logical functions, are ● RTL? A description of the values implemented in fundamental logic signals should take on when the components in hardware (not, and, clock, or other signals, change or, xor etc.) their values

Logic A D Q Logic B D Q Logic C

● Code in a ● You are ultimately synthesisable intending to implement your logic with a subset of the particular technology

language ● Technology in this case is supported by the used to refer to the ASIC synthesis tool in process or FPGA which will have the design 'put use on it' – each provide a library of cells which can be used to implement the design

● Field Programmable Gate ● American FPGA Array vendor Xilinx uses ● An array of multi-purpose thousands of lookup logic which can be tables (LUTs) which configured to create (within reason) arbitrary have signals routed logical functions and through to emulate interconnections between the logic functions them the designer describes in the HDL

● FPGAs contain arrays ● They are reconfigurable so of the bread-and- can be applied for a wide butter of digital logic variety of designs (combinatorial and ● Have area, power, sequential logic operating frequency disadvantages when elements in the LUTs) compared to ASIC as well as: ● Often used for ASIC ● Routing interconnect prototyping ● RAMs

● I/O hardware

● Clock generation

● Are now big ● How do we get enough to from Verilog to an implement FPGA configuration systems-on-chip file? (consiting of processor, memory, I/O, accelerators) capable of running Linux distros

● Each ASIC process, ● The synthesis tool FPGA generation must be aware of this and family provide and optimise and map the design described implementation in the HDL to the components in the targeted technology way of gates and ● The synthesised macro cells (RAMs, design is described in adders, multipliers) the synthesisable subset of the HDL

● The technology an ● IP blocks have a lot of 'tunability' for synthesis IP block will be (removing unwanted or used on is unnecessary or unimplementable features.) determined by SoC ● Verilog has a preprocessor, designers so features can be selected with a set of defines, ● IP designers don't equivalent to C #defines know this and ● Verilog parameters are similar and are a 'compile- must design time' (synthesis-time) accordingly option

147,001 registered users reported as of 28 March 2012 919 projects as of 28 March 2012

Founded by OpenRISC 1000 OpenRISC 1000 Damjan Lampret developed commercial deployment

1999 2007 2011

Primary support Flextronics Owned by ORSoC AB

Web: www.opencores.org and www.openrisc.net IRC: freenode.net, channel #opencores

● Objective to develop a family of open source RISC designs

● 32 and 64-bit architectures

● floating point support

● vector operation support

● Key features

● fully free and open source

● linear address space

● register-to-register ALU operations

● two addressing modes

● delayed branches

● Harvard or Stanford memory MMU/cache architecture

● fast context switch

● Looks rather like MIPS or DLX

OpenRISC 1200 ● 32-bit Harvard RISC architecture

Power Inst W ● MIPS/DLX like instruction set Mgmt MMU i s ● first in OpenRISC 1000 family h ● originally developed 1999-2001 B o ● J CPU Open source under the T Debug Inst n A Unit Cache e ● GNU Lesser General Public License G ALU ● allows reuse as a component

● Configurable design

Tick Data W ● caches and MMUs optional Timer MMU i s ● core instruction set

h ● B Source code Verilog 2001 o ● approx 32k lines of code Data n PIC Cache e ● Full GNU tool chain and Linux port

● various RTOS ported as well

● Combined reference implementation and board ORPSoC adaptations Clock, Reset management OR1200 ● Reference implementation – minimal SoC for processor testing, development Memory ● Controller compilable into cycle-accurate model Wish- ● Boards ports target multiple bone Bus technologies UART Arbiter ● Lowers barrier to entry for OpenRISC-based SoC design

SoC ● Push-button compile flow Peripheral A Debug ● Interface JTAG Largely utilises open-source EDA tools TAP

● Objective is to use an open source EDA tool chain

● back end tools for FGPA all proprietary

– free (as in beer) versions available

● front end tools now have open source alternatives

● OpenRISC 1000 simulation models

● Or1ksim: golden reference ISS

– C/SystemC interpreting ISS, 2-5 MIPS

● Verilator cycle accurate model from the Verilog RTL

– 130kHz in C++ or SystemC

● Icarus Verilog event driven simulation

– 1.4kHz, 50x slower than commercial alternatives

● All OpenRISC 1000 simulation models suitable for SW use

● all support GDB debug interface

● A standard GNU tool chain

● binutils 2.20.1

● gcc 4.5.1

● gdb 7.3 (for BCS use only!)

● C and C++ language support

● Library support

● static libraries only

● newlib 1.18.0 for bare metal (or32-elf-*)

● uClibc 0.9.32 for Linux applications (or32-linux-*)

● Testing

● regression tested using Or1ksim (both tool chains)

● or32-linux-* regression tested on hardware

● or32-elf-* regression tested on a Verilator model Board and OS Support

● Boards with BSP implementations

● Or1ksim

● Xilinx ML501, Terasic Altera DE-2, DE0-nano, ...

● RTOS support

● FreeRTOS, RTEMS and eCos all ported

● Linux support

● adopted into Linux 3.1 kernel mainline

● some limitations (kernel debug, ptrace)

● BusyBox as application environment

● Debug interfaces

● JTAG for bare metal

● gdbserver over Ethernet for Linux applications Software Development Remote Connection to GDB

TCP/IP USB JTAG RSP GDB I/F Server RSP

TCP/IP SystemC RSP SystemC GDB Server Model RSP I/F

(gdb)(gdb) targettarget remoteremote :51000:51000

● Download the source: svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1ksim svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/gnu-src cd gnu-src; git clone git://git.openrisc.net/jonas/uClibc; cd .. cd gnu-src; git clone git://git.openrisc.net/jonas/linux; cd ..

● Build and install Or1ksim cd or1ksim; mkdir bd; cd bd ../configure --target=or32-elf32 --prefix=/opt/or1ksim-new make; make install; make pdf; cd ../..

● Build and install the tool chains into /opt/or32-new cd gnu-src ./bld-all.sh --force --prefix /opt/or32-new \ --or1ksim-dir /opt/or1ksim-new \ --uclibc-dir uClibc --linux-dir linux export PATH=$PATH:/opt/or1ksim-new:/opt/or32-new/bin

● You can then use the tools to build BusyBox and Linux

● see http://opencores.org/or1k/OR1K:Community_Portal

● Stefan Wallentowitz at TUM

● multicore version of OpenRISC 1200 ● student working on LLVM ● Pete Gavin

● bringing the GNU tool chain up to date ● Ruben Diez

● automated nightly builds ● common test platform for models and HW

● “Reference build” ● “Board builds”

● Processor testing ● Targeted at platform particular FPGA ● Not technology boards targeted ● Live in own sub- ● Can build fast project cycle-accurate ● Intended to provide model “push-button” synthesis flows

● Provides framework for users to experience digital design and, hopefully, get commodity FPGA development boards running an open source system

● FPGA majors provide non-free (libre and beer) SoC implementations :( ● Potential uses are numerous but use cases for bespoke processing or I/O are common

● Develop an IP for SHA256/DSP/motor control and instantiate multiple on FPGA along with OR1200 running Linux, connected via ethernet

● Simplest useful ORPSoC Reference Design system for OR1200 BootROM Insn. processor Bus verification Memory Controller

● 32-bit “On-chip” memory Data Bus Clock, RST ● Debug interface control – Can master bus UART SoC 8-bit Debug ● Data JTAG UART Interrupt Interface Bus TAP Generator ● Interrupt generator

● Can execute a basic test, running the CPU through bootup, into a main() loop and immediately exiting orpsocv2$ cd sim/run run$ make rtl-test TEST=or1200-simple VCD=1

● The VCD=1 will create a dump of the internal signals which can be viewed in a waveform viewer such as GTKWave

● Running a test will cause software to be built. This includes:

● A simple C library containing basically rand() and printf()

● Low-level CPU functions for features like interrupts and timers

● The boot code (OR1K assembly, crt0.S)

● Some application code ● It is all compiled and converted into appropriate format for loading into sim.

Copyright © 2012 Julius Baxter and Jeremy Bennett. 50 Freely available under a Creative Commons license ORPSoC simulation directories sim$ tree -L 2 . ● All sims launched from ├── bin sim/run but output │ ├── definesgen.inc generated in sim/out │ ├── Makefile │ └── refdesign-or1ksim.cfg ● Some intermediate files ├── out │ ├── or1200-simple-executed.log generated in sim/run │ ├── or1200-simple-general.log │ ├── or1200-simple-lookup.log ● VCD in sim/out │ ├── or1200-simple-sprs.log ● Memory image of program │ ├── or1200-simple.vcd │ └── vvp.log we executed was in └── run sim/run/sram.vmem ├── icarus.scr (symlink to it) ├── Makefile ├── sram.vmem → ../../sw/tests/or1200/sim/or1200- simple.vmem ├── test-defines.v └── vlogsim.elf

● A sub-project of ORPSoC intended boards$ tree -L 2 . to be built and run ├── actel │ ├── backend on a specific FPGA │ └── ordb1a3pe1500 ├── README system └── xilinx ├── atlys ● ├── backend Contained under ├── ml501 boards/ directory, └── s3adsp1800 then sorted by FPGA vendor

● Inherent modularity ... `define JTAG_DEBUG of SoC designs // `define RAM_WB // `define XILINX_SSRAM makes it relatively `define CFI_FLASH `define XILINX_DDR2 straight forward to `define UART0 `define GPIO0 add or remove // `define SPI0 features `define I2C0 `define I2C1 `define ETH0 ● Removing features `define ETH0_PHY_RST is usually as simple ... A defines file in as commenting out boards/xilinx/ml501/rtl/verilog/include/orpsoc-defines.v a `define

… // Do not implement Data cache //`define OR1200_NO_DC ● IP blocks usually have own // Do not implement Insn cache configuration information //`define OR1200_NO_IC

● A Verilog `defines header is // Do not implement Data MMU usually used to store config //`define OR1200_NO_DMMU

● Parameters on the // Do not implement Insn MMU instantiations are preferred as //`define OR1200_NO_IMMU it allows multiple instances // Size/type of insn/data cache if implemented with differing configurations // (consider available FPGA memory resources) //`define OR1200_IC_1W_16KB `define OR1200_IC_1W_32KB //`define OR1200_DC_1W_16KB `define OR1200_DC_1W_32KB

// Implement optional l.div/l.divu instructions // By default divide instructions are not implemented // to save area. `define OR1200_DIV_IMPLEMENTED ...

● Instantiate the core ORPSoC OR1200 BootROM in top-level Insn. Bus

● Memory Attach to bus Controller 32-bit DMA Data ● YOUR Bus Provide some CORE software clk/rst SoC Debug (driver/test) 8-bit InterfaceJTAG UART Data TAP Bus ● Attach I/O (if any) Interrupt Generator ● Add constraints to orpsoc_top back-end scripts

● Be aware of FPGA ● Ensure new pin technology (family, mapping applied variant) and (which signals whether existing from ORPSoC go to clocking and which pins on the memory device/board) components can be ● Check design fits used on device (quick synthesis check)

● Two debug options ● Be sure to ● “Mohor” SoC debug IF determine debug ● Advanced debug IF solution! ● Both use JTAG physical layer

● Mohor adds own JTAG TAP and needs 4 extra pins Diagram of Mohor Debug Interface ● adv_debug_if can use Connecting to ORPSoC FPGA's TAP and save pins

Constrains File (.xcf) Verilog Source Project file (.prj) Commands (.xst) ● Example flow

based on Xilinx xst tools (Xilinx Synthesis Tool)

NGC Constrains File (.ucf) FPGA configuration file (binary bitsream) ngdbuild

bitgen (programming file generation) NGD

PAR'ed NCD map

Place And Route (par) Mapped NCD

● GNU tool chain for ● Newlib's libgloss both bare metal handles low level and Linux interaction userspace (supposed to programs implement syscall support.) ● Bare metal tol chain relies on ● OR1K libgloss is newlib for its C designed for bare library metal usage

cat gnu-src/newlib-1.18.0/libgloss/or32/ml501.S ● A single object file /* * Define symbols to be used during startup - must be compiled * file is linked at compile time * */ which contains .global _board_mem_base .global _board_mem_size some symbols .global _board_clk_freq

defining, eg. _board_mem_base: .long0x0 _board_mem_size: .long0x800000 ● Clock frequency of _board_clk_freq: .long66666666

design /* Peripheral information - Set base to 0 if not present*/ .global _board_uart_base ● UART address on .global _board_uart_baud .global _board_uart_IRQ bus _board_uart_base: .long0x90000000 _board_uart_baud: .long115200 _board_uart_IRQ: .long2 Copyright © 2012 Julius Baxter and Jeremy Bennett. 61 Freely available under a Creative Commons license Compiling with new board library

● Once the file is ● The compiled with the -mboard=boardna correct values, it me switch can be should be archived now passed to the and placed along compiler and side the rest of the software should newlib board initialise correctly support files: for the board

●$TOOLCHDIR/or32-elf/lib/boards//libboard.a

● Create a basic ● Run it in or1ksim helloworld C file: $ or32-elf-sim -m8M hello #include Seeding random generator with value ... int main(void) Or1ksim 2012-03-23 Building automata... done { ... printf(“Hello world!\n”); Section: .jcr, vaddr: 0x000089bc,... return 0; Section: .data, vaddr: 0x000089c0, ... Hello world! } exit(0) ● @reset : cycles 0, insn #0 Compile it: @exit : cycles 3692, insn #2842 diff : cycles 3692, insn #2842 or32-elf-gcc hello.c -o hello ● Note: GCC defaults to use the”or1ksim” board