DOCSLIB.ORG

Openrisc 1200

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Openrisc 1200 Practical System-on-Chip OSHUG #17: 29 March 2012 Julius Baxter, Jeremy Bennett, opencores.org Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Overview ● Introduction ● Systems On A Chip, IP cores, HDL, Implementation technologies (FPGA) ● OpenCores & OpenRISC Project ● Using ORPSoC ● Compiling software for OpenRISC bare metal Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license System On A Chip Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license System on a Chip (SoC) ● Integrate many functions onto a single silicon die ● Result of increased IC consolidation ● Enabled by improvements in VLSI process ● Modern high-end SoCs integrate: ● µ/DSP/graphics processors ● Memory controllers ● DRAM, flash ● Communications ● USB, ethernet, i2c ● Bespoke processing, I/O Image source: http://spectrum.ieee.org/semiconductors/design/crossroads-for-mixedsignal-chips Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Chip Implementation Process ● ASIC: Application- Specific Integrated Circuit ● Modern process for purely digital ASICs (no major analog circuitry on chip) relatively straight forward ● Most chip design houses are fabless – they do not own and operate own manufacturing facility Copyright © 2012 Julius Baxter and Jeremy Bennett. Sources: http://www.geek.com/images/procspecs/p4/p4-13wafer.jpg Freely available under a Creative Commonshttp://www.cadence.com/products/di/soc_encounter/pages/default.aspx license Fabless ASIC Development Process Project Develop or buy IP? Selection/Specification ? Determine implementation based on divide-and-conquer approach. Emphasis on re-use of existing IP or most efficient development stratergy Design implementation, verification. A digital design engineer hard at work, RTL description in synthesisable HDL overlooked by expectant management Process into manufacturable format. Source: http://www.ipod.org.uk/reality/reality_universe_computer.asp RTL -> gatelevel netlist -> EDA tool vendor-specific database for many and varied processing stages Generate final layout, transfer to fab. Usually GDSII format (largely just planar geometric shapes and metadata) Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative CommonsSource: http://freecode.com/projects/socgdslicense FPGA Development Process, In Comparison Front-end ASIC FPGA Design implementation, verification. RTL description in synthesisable HDL Back-end Process into manufacturable format. Process into FPGA configuration file. RTL -> gatelevel netlist -> RTL -> FPGA netlist -> EDA tool vendor-specific database FPGA bitstream for many and varied processing stages Generate final layout, transfer to fab. Program/Configure FPGA Usually GDSII format (largely just planar Download generated bitstream geometric shapes and metadata) Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license IP Cores in SoCs Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license System Design with IP cores ● Decide on function and Develop or buy IP? rough breakdown of how to achieve that ? ● Select units of semiconductor intellectual property (IP cores) for the job at hand IP cores are units intended to provide a specific functionality and: ● usually provide a control mechanism via a standardised protocol (typically over a memory-mapped bus) ● are delivered in an electronic format (normally files with hardware description language, or HDL, code) which can be built and tested with the rest of the system ● are ultimately synthesised (combined) into the overall chip design so become part of the whole chip Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license IP Cores ● IP core design houses ● Along with reuse and aim to design IP for configurability are maximum reuse (an requirements for: industry mantra) this means: ● a demonstrably verified and 'proven' design ● Very configurable (heavy (bugs causing a re-fab use of parameterised can cost $10k->$1M+) options) ● Maximum area and ● Try to be application- generic power efficiency Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Modern Implementations ● Typically µ-processor based, with on-chip µ-processor µ-processor communication done via Bus master Bus master internal bus ● Highly configurable bus arbiter ● Many on-chip bus standards: ● Wishbone ● ARM AMBA Non-volatile DSP memory I/O controller ● OCP memory Bus slave Logic Bus slave Bus slave 0x0000-0xf000 Bus slave 0xf100-0xf200 ● IBM CoreConnect 0xfc00-0xff00 0xf000-0xf100 ● A growing number of network-on-chip (NoC) interconnects, too Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license SoC Interconnect ● The SoC interconnect is what ties the IP blocks together ● Usually a memory- mapped bus providing access to control registers and memories Copyright © 2012 Julius Baxter and JeremySource: http://www.design-reuse.com/articles/14612/future-trends-in-soc-interconnect.html Bennett. Freely available under a Creative Commons license SoC Development Summary ● A large part of SoC design work is combination and verification (testing) of a set of IP ● Confirm it's implementable ● Confirm it works in your particular configuration ● Confirm it has sufficient capacity for the intended application Source: http://www.eurekatech.com/ Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Describing The Hardware Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Describing the design ● IP blocks for implementation in modern digital VLSI process are usually designed using a hardware description language ● VHDL ● Verilog ● SystemVerilog increasingly Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Hardware Description Languages ● Crucially allow the ● Synchronous elements such as registers (flip-flops) description of store the state of the incoming signal based on ● Synchronous the rising/falling of the elements clock ● Combinatorial ● Combinatorial elements logic comprise the logical functions between synchronous elements Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license A synchronous element in Verilog ● Always sampling on each rising edge of the clock, output to 'D' wire logic_a_output; /* assigned elsewhere */ after a short time afterward, valid wire logic_b_input; until next rising clock edge reg q; ● The simplest memory element, also considered a 1-cycle delay always @(posedge clock) q <= logic_a_output; /* the 'D' input */ assign logic_b_input = q; Logic A D Q Logic B falling edge rising edge D-type flip-flop clock t (period), freq = 1/t Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Combinatorial logic in Verilog ● Essentially any logic, arithmetic, conditional operator assign d = !(a | b); F assign e = b & c; assign q = d | e; Assign f = e ? a : q; Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Verilog HDL ● Provides ways of describing the propagation of time and signal dependencies (sensitivity) ● Block-based structure Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Verilog Module Instantiations ● As design for re-use is emphasised, modular design is important. ● Abstraction and organisation is achieved by organising smaller, repeatable parts of a design into modules, much like functions in any other language Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Levels of Abstraction ● Verilog could be used to ● Higher level design is describe a design at a low or achieved through the use high level of abstraction of Verilog's arithmetic ● An example of quite low level operators which can infer Verilog is a gatelevel netlist rather complex logic which describes each and (multipliers, adders) or every atomic cell and their case statements on wide interconnections in a design busses which can also infer large amounts of logic (multiplexors) Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Register Transfer Level ● Most common level at which ● Synchronous, or clock-based design is described is the register behaviour, results in flip- transfer level (RTL) flops/registers being used to implement the design ● Synthesisable Verilog is commonly referred to as RTL ● Combinatorial logic, or descriptions of logical functions, are ● RTL? A description of the values implemented in fundamental logic signals should take on when the components in hardware (not, and, clock, or other signals, change or, xor etc.) their values Logic A D Q Logic B D Q Logic C Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Implementation Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Getting the design onto the silicon ● Code in a ● You are ultimately synthesisable intending to implement your logic with a subset of the particular technology language ● Technology in this case is supported by the used to
Load more

Recommended publications
  • Debugging System for Openrisc 1000- Based Systems
    Debugging System for OpenRisc 1000- based Systems Nathan Yawn [email protected] 05/12/09 Copyright (C) 2008 Nathan Yawn Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license should be included with this document. If not, the license may be obtained from www.gnu.org, or by writing to the Free Software Foundation. This document is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. History Rev Date Author Comments 1.0 20/7/2008 Nathan Yawn Initial version Contents 1.Introduction.............................................................................................................................................5 1.1.Overview.........................................................................................................................................5 1.2.Versions...........................................................................................................................................6 1.3.Stub-based methods.........................................................................................................................6 2.System Components................................................................................................................................7
    [Show full text]
  • Implementation, Verification and Validation of an Openrisc-1200
    (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 10, No. 1, 2019 Implementation, Verification and Validation of an OpenRISC-1200 Soft-core Processor on FPGA Abdul Rafay Khatri Department of Electronic Engineering, QUEST, NawabShah, Pakistan Abstract—An embedded system is a dedicated computer system in which hardware and software are combined to per- form some specific tasks. Recent advancements in the Field Programmable Gate Array (FPGA) technology make it possible to implement the complete embedded system on a single FPGA chip. The fundamental component of an embedded system is a microprocessor. Soft-core processors are written in hardware description languages and functionally equivalent to an ordinary microprocessor. These soft-core processors are synthesized and implemented on the FPGA devices. In this paper, the OpenRISC 1200 processor is used, which is a 32-bit soft-core processor and Fig. 1. General block diagram of embedded systems. written in the Verilog HDL. Xilinx ISE tools perform synthesis, design implementation and configure/program the FPGA. For verification and debugging purpose, a software toolchain from (RISC) processor. This processor consists of all necessary GNU is configured and installed. The software is written in C components which are available in any other microproces- and Assembly languages. The communication between the host computer and FPGA board is carried out through the serial RS- sor. These components are connected through a bus called 232 port. Wishbone bus. In this work, the OR1200 processor is used to implement the system on a chip technology on a Virtex-5 Keywords—FPGA Design; HDLs; Hw-Sw Co-design; Open- FPGA board from Xilinx.
    [Show full text]
  • Openpiton: an Open Source Manycore Research Framework
    OpenPiton: An Open Source Manycore Research Framework Jonathan Balkind Michael McKeown Yaosheng Fu Tri Nguyen Yanqi Zhou Alexey Lavrov Mohammad Shahrad Adi Fuchs Samuel Payne ∗ Xiaohua Liang Matthew Matl David Wentzlaff Princeton University fjbalkind,mmckeown,yfu,trin,yanqiz,alavrov,mshahrad,[email protected], [email protected], fxiaohua,mmatl,[email protected] Abstract chipset Industry is building larger, more complex, manycore proces- sors on the back of strong institutional knowledge, but aca- demic projects face difficulties in replicating that scale. To Tile alleviate these difficulties and to develop and share knowl- edge, the community needs open architecture frameworks for simulation, synthesis, and software exploration which Chip support extensibility, scalability, and configurability, along- side an established base of verification tools and supported software. In this paper we present OpenPiton, an open source framework for building scalable architecture research proto- types from 1 core to 500 million cores. OpenPiton is the world’s first open source, general-purpose, multithreaded manycore processor and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core with modifica- Figure 1: OpenPiton Architecture. Multiple manycore chips tions and builds upon it with a scratch-built, scalable uncore are connected together with chipset logic and networks to creating a flexible, modern manycore design. In addition, build large scalable manycore systems. OpenPiton’s cache OpenPiton provides synthesis and backend scripts for ASIC coherence protocol extends off chip. and FPGA to enable other researchers to bring their designs to implementation. OpenPiton provides a complete verifica- tion infrastructure of over 8000 tests, is supported by mature software tools, runs full-stack multiuser Debian Linux, and has been widespread across the industry with manycore pro- is written in industry standard Verilog.
    [Show full text]
  • Small Soft Core up Inventory ©2019 James Brakefield Opencore and Other Soft Core Processors Reverse-U16 A.T
    tool pip _uP_all_soft opencores or style / data inst repor com LUTs blk F tool MIPS clks/ KIPS ven src #src fltg max max byte adr # start last secondary web status author FPGA top file chai e note worthy comments doc SOC date LUT? # inst # folder prmary link clone size size ter ents ALUT mults ram max ver /inst inst /LUT dor code files pt Hav'd dat inst adrs mod reg year revis link n len Small soft core uP Inventory ©2019 James Brakefield Opencore and other soft core processors reverse-u16 https://github.com/programmerby/ReVerSE-U16stable A.T. Z80 8 8 cylcone-4 James Brakefield11224 4 60 ## 14.7 0.33 4.0 X Y vhdl 29 zxpoly Y yes N N 64K 64K Y 2015 SOC project using T80, HDMI generatorretro Z80 based on T80 by Daniel Wallner copyblaze https://opencores.org/project,copyblazestable Abdallah ElIbrahimi picoBlaze 8 18 kintex-7-3 James Brakefieldmissing block622 ROM6 217 ## 14.7 0.33 2.0 57.5 IX vhdl 16 cp_copyblazeY asm N 256 2K Y 2011 2016 wishbone extras sap https://opencores.org/project,sapstable Ahmed Shahein accum 8 8 kintex-7-3 James Brakefieldno LUT RAM48 or block6 RAM 200 ## 14.7 0.10 4.0 104.2 X vhdl 15 mp_struct N 16 16 Y 5 2012 2017 https://shirishkoirala.blogspot.com/2017/01/sap-1simple-as-possible-1-computer.htmlSimple as Possible Computer from Malvinohttps://www.youtube.com/watch?v=prpyEFxZCMw & Brown "Digital computer electronics" blue https://opencores.org/project,bluestable Al Williams accum 16 16 spartan-3-5 James Brakefieldremoved clock1025 constraint4 63 ## 14.7 0.67 1.0 41.1 X verilog 16 topbox web N 4K 4K N 16 2 2009
    [Show full text]
  • Evaluation of Synthesizable CPU Cores
    Evaluation of synthesizable CPU cores DANIEL MATTSSON MARCUS CHRISTENSSON Maste r ' s Thesis Com p u t e r Science an d Eng i n ee r i n g Pro g r a m CHALMERS UNIVERSITY OF TECHNOLOGY Depart men t of Computer Engineering Gothe n bu r g 20 0 4 All rights reserved. This publication is protected by law in accordance with “Lagen om Upphovsrätt, 1960:729”. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior permission of the authors. Daniel Mattsson and Marcus Christensson, Gothenburg 2004. Evaluation of synthesizable CPU cores Abstract The three synthesizable processors: LEON2 from Gaisler Research, MicroBlaze from Xilinx, and OpenRISC 1200 from OpenCores are evaluated and discussed. Performance in terms of benchmark results and area resource usage is measured. Different aspects like usability and configurability are also reviewed. Three configurations for each of the processors are defined and evaluated: the comparable configuration, the performance optimized configuration and the area optimized configuration. For each of the configurations three benchmarks are executed: the Dhrystone 2.1 benchmark, the Stanford benchmark suite and a typical control application run as a benchmark. A detailed analysis of the three processors and their development tools is presented. The three benchmarks are described and motivated. Conclusions and results in terms of benchmark results, performance per clock cycle and performance per area unit are discussed and presented. Sammanfattning De tre syntetiserbara processorerna: LEON2 från Gaisler Research, MicroBlaze från Xilinx och OpenRISC 1200 från OpenCores utvärderas och diskuteras.
    [Show full text]
  • An Evaluation of Soft Processors As a Reliable Computing Platform
    Brigham Young University BYU ScholarsArchive Theses and Dissertations 2015-07-01 An Evaluation of Soft Processors as a Reliable Computing Platform Michael Robert Gardiner Brigham Young University - Provo Follow this and additional works at: https://scholarsarchive.byu.edu/etd Part of the Electrical and Computer Engineering Commons BYU ScholarsArchive Citation Gardiner, Michael Robert, "An Evaluation of Soft Processors as a Reliable Computing Platform" (2015). Theses and Dissertations. 5509. https://scholarsarchive.byu.edu/etd/5509 This Thesis is brought to you for free and open access by BYU ScholarsArchive. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of BYU ScholarsArchive. For more information, please contact [email protected], [email protected]. An Evaluation of Soft Processors as a Reliable Computing Platform Michael Robert Gardiner A thesis submitted to the faculty of Brigham Young University in partial fulfillment of the requirements for the degree of Master of Science Michael J. Wirthlin, Chair Brad L. Hutchings Brent E. Nelson Department of Electrical and Computer Engineering Brigham Young University July 2015 Copyright © 2015 Michael Robert Gardiner All Rights Reserved ABSTRACT An Evaluation of Soft Processors as a Reliable Computing Platform Michael Robert Gardiner Department of Electrical and Computer Engineering, BYU Master of Science This study evaluates the benefits and limitations of soft processors operating in a radiation-hardened FPGA, focusing primarily on the performance and reliability of these systems. FPGAs designs for four popular soft processors, the MicroBlaze, LEON3, Cortex- M0 DesignStart, and OpenRISC 1200 are developed for a Virtex-5 FPGA. The performance of these soft processor designs is then compared on ten widely-used benchmark programs.
    [Show full text]
  • Open-Source 32-Bit RISC Soft-Core Processors
    IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 2, Issue 4 (May. – Jun. 2013), PP 43-46 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org Open-Source 32-Bit RISC Soft-Core Processors Rahul R.Balwaik, Shailja R.Nayak, Prof. Amutha Jeyakumar Department of Electrical Engineering, VJTI, Mumbai-19, INDIA Abstract: A soft-core processor build using a Field-Programmable Gate Array (FPGA)’s general-purpose logic represents an embedded processor commonly used for implementation. In a large number of applications; soft-core processors play a vital role due to their ease of usage. Soft-core processors are more advantageous than their hard-core counterparts due to their reduced cost, flexibility, platform independence and greater immunity to obsolescence. This paper presents a survey of a considerable number of soft core processors available from the open-source communities. Some real world applications of these soft-core processors are also discussed followed by the comparison of their several features and characteristics. The increasing popularity of these soft-core processors will inevitably lead to more widespread usage in embedded system design. This is due to the number of significant advantages that soft-core processors hold over their hard-core counterparts. Keywords: Field-Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), open- source, soft-core processors. I. INTRODUCTION Field-Programmable Gate Array (FPGA) has grown in capacity and performance, and is now one of the main implementation fabrics for designs, particularly where the products do not demand for custom integrated circuits. And in recent past due to the increased capacity and falling cost of the FPGA’s relatively fast and high density devices are today becoming available to the general public.
    [Show full text]
  • Latticemico32 Hardware Developer User Guide
    LatticeMico32 Hardware Developer User Guide May 2014 Copyright Copyright © 2014 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior written consent from Lattice Semiconductor Corporation. Trademarks Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, CleanClock, Custom Mobile Device, DiePlus, E2CMOS, ECP5, Extreme Performance, FlashBAK, FlexiClock, flexiFLASH, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, iCE Dice, iCE40, iCE65, iCEblink, iCEcable, iCEchip, iCEcube, iCEcube2, iCEman, iCEprog, iCEsab, iCEsocket, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDX2, ispGDXV, ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, Lattice Diamond, LatticeCORE, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeECP3, LatticeECP4, LatticeMico, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MACH, MachXO, MachXO2, MachXO3, MACO, mobileFPGA, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, Platform Manager, ProcessorPM, PURESPEED, Reveal, SensorExtender, SiliconBlue, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex
    [Show full text]
  • A High Performance Microprocessor with Dsp Extensions Optimized for the Virtex-4 Fpga
    A HIGH PERFORMANCE MICROPROCESSOR WITH DSP EXTENSIONS OPTIMIZED FOR THE VIRTEX-4 FPGA Andreas Ehliar∗, Per Karlstrom¨ †, Dake Liu Department of Electrical Engineering Linkoping¨ University Sweden email: [email protected], [email protected], [email protected] ABSTRACT In this paper we will present a high speed soft micropro- As the use of FPGAs increases, the importance of highly cessor core with DSP extensions optimized for the Virtex- optimized processors for FPGAs will increase. In this paper 4 FPGA family. The microarchitecture of the processor is we present the microarchitecture of a soft microprocessor carefully designed to allow for high speed operation. core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xil- 2. RELATED WORK inx’ Microblaze architecture on the same FPGA. At this fre- quency it is necessary to keep the logic complexity down There are many soft processor cores available for FPGA us- and this paper shows how this can be done while retaining age although Nios II, Mico32, and Microblaze are common sufficient functionality for a high performance processor. choices thanks to the support from their vendors. Altera’s Nios II [2]. is a 32-bit RISC processor that 1. INTRODUCTION comes in three flavors; e, s, and, f with a one, five, or six pipeline stages respectively. The use of FPGAs has increased steadily since their in- Xilinx’ Microblaze is a 32-bit RISC processor [10] opti- troduction. The first FPGAs were limited devices, usable mized for Xilinx FPGAs. mainly for glue logic whereas the capabilities of modern FP- Lattice’ Mico32 is a 32 bit RISC processor [7] with a six GAs allow for extremely varied use cases in everything from stage pipeline.
    [Show full text]
  • The Libre-SOC Hybrid 3D CPU
    The Libre-SOC Hybrid 3D CPU Augmenting the OpenPOWER ISA to provide 3D and Video instructions (properly and officially) [proposed for] OpenPOWER Summit 2020 Sponsored by NLnet's PET Programme September 10, 2020 Luke Kenneth Casson Leighton The Libre-SOC Hybrid 3D CPU Why another SoC? I Intel Management Engine, QA issues, Spectre I Endless proprietary drivers (affects product development cost) I Opportunity to drastically simplify driver development and engage in "long-tail" markets I Because for 30 years I Always Wanted To Design A CPU Luke Kenneth Casson Leighton The Libre-SOC Hybrid 3D CPU Why OpenPOWER? (but first: Evaluation Criteria) I Good ecosystem essential linux kernel, u-boot, compilers, OSes, Reference Implementation(s) I Supportive Foundation and Members need to be able to submit ISA augmentations (for proper peer review) I No NDAs, full transparency must be acceptable due to being funded under NLnet's PET Programme Luke Kenneth Casson Leighton The Libre-SOC Hybrid 3D CPU Why OpenPOWER? I RISC-V: closed secretive mailing lists, closed secretive ISA Working Groups, no acceptance of transparency requirements, not well-established enough I MIPS Open Initiative website was offline I ARM and x86 are proprietary (x86 too complex) I OpenRISC 1200 not enough adoption I Nyuzi GPU too specialist (not a general-purpose ISA) I MIAOW GPU is not a GPU (it's an AMD Vector Engine) I "rolling your own" out of the question (20+ man-years) I OpenPOWER: established for decades, excellent Foundation, Microwatt as Reference, approachable and friendly. Luke Kenneth Casson Leighton The Libre-SOC Hybrid 3D CPU What goes into a typical SoC? I 15 to 20mm BGA package: 2.5 to 5 watt power consumption heat sink normally not required (simplifies overall design) I Fully-integrated peripherals (not Northbridge/Southbridge) USB, HDMI, RGB/TTL, SD/MMC, I2C, UART, SPI, GPIO etc.
    [Show full text]
  • An Out-Of-Order Superscalar Processor on FPGA: the Reorder Buffer Design
    An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design Mathieu Rosière, Jean-lou Desbarbieux, Nathalie Drach, Franck Wajsbürt University of Pierre et Marie Curie – UPMC (Paris 6) LIP6 - France Abstract—Embedded systems based on FPGA (Field- ports on the register file and the reservation station (a Programmable Gate Arrays) must exhibit more performance for component of the out-of-order execution block) for each new applications. However, no high-performance superscalar soft cluster. Another design modification is to sequentially access to processor is available on the FPGA, because the superscalar complex structures. For example, the limitation of one architecture is not suitable for FPGAs. High-performance load/store instruction per cycle can simplify the load/store unit superscalar processors execute instructions out-of-order and it is and the data cache design. But these modifications may necessary to re-order instructions after execution. This task is decrease performance. performed by the ROB (ReOrder Buffer) that uses usually multi- ports RAM, but only two-port buffers are available in FPGA. In For our architecture studies, we use the Morpheo processor this work, we propose a FPGA friendly ROB (ReOrder Buffer) generator [6]. Morpheo can simulate an out-of-order architecture using only 2 ports RAM called a multi-bank ROB superscalar processor with configurable architectures (for architecture. The ROB is the main and more complex structure example, configurable coarse-grain as superscalar degree and in an out-of-order superscalar processor. Depending on processor configurable fine-grain as ReOrder Buffer (ROB) size). It architecture parameters, the FPGA implementation of our ROB supports the integer subset of OpenRISC 1000 instructions set compared to a classic architecture, requires 5 to 7 times less [2].
    [Show full text]
  • BCS OSSG Newsletter July 2011 Page 1 of 8 Figure 1: Overall Design of the Openrisc 1200
    Open Source Software Meets Open Source Hardware: The OpenRISC 1000 Jeremy Bennett, Embecosm Abstract This paper presents the OpenRISC 1200, an open source implementation of the OpenRISC 1000 architecture, verified using open source tools. The OpenRISC 1000 is supported by a modern GNU tool chain and is capable of running Linux as well as many real-time operating systems. 1 Introducing the OpenRISC 1000 Architecture The OpenRISC 1000 architecture defines a family of 32 and 64-bit RISC processors with a Harvard architecture [9]. The instruction set architecture (ISA) is similar to that of MIPS or DLX, offering 32 general purpose registers. The processor offers WishBone bus interfaces for instruction and memory access with IEEE 1149.1 JTAG as a debugging interface. Memory management units (MMU) and caches may optionally be included. The core instruction set features the common arithmetic/logic and control flow instructions. Optional additional instructions allow for hardware multiply/divide, additional logical instructions, floating point and vector operations. The ALU is a 4/5 stage pipeline, similar to that in early MIPS designs. A hardware debug unit provides access to all registers and main memory and allows external stall/unstall and reset of the processor via JTAG. This interface can be used to provide software debug access via the GDB remote serial protocol. One particularly useful feature is the parameterized NOP instruction, l.nop. The 16-bit immediate operand is ignored by hardware, but can be used by simulators to provide useful side-effects, such as host I/O and tracing. The design is completely open source, licensed under the GNU Lesser General Public License (LGPL), this means it can be included as an IP block in larger designs, without requiring that the rest of the design be open source.
    [Show full text]