Practical System-on-Chip OSHUG #17: 29 March 2012 Julius Baxter, Jeremy Bennett, opencores.org Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Overview ● Introduction ● Systems On A Chip, IP cores, HDL, Implementation technologies (FPGA) ● OpenCores & OpenRISC Project ● Using ORPSoC ● Compiling software for OpenRISC bare metal Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license System On A Chip Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license System on a Chip (SoC) ● Integrate many functions onto a single silicon die ● Result of increased IC consolidation ● Enabled by improvements in VLSI process ● Modern high-end SoCs integrate: ● µ/DSP/graphics processors ● Memory controllers ● DRAM, flash ● Communications ● USB, ethernet, i2c ● Bespoke processing, I/O Image source: http://spectrum.ieee.org/semiconductors/design/crossroads-for-mixedsignal-chips Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Chip Implementation Process ● ASIC: Application- Specific Integrated Circuit ● Modern process for purely digital ASICs (no major analog circuitry on chip) relatively straight forward ● Most chip design houses are fabless – they do not own and operate own manufacturing facility Copyright © 2012 Julius Baxter and Jeremy Bennett. Sources: http://www.geek.com/images/procspecs/p4/p4-13wafer.jpg Freely available under a Creative Commonshttp://www.cadence.com/products/di/soc_encounter/pages/default.aspx license Fabless ASIC Development Process Project Develop or buy IP? Selection/Specification ? Determine implementation based on divide-and-conquer approach. Emphasis on re-use of existing IP or most efficient development stratergy Design implementation, verification. A digital design engineer hard at work, RTL description in synthesisable HDL overlooked by expectant management Process into manufacturable format. Source: http://www.ipod.org.uk/reality/reality_universe_computer.asp RTL -> gatelevel netlist -> EDA tool vendor-specific database for many and varied processing stages Generate final layout, transfer to fab. Usually GDSII format (largely just planar geometric shapes and metadata) Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative CommonsSource: http://freecode.com/projects/socgdslicense FPGA Development Process, In Comparison Front-end ASIC FPGA Design implementation, verification. RTL description in synthesisable HDL Back-end Process into manufacturable format. Process into FPGA configuration file. RTL -> gatelevel netlist -> RTL -> FPGA netlist -> EDA tool vendor-specific database FPGA bitstream for many and varied processing stages Generate final layout, transfer to fab. Program/Configure FPGA Usually GDSII format (largely just planar Download generated bitstream geometric shapes and metadata) Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license IP Cores in SoCs Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license System Design with IP cores ● Decide on function and Develop or buy IP? rough breakdown of how to achieve that ? ● Select units of semiconductor intellectual property (IP cores) for the job at hand IP cores are units intended to provide a specific functionality and: ● usually provide a control mechanism via a standardised protocol (typically over a memory-mapped bus) ● are delivered in an electronic format (normally files with hardware description language, or HDL, code) which can be built and tested with the rest of the system ● are ultimately synthesised (combined) into the overall chip design so become part of the whole chip Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license IP Cores ● IP core design houses ● Along with reuse and aim to design IP for configurability are maximum reuse (an requirements for: industry mantra) this means: ● a demonstrably verified and 'proven' design ● Very configurable (heavy (bugs causing a re-fab use of parameterised can cost $10k->$1M+) options) ● Maximum area and ● Try to be application- generic power efficiency Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Modern Implementations ● Typically µ-processor based, with on-chip µ-processor µ-processor communication done via Bus master Bus master internal bus ● Highly configurable bus arbiter ● Many on-chip bus standards: ● Wishbone ● ARM AMBA Non-volatile DSP memory I/O controller ● OCP memory Bus slave Logic Bus slave Bus slave 0x0000-0xf000 Bus slave 0xf100-0xf200 ● IBM CoreConnect 0xfc00-0xff00 0xf000-0xf100 ● A growing number of network-on-chip (NoC) interconnects, too Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license SoC Interconnect ● The SoC interconnect is what ties the IP blocks together ● Usually a memory- mapped bus providing access to control registers and memories Copyright © 2012 Julius Baxter and JeremySource: http://www.design-reuse.com/articles/14612/future-trends-in-soc-interconnect.html Bennett. Freely available under a Creative Commons license SoC Development Summary ● A large part of SoC design work is combination and verification (testing) of a set of IP ● Confirm it's implementable ● Confirm it works in your particular configuration ● Confirm it has sufficient capacity for the intended application Source: http://www.eurekatech.com/ Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Describing The Hardware Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Describing the design ● IP blocks for implementation in modern digital VLSI process are usually designed using a hardware description language ● VHDL ● Verilog ● SystemVerilog increasingly Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Hardware Description Languages ● Crucially allow the ● Synchronous elements such as registers (flip-flops) description of store the state of the incoming signal based on ● Synchronous the rising/falling of the elements clock ● Combinatorial ● Combinatorial elements logic comprise the logical functions between synchronous elements Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license A synchronous element in Verilog ● Always sampling on each rising edge of the clock, output to 'D' wire logic_a_output; /* assigned elsewhere */ after a short time afterward, valid wire logic_b_input; until next rising clock edge reg q; ● The simplest memory element, also considered a 1-cycle delay always @(posedge clock) q <= logic_a_output; /* the 'D' input */ assign logic_b_input = q; Logic A D Q Logic B falling edge rising edge D-type flip-flop clock t (period), freq = 1/t Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Combinatorial logic in Verilog ● Essentially any logic, arithmetic, conditional operator assign d = !(a | b); F assign e = b & c; assign q = d | e; Assign f = e ? a : q; Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Verilog HDL ● Provides ways of describing the propagation of time and signal dependencies (sensitivity) ● Block-based structure Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Verilog Module Instantiations ● As design for re-use is emphasised, modular design is important. ● Abstraction and organisation is achieved by organising smaller, repeatable parts of a design into modules, much like functions in any other language Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Levels of Abstraction ● Verilog could be used to ● Higher level design is describe a design at a low or achieved through the use high level of abstraction of Verilog's arithmetic ● An example of quite low level operators which can infer Verilog is a gatelevel netlist rather complex logic which describes each and (multipliers, adders) or every atomic cell and their case statements on wide interconnections in a design busses which can also infer large amounts of logic (multiplexors) Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Register Transfer Level ● Most common level at which ● Synchronous, or clock-based design is described is the register behaviour, results in flip- transfer level (RTL) flops/registers being used to implement the design ● Synthesisable Verilog is commonly referred to as RTL ● Combinatorial logic, or descriptions of logical functions, are ● RTL? A description of the values implemented in fundamental logic signals should take on when the components in hardware (not, and, clock, or other signals, change or, xor etc.) their values Logic A D Q Logic B D Q Logic C Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Implementation Copyright © 2012 Julius Baxter and Jeremy Bennett. Freely available under a Creative Commons license Getting the design onto the silicon ● Code in a ● You are ultimately synthesisable intending to implement your logic with a subset of the particular technology language ● Technology in this case is supported by the used to