MPC107 PCI Bridge/Integrated Memory Controller Fact Sheet
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Freescale Semiconductor, Inc. Fact Sheet MPC107 PCI BRIDGE MEMORY CONTROLLER The MPC107 PCI Bridge/Integrated Memory Controller provides a bridge between the INTEGRATED MEMORY CONTROLLER Peripheral Component Interconnect (PCI) bus and Motorola MPC6xx, MPC7xx, and The memory interface controls processor and PCI . MPC74xx microprocessors. PCI support allows system designers to design systems interactions to main memory. It supports a variety of . quickly using peripherals already designed for PCI and the other standard interfaces programmable timing supporting DRAM (FPM, EDO), c available in the personal computer hardware environment. The MPC107 provides many SDRAM, and ROM/Flash ROM configurations, up to n of the other necessities for embedded applications, including a high-performance speeds of 100 MHz. I , memory controller and dual-processor support; two-channel flexible DMA controller; an r interrupt controller; an I2O-ready message unit; an inter-integrated circuit controller PCI BUS SUPPORT o (I2C); and low-skew clock drivers. The MPC107 contains an Embedded Programmable The MPC107 PCI interface is designed to connect the t Interrupt Controller (EPIC) featuring five hardware interrupts (IRQs) as well as 16 serial c processor and memory buses to the PCI local bus without u interrupts along with four timers. The MPC107 uses an advanced, 2.5V HiP3 process the need for “glue” logic at speeds up to 66 MHz. The d technology and is fully compatible with TTL devices. MPC107 acts as either a master or slave device on the n o MOTOROLA MPC107 BLOCK DIAGRAM c i m 60x Bus e S Memory Data Data Path e l ECC/Parity a Unit PIU c I O s 2 Memory e Add/Cntl e CCU MCU r DMA F 2 Mem Clocks I C DLL I2C PCIU IRQs Clock In EPIC PLL PCI Clocks ATU Arbiter FO Buffer Timers PCI Bus REQ/GNT OSC For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. PCI bus and contains a PCI bus arbitration unit which Other Embedded Features reduces the need for an equivalent external unit, thus •Two-channel integrated DMA controller reducing the total system complexity and cost. - Supports direct or chaining modes -Scatter gather MULTIPROCESSOR AND LOCAL BUS SLAVE SUPPORT - Interrupt on completed segment, chain, and error The MPC107 supports a programmable interface to - Local to local memory microprocessors implementing the PowerPC architecture - PCI to PCI memory operating at bus frequencies up to 100 MHz. The MPC107 - PCI to local memory processor interface allows for a variety of system - Local to PCI memory configurations by providing support for a second processor •Message Unit and a local bus slave. - Intelligent Input/Output (I2O) Message Controller -Two door-bell registers . - Inbound and outbound messaging registers . MPC107 MAJOR FEATURES . • Inter-Integrated Circuit (I2C) Controller Memory Interface c - Full master/slave support • High-bandwidth (32-bit/64-bit) data bus up to 100 MHz n •Embedded programmable interrupt controller (EPIC) I •Programmable timing supporting either DRAM (FPM, EDO) - Five hardware interrupts (IRQs) or 16 serial interrupts , or SDRAM r - Four programmable timers • Supports one to eight banks – 4-, 16-, 64-, 128-, and/or o • Integrated PCI bus and SDRAM clock generation t 256-bit DRAMs or SDRAMs •Programmable memory and PCI bus drivers c •1 GB of RAM space, 144 MB of ROM space •Debug Features u • 8-, 32-, or 64-bit ROM/Flash ROM d -Watchpoint monitor • PortX: 8-, 32-, or 64-bit general-purpose I/O port uses ROM n - Memory attribute and PCI attribute signals controller interface with address strobe o - JTAG/COP – Common On-board Processor for • Supports parity, read-modify-write, or error-correcting c in-circuit hardware debugging i code (ECC) - IEEE 1149.1-compliant, JTAG boundary-scan m Processor Interface interface e •Processor bus frequency up to 100 MHz • 503-pin ball grid array (BGA) package S • 64-bit or 32-bit data bus and 32-bit address bus Power Management •SMP support for a second processor e • Four levels of power reduction–doze, nap, sleep, and l • Full memory coherency supported, integrated arbiter, and suspend a slave peripheral support • Fully static, internal logic states preserved during all c • Supports MPC6xx, MPC7xx, and MPC74xx processors s power modes PCI Interface e • Compliant with PCI specification, revision 2.1 e r • 32-bit PCI interface operates up to 66 MHz CONTACT INFORMATION F • 5.0V compatible For more information on Motorola processors, point your • Read and write buffers to improve PCI performance Web browser to: http://motorola.com/smartnetworks • Selectable big- or little-endian operation For all other inquiries about Motorola products, please • PCI interface can be configured as host or agent, allowing contact the Motorola Customer Response Center at: multiple MPC107 chips on same PCI bus Phone: 800-521-6274 or •Arbiter supports up to five other PCI devices http://www.motorola.com/semiconductors • Parity support MOTOROLA and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2002. MPC107FACT/D For MoreRev.2 Information On This Product, Go to: www.freescale.com.