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Tricore™ Tricore™ V1.6 Microcontrollers User Manual

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Tricore™ Tricore™ V1.6 Microcontrollers User Manual TriCore™ 32-bit TriCore™ V1.6 Core Architecture 32-bit Unified Processor Core User Manual (Volume 1) V1.0, 2012-05 Microcontrollers Edition 2012-05 Published by Infineon Technologies AG 81726 Munich, Germany © 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TriCore™ 32-bit TriCore™ V1.6 Core Architecture 32-bit Unified Processor Core User Manual (Volume 1) V1.0, 2012-05 Microcontrollers TriCore™ V1.6 32-bit Unified Processor Core TriCore™ V1.6 User Manual (Volume 1) Revision History: V1.0 2012-05 Page Subjects (major changes since last revision) v1.0 TC1.6 First release Trademarks TriCore™ is a trademark of Infineon Technologies AG. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of our documentation. Please send your proposal (including a reference to this document) to: [email protected] User Manual (Volume 1) R-1 V1.0, 2012-05 TriCore™ V1.6 32-bit Unified Processor Core Table of Contents Table of Contents 1 Architecture Overview . 1-1 1.1 Introduction . 1-1 1.1.1 Feature Summary . 1-1 1.2 Programming Model . 1-2 1.2.1 Architectural Registers . 1-2 1.2.2 Data Types . 1-3 1.2.3 Memory Model . 1-3 1.2.4 Addressing Modes . 1-3 1.3 Tasks and Contexts . 1-3 1.4 Interrupt System . 1-4 1.4.1 Interrupt Priority . 1-4 1.5 Trap System . 1-5 1.6 Protection System . 1-5 1.7 Core Debug Controller . 1-6 1.8 TriCore Coprocessor Interface . 1-6 2 Programming Model . 2-1 2.1 Data Types . 2-1 2.1.1 Boolean . 2-1 2.1.2 Bit String . 2-1 2.1.3 Byte . 2-1 2.1.4 Signed Fraction . 2-1 2.1.5 Address . 2-1 2.1.6 Signed and Unsigned Integers . 2-1 2.1.7 IEEE-754 Single-Precision Floating-Point Number . 2-2 2.2 Data Formats . 2-2 2.2.1 Alignment Requirements . 2-4 2.2.2 Byte Ordering . 2-5 2.3 Memory Model . 2-6 2.4 Semaphores and Atomic Operations . 2-7 2.5 Addressing Modes . 2-7 2.5.1 Absolute Addressing . 2-8 2.5.2 Base + Offset Addressing . 2-8 2.5.3 Pre-Increment and Pre-Decrement Addressing . 2-8 2.5.4 Post-Increment and Post-Decrement Addressing . 2-8 2.5.5 Circular Addressing . 2-9 2.5.6 Bit-Reverse Addressing . 2-11 2.5.7 Synthesized Addressing Modes . 2-12 3 General Purpose and System Registers . 3-1 3.1 General Purpose Registers (GPRs) . 3-2 3.2 Program State Information Registers . 3-4 3.3 Stack Management Registers . 3-10 3.4 Compatibility Mode Register (COMPAT) . 3-15 3.5 Access Control Registers . 3-16 3.5.1 BIST Mode Access Control Register (BMACON) . 3-16 3.6 Interrupt Registers . 3-18 3.7 Memory Protection Registers . 3-18 3.8 Trap Registers . 3-18 3.9 Memory Configuration Registers . 3-18 User Manual (Volume 1) L-1 V1.0, 2012-05 TriCore™ V1.6 32-bit Unified Processor Core Table of Contents 3.10 Core Debug Controller Registers . 3-18 3.11 Floating Point Registers . 3-18 3.12 Accessing Core Special Function Registers (CSFRs) . 3-18 4 Tasks and Functions . 4-1 4.1 Context Types . ..
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