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Definition of Terms Introduction Trap Are a Mechanism To Eidgenössische Definition of Terms Technische Hochschule Zürich Interrupt: Asynchronous interruption of the instruction flow Programming in Systems Caused by external event! (37-023) Hit program execution in Programming in Assembler «between» 2 Instructions Basics of Operating Systems Exception: Unexpected event during Models of Computer Architecture program execution (division by zero, page fault) Lecturer today: Prof. Thomas M. Stricker Hits «during» an instruction Text-/Reference-Books: Trap: Software generated Inter- R.P.Paul: SPARC Architecture... and C rupt Sun SPARC V8 Manual and K&R C Reference Caused by an exception or by an explicit trap instruction Topics of Today: (e.g. for a system call) • Traps, Exceptions and Supervisor Mode Supervisor Privileged execution mode • SPARC V8 Trap Model Mode: in contrast to User Mode • Traps in tkisem System Calls, Interrupt-, • Register Window Trap-Handlers Exception- and Traphandler execute in supervisor mode. 9/14.1.02 - 1 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 2 37-023 Systemprogrammierung © Alonso/Stricker Introduction Trap are a mechanism to... Standard library in C (libc.a) provides ... avoid programming mistakes with sys- two different kind of functions: tem resources. • pure library functions ... share common system resources in a fair way under OS control. • self contained code (sin, printf...) ... prevent access to protected memory • «visible» execution in user mode. segments. • examination in single-step mode of ... catch Instructions which would lead to the debugger possible. error conditions and inconsistent sys- • glue code to system calls tem state (z.B. Division by 0, Window- (read, write, open, close...) Overflow). • «invisible» execution ➜ Two modes of execution: Supervisor and User Mode • call some code in the operating system (Trap) ➜ Traps: • execute in supervisor mode Mechanism to get into/return from supervisor mode. • very hard to examine (kernel debugger or simulator required) Mechanism to jump into OS code and to handle exceptions and Why are there two categories? interrupts. 9/14.1.02 - 3 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 4 37-023 Systemprogrammierung © Alonso/Stricker User and Supervisor Mode Alternate Address Space Instr. User Mode: • address space identifiers (ASI): • Access only to the text- and data- ASI Memory Segment segment of your own process. 0x08 User Text • Limited instruction set - only regular 0x09 Supervisor Text instructions. 0x0A User Data 0x0B Supervisor Data • Limited access to system status registers. ➜normal ld and st affect ASI 0x0A or 0x0B depending on mode Supervisor Mode: • load/store alternate space instructions: • Unlimited access to memory segments: • load and store to alternate memory Instruction Meaning (AS=alternate space) ldsba/stba ld/st signed byte from AS • load and store to I/O devices ldsha/stha ld/st signed halfword from AS • load and store to code segments lduba/stba ld/st unsigned byte from AS (needed by operating system). lduha/stha ld/st unsigned halfword from AS • system tables lda/sta ld/st from AS • Privileged Instructions ldda/stda ld/st double word from AS • access to several status registers ➜lda [address]asi, rd • access to I/O-devices (if not mem.) lda [0x0800]0x09, %l3 9/14.1.02 - 5 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 6 37-023 Systemprogrammierung © Alonso/Stricker Trap Trap Types • Branch to operating system code to • precise traps (synchronous traps): carry out certain functions. Trap/exception is raised before the cor- responding instruction has cause any • Program execution transferred from effect to the system state. user code to systems code. • deferred trap (asynchronous traps): • Trap handler runs in supervisor mode. Trap/exception is raised later, after the • State of the machine (CPU) will be save «trapping» instruction has had any and restore upon return to user code effects - eventually even many cycles (return from trap instruction, rett) later, but still before the next instruction had any effects. • Operating system provides different rou- tines to handle the different trap instruc- • interrupting trap tions/conditions Trap/exception is raised by an (external) (trap handler) interrupts or by an exception, of an instruction that is executed earlier. • txx is a nondelayed branch: CWP-- • Interrupt requests can be handled like traps although they are caused by exter- nal events. 9/14.1.02 - 7 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 8 37-023 Systemprogrammierung © Alonso/Stricker Status Registers of the Processor Processor State Register (PSR) icc PIL S CWP ET EF PS • Y-Reg. for Multiplication and Division: 31 23 20 1211 87654 0 ➜ read and write with rdy, wry in user mode. icc: Condition Code Flags • PC and nPC: EF: indicates FP-Coprocessor available. ➜ read and write is implicit (jmpl, ret...) in user mode. PIL: Level of Interrupts that will be cur- rently be accepted by processor • PSR Processor State Register: ➜ read and write only in the S: Supervisor mode flag supervisor mode (%psr, rdpsr, PS: Bit to save mode before the execu- wrpsr) tion of the last trap. • WIM Window Invalid Mask Register: ET: enable trap: ET == 1 ➜ read and write only in the Held to zero during trap, ET == 0 supervisor mode (%wim, rdwim, wrwim) CWP: Current Window Pointer Bits 31-23 contain the imple- • TBR Trap Base Register: ➜ mentation and version of the read and write only in the CPU (hard wired) supervisor mode (%tbr, rdtbr, wrtbr) Bits 19-14 are always 0 9/14.1.02 - 9 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 10 37-023 Systemprogrammierung © Alonso/Stricker Window Invalid Mask (WIM) Trap Base Register (TBR) • k Flags for the representation of the k TBA tt zero register sets implemented (2≤k≤32) 31 1211 4 3 0 • WIM[n] indicates the status of the regis- TBA: trap base address, upper part of the ter sets n: base address of the trap table. 1: Register set has invalid contents tt: trap type, 256 possible traps, offset 0: Register set has valid contents into the trap table. • Test upon save, restore oder zero:last four bits are always zero. rett against WIM[CWP]: • WIM[CWP]==1 • TBR puts the bits TBA and tt together save: ⇒ Window into a destination address for the CALL. Overflow • The zero-bits make the subsequent trap restore, ⇒ Window entry points spaced 16 bytes apart. rett: Underflow Table can hold the first 4 instructions of • WIM[CWP]==0 ⇒ Window valid the trap handlers: • Flags of unimplemented windows read handler_vect: as 0es and can not be written. set handler, %l3 jmpl %l3, %r0 • wrwim with all ones followed by rdwim indicates the implemented registers with nop a one. handler: ... 9/14.1.02 - 11 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 12 37-023 Systemprogrammierung © Alonso/Stricker FP Processor Status Reg. (FSR) Priorities of Traps- and Interrupts RD TEM ftt fcc cexc • 0x80 - 0xFF 3130 27 23 16 14 1110 4 0 Software- Traps RD: Field specifies rounding mode: 0: Nearest Number 2: +∞ • 0x00 - 0x7F 1: towards 0 3: -∞ Hardware- Traps fcc: floating point cond. code, is set by (partially FP-compare instructions. used in cur- cexc:current exception field, set after rent impl- every FP-instruction (invalid op, mentations) overflow, underflow, division by zero, result inexact) TEM: trap enable mask, switches FP- traps on and off. After each com- pleted FP-instruction TEM OR cexc will be examined: TEM OR cexc != 0 ⇒ FP-Trap ftt: floating point trap type (no trap, trap in cexc, unfinished, unimplemented, invalid register) 9/14.1.02 - 13 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 14 37-023 Systemprogrammierung © Alonso/Stricker Priorities of Traps- and Interrupts Steps executed with a trap •If ET=1, traps will be handler according If ET == 1: to priorities in the table before. 1. ET = 0 • If ET=0, all interrupts are ignored and disable traps any further trap will reset the machine. 2. PS = S • Priority decides about the order in save current execution mode which concurrent interrupt/traps are 3. S = 1 handled. switch to supervisor mode • Interrupts have smaller priorities than 4. CWP = CWP-1 mod NWINDOWS exceptions, i.e. they have higher trap advance register window without numbers (17-31) test for window overflow • Interrupts on IRL 1 (Interrupt Request 5. %l1(%r17) = PC; %l2(%r18) = nPC Level) have smallest priority save trapped program counters • Only IRL > PIL (processor interrupt 6. tt = trap_type level) will be handled: write tt field ➜ Mechanism to mask-out interrupts 7. PC = TBR; nPC = TBR+4 ➜ IRL 15 is unmaskable transfer control into trap table (Reset Trap: PC = 0; nPC = 4) • It is expected, that Interrupts with lower priority will stick until they are handled. (if not they can be missed) 9/14.1.02 - 15 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 16 37-023 Systemprogrammierung © Alonso/Stricker Steps executed with a trap Return from a trap handler Optional: rett address • %l0(%r16) = %psr 1. CWP = CWP+1 mod NWINDOWS save PSR if trap handler changes it advance register window temporarily and it must be restored. 2. nPC = address • If the local register %l3-%l7 are not initiate delayed transfer to address sufficient to program the trap handler of return from trap instruction and WIM[CWP]==1 the register window 3. S = PS must be saved explicitly/manually. restore previous mode of execution • if trap is an interrupt: PSR must be 4. ET = 1 saved, PIL set, ET=1 and the Window re-enable traps must be saved in any case (➜ traps) Notes: If ET == 0: • eventually restore PSR, PIL, Regis- ter Window • Interrupts will be ignored. • Instruction before rett must be • Further traps/exception conditions will jmpl, otherwise the instruction result in a reset of the machine. after rett will be read from the • Deferred traps, which are caused by an supervisor memory while the exe- instruction that started execution still cution is already in used mode.
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