Eidgenössische Definition of Terms Technische Hochschule Zürich : Asynchronous interruption of the instruction flow Programming in Systems Caused by external event! (37-023) Hit program execution in Programming in Assembler «between» 2 Instructions Basics of Operating Systems Exception: Unexpected event during Models of Computer Architecture program execution (division by zero, page fault) Lecturer today: Prof. Thomas M. Stricker Hits «during» an instruction Text-/Reference-Books: Trap: Software generated Inter- R.P.Paul: SPARC Architecture... and C rupt Sun SPARC V8 Manual and K&R C Reference Caused by an exception or by an explicit trap instruction Topics of Today: (e.g. for a ) • Traps, Exceptions and Supervisor Mode Supervisor Privileged execution mode • SPARC V8 Trap Model Mode: in contrast to User Mode • Traps in tkisem System Calls, Interrupt-, • Register Window Trap-Handlers Exception- and Traphandler execute in supervisor mode.

9/14.1.02 - 1 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 2 37-023 Systemprogrammierung © Alonso/Stricker

Introduction Trap are a mechanism to...

Standard library in C (libc.a) provides ... avoid programming mistakes with sys- two different kind of functions: tem resources. • pure library functions ... share common system resources in a fair way under OS control. • self contained code (sin, printf...) ... prevent access to protected memory • «visible» execution in user mode. segments. • examination in single-step mode of ... catch Instructions which would lead to the debugger possible. error conditions and inconsistent sys- • glue code to system calls tem state (z.B. Division by 0, Window- (read, write, open, close...) Overflow). • «invisible» execution ➜ Two modes of execution: Supervisor and User Mode • call some code in the (Trap) ➜ Traps: • execute in supervisor mode Mechanism to get into/return from supervisor mode. • very hard to examine (kernel debugger or simulator required) Mechanism to jump into OS code and to handle exceptions and Why are there two categories? .

9/14.1.02 - 3 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 4 37-023 Systemprogrammierung © Alonso/Stricker

User and Supervisor Mode Alternate Address Space Instr.

User Mode: • address space identifiers (ASI): • Access only to the text- and data- ASI Memory Segment segment of your own . 0x08 User Text • Limited instruction set - only regular 0x09 Supervisor Text instructions. 0x0A User Data 0x0B Supervisor Data • Limited access to system status registers. ➜normal ld and st affect ASI 0x0A or 0x0B depending on mode Supervisor Mode: • load/store alternate space instructions: • Unlimited access to memory segments: • load and store to alternate memory Instruction Meaning (AS=alternate space) ldsba/stba ld/st signed byte from AS • load and store to I/O devices ldsha/stha ld/st signed halfword from AS • load and store to code segments lduba/stba ld/st unsigned byte from AS (needed by operating system). lduha/stha ld/st unsigned halfword from AS • system tables lda/sta ld/st from AS • Privileged Instructions ldda/stda ld/st double word from AS • access to several status registers ➜lda [address]asi, rd • access to I/O-devices (if not mem.) lda [0x0800]0x09, %l3

9/14.1.02 - 5 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 6 37-023 Systemprogrammierung © Alonso/Stricker

Trap Trap Types

• Branch to operating system code to • precise traps (synchronous traps): carry out certain functions. Trap/exception is raised before the cor- responding instruction has cause any • Program execution transferred from effect to the system state. user code to systems code. • deferred trap (asynchronous traps): • Trap handler runs in supervisor mode. Trap/exception is raised later, after the • State of the machine (CPU) will be save «trapping» instruction has had any and restore upon return to user code effects - eventually even many cycles (return from trap instruction, rett) later, but still before the next instruction had any effects. • Operating system provides different rou- tines to handle the different trap instruc- • interrupting trap tions/conditions Trap/exception is raised by an (external) (trap handler) interrupts or by an exception, of an instruction that is executed earlier. • txx is a nondelayed branch: CWP-- • Interrupt requests can be handled like traps although they are caused by exter- nal events.

9/14.1.02 - 7 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 8 37-023 Systemprogrammierung © Alonso/Stricker

Status Registers of the Processor Processor State Register (PSR)

icc PIL S CWP ET EF PS • Y-Reg. for Multiplication and Division: 31 23 20 1211 87654 0 ➜ read and write with rdy, wry in user mode. icc: Condition Code Flags • PC and nPC: EF: indicates FP-Coprocessor available. ➜ read and write is implicit (jmpl, ret...) in user mode. PIL: Level of Interrupts that will be cur- rently be accepted by processor • PSR Processor State Register: ➜ read and write only in the S: Supervisor mode flag supervisor mode (%psr, rdpsr, PS: Bit to save mode before the execu- wrpsr) tion of the last trap. • WIM Window Invalid Mask Register: ET: enable trap: ET == 1 ➜ read and write only in the Held to zero during trap, ET == 0 supervisor mode (%wim, rdwim, wrwim) CWP: Current Window Pointer Bits 31-23 contain the imple- • TBR Trap Base Register: ➜ mentation and version of the read and write only in the CPU (hard wired) supervisor mode (%tbr, rdtbr, wrtbr) Bits 19-14 are always 0

9/14.1.02 - 9 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 10 37-023 Systemprogrammierung © Alonso/Stricker

Window Invalid Mask (WIM) Trap Base Register (TBR)

• k Flags for the representation of the k TBA tt zero register sets implemented (2≤k≤32) 31 1211 4 3 0 • WIM[n] indicates the status of the regis- TBA: trap base address, upper part of the ter sets n: base address of the trap table. 1: Register set has invalid contents tt: trap type, 256 possible traps, offset 0: Register set has valid contents into the trap table. • Test upon save, restore oder zero:last four bits are always zero. rett against WIM[CWP]: • WIM[CWP]==1 • TBR puts the bits TBA and tt together save: ⇒ Window into a destination address for the CALL. Overflow • The zero-bits make the subsequent trap restore, ⇒ Window entry points spaced 16 bytes apart. rett: Underflow Table can hold the first 4 instructions of • WIM[CWP]==0 ⇒ Window valid the trap handlers: • Flags of unimplemented windows read handler_vect: as 0es and can not be written. set handler, %l3 jmpl %l3, %r0 • wrwim with all ones followed by rdwim indicates the implemented registers with nop a one. handler: ...

9/14.1.02 - 11 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 12 37-023 Systemprogrammierung © Alonso/Stricker FP Processor Status Reg. (FSR) Priorities of Traps- and Interrupts

RD TEM ftt fcc cexc • 0x80 - 0xFF 3130 27 23 16 14 1110 4 0 Software- Traps RD: Field specifies rounding mode: 0: Nearest Number 2: +∞ • 0x00 - 0x7F 1: towards 0 3: -∞ Hardware- Traps fcc: floating point cond. code, is set by (partially FP-compare instructions. used in cur- cexc:current exception field, set after rent impl- every FP-instruction (invalid op, mentations) overflow, underflow, division by zero, result inexact) TEM: trap enable mask, switches FP- traps on and off. After each com- pleted FP-instruction TEM OR cexc will be examined: TEM OR cexc != 0 ⇒ FP-Trap ftt: floating point trap type (no trap, trap in cexc, unfinished, unimplemented, invalid register)

9/14.1.02 - 13 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 14 37-023 Systemprogrammierung © Alonso/Stricker

Priorities of Traps- and Interrupts Steps executed with a trap

•If ET=1, traps will be handler according If ET == 1: to priorities in the table before. 1. ET = 0 • If ET=0, all interrupts are ignored and disable traps any further trap will reset the machine. 2. PS = S • Priority decides about the order in save current execution mode which concurrent interrupt/traps are 3. S = 1 handled. switch to supervisor mode • Interrupts have smaller priorities than 4. CWP = CWP-1 mod NWINDOWS exceptions, i.e. they have higher trap advance register window without numbers (17-31) test for window overflow • Interrupts on IRL 1 (Interrupt Request 5. %l1(%r17) = PC; %l2(%r18) = nPC Level) have smallest priority save trapped program counters • Only IRL > PIL (processor interrupt 6. tt = trap_type level) will be handled: write tt field ➜ Mechanism to mask-out interrupts 7. PC = TBR; nPC = TBR+4 ➜ IRL 15 is unmaskable transfer control into trap table (Reset Trap: PC = 0; nPC = 4) • It is expected, that Interrupts with lower priority will stick until they are handled. (if not they can be missed)

9/14.1.02 - 15 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 16 37-023 Systemprogrammierung © Alonso/Stricker Steps executed with a trap Return from a trap handler Optional: rett address • %l0(%r16) = %psr 1. CWP = CWP+1 mod NWINDOWS save PSR if trap handler changes it advance register window temporarily and it must be restored. 2. nPC = address • If the local register %l3-%l7 are not initiate delayed transfer to address sufficient to program the trap handler of return from trap instruction and WIM[CWP]==1 the register window 3. S = PS must be saved explicitly/manually. restore previous mode of execution • if trap is an interrupt: PSR must be 4. ET = 1 saved, PIL set, ET=1 and the Window re-enable traps must be saved in any case (➜ traps) Notes: If ET == 0: • eventually restore PSR, PIL, Regis- ter Window • Interrupts will be ignored. • Instruction before rett must be • Further traps/exception conditions will jmpl, otherwise the instruction result in a reset of the machine. after rett will be read from the • Deferred traps, which are caused by an supervisor memory while the exe- instruction that started execution still cution is already in used mode. with ET == 1 will also be ignored. • jmpl sets PC, rett sets the nPC

9/14.1.02 - 17 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 18 37-023 Systemprogrammierung © Alonso/Stricker

Options for returning from a trap Example User Program

• Repetition/retry of the instruction that Input of a digit n and output of n+5 caused the trap: .text jmpl %l1, %g0 !old PC start: ta 2 rett %l2 !old nPC sub %r8, ’0’, %r8 pc -> jmplnpc -> rett pc -> rettnpc -> old PC add %r8, 5, %r8 pc -> old PCnpc -> old nPC cmp %r8, 9 • Return to the Instruction after the ble one_dg instruction that caused the trap: nop jmpl %l2, %g0 !old nPC mov %r8, %r7 rett %l2+4 !old nPC+4 pc -> jmplnpc -> rett set ’1’, %r8 pc -> rettnpc -> old nPC ta 1 pc -> old nPCnpc -> old nPC+4 sub %r7, 10, %r8 Notes: one_dg: • both options of the return jump make use of the so called delayed add %r8, ’0’, %r8 control transfer couple. ta 1 • rett is a privileged instruction ta 0

9/14.1.02 - 19 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 20 37-023 Systemprogrammierung © Alonso/Stricker Trap handlers in ROM – getc Trap handlers in ROM – putc

.text .text .align 8 .align 8 getc_vect: putc_vect: set getc, %l3 set putc, %l3 jmpl %l3, %r0 jmpl %l3, %r0 nop nop getc: putc: set 0xffffffff, %l3 set CONOUT, %l0 set CONIN, %l0 st %i0, [%l0] lb0: ld [%l0], %i0 ! return to instr. cmp %i0, %l3 ! following the trap be lb0 jmpl %r18, %r0 nop rett %r18+4

! return to instr. ! following the trap jmpl %r18, %r0 rett %r18+4

9/14.1.02 - 21 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 22 37-023 Systemprogrammierung © Alonso/Stricker

Traps to I/O syscalls in TKISEM What happens exactly at • Examination/programming of instruc- program start? tions in user-/supervisor text segment including single step execution. The operating system carries out the following operations at program start: • Trap table in the lower area of supervi- sor text (ta 0 bei 0x800). CWP and TBR • Load of the user program into user text- are preinitialized in that way. memory segment. • The standard I/O devices of the • Load of library functions, only if shared TKISEM environment are memory libraries are used (“libc.so”), not if stati- mapped in system space. cally linked (“libc.a”). CONOUT = 0x110000 [e.g. printf,sin,strcpy...] CONIN = 0x110000 HALT = 0x120000 • Collect command line arguments and TIMER = 0x130000 UARTSTATUS = 0X140000 pass them by yointer array (by shell) UARTCREG = 0x140001 UARTTXREG = 0x140002 • Call OS code stub “crt0.o” which sets UARTRXREG = 0x140003 %sp and calls entry point of program • User access is through traps main (argc,*argv[]) 0 -- terminate program tkisem: simply starts with first instruc- 1 -- putc tion and user must set %sp first. 2 -- getc (blocking version) 3 -- getc_nb (nonblocking) • Return with ret instruction to OS code 4 -- putx 5 -- getx “crt0.o” stub which terminates program. 6 -- puts tkisem: terminates with a ta 0

9/14.1.02 - 23 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 24 37-023 Systemprogrammierung © Alonso/Stricker Register Window Overflow Trap Register Window Overflow Trap

• Example with four register sets • save instruction • Starting situation: • WIM[--CWP] == 0 ⇒ okay - User in first register set (set #3) - Sets #3,#2,#1 are valid: WIM[n]==0 • Register window shift - Set #0 is invalid: WIM[0]==1 WIM Registers Stack WIM Registers Stack

in in save save 0 CWP local area 0 local area %sp %fp out out in 3 3 save 0 0 CWP local area %sp 2 2out 0 1 0 1 1 1 0in of set 3 0in of set 3 global global

9/14.1.02 - 25 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 26 37-023 Systemprogrammierung © Alonso/Stricker

Register Window Overflow Trap Register Window Overflow Trap

• save instruction • Attempt save instruction • WIM[--CWP] == 0 ⇒ okay • WIM[--CWP] == 1 ⇒ window overflow • register window shift • Overflow trap handler starts with set #0

WIM Registers Stack WIM Registers Stack

in in save save 0 local area 0 local area

out in out in 3 save 3 save 0 local area 0 local area %fp in out in out 2 save 2 save 0 CWP local area 0 local area %sp %fp 1out 1out 1 1 local %npc CWP %pc 0in of set 3 0in of set 3 global global

9/14.1.02 - 27 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 28 37-023 Systemprogrammierung © Alonso/Stricker Register Window Overflow Trap Register Window Overflow Trap

• Trap handler: • Trap handler: • CWP-- (save again) • rotate WIM • CWP points to set #3 • CWP+2 (restore, rett) •save %lx, %ix to mem[%sp] • CWP just as before trap on set #1

WIM Registers Stack WIM Registers Stack

in in 3 in 3 0 CWP local local 3 1 local 3 %sp out in out in 3 save 3 save 0 local area 0 local area %fp in out in out 2 save 2 save 0 local area 0 CWP local area %sp 1out 1out 1 local %npc 0 local %npc %pc %pc 0in of set 3 0 global global

9/14.1.02 - 29 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 30 37-023 Systemprogrammierung © Alonso/Stricker

Register Window Overflow Trap Overflow Handler aus tkisem

wover_vect: • save instruction set wover, %l3 jmpl %l3, %r0 • WIM[--CWP] == 0 ⇒ now okay nop wover: • Register window shift, work in set #0 !save the oldest set of user registers !to the appropriate stack frame save !use the oldest register set WIM Registers Stack stda %l0, [%sp]10 !save local regs add %sp, 8, %l0 stda %l2, [%l0]10 out of set 0 inc 8, %l0 in 3 stda %l4, [%l0]10 1 local 3 ... stda %i0, [%l0]10 !save in regs out in inc 8, %l0 stda %i2, [%l0]10 3 save 0 local ... area stda %i6, [%l0]10 in out !make this the invalid register set mov %psr, %l2 2 save and %l2, 0x1f, %l2 !get CWP from PSR 0 local area set 1, %l3 %fp sll %l3, %l2, %l3 out in mov %l3, %wim !set WIM mask 1 save nop !delay for three cycles 0 CWP local area nop nop %sp out !restore original reg. set and return 0 !re-execute save restore global jmpl %r17, %g0 rett %r18

9/14.1.02 - 31 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 32 37-023 Systemprogrammierung © Alonso/Stricker Register Window Underflow Trap Register Window Underflow Trap

• Example with four register sets • Attempt restore instruction • Situation before restore instruction • WIM[++CWP] == 1 ⇒ win. underflow - user in register set #2 - sets #2,#1,#0 are valid: WIM[n]==0 • Overflow trap handler starts in set #1 - set #3 is invalid: WIM[3]==1 WIM Registers Stack WIM Registers Stack

out of set 0 out of set 0 in 3 in 3 1 local 3 1 local 3 %fp %fp out in out in 3 save 3 save 0 CWP local area 0 local area %sp %sp 2out 2out 0 0 CWP local %npc 1 1%pc 0 0 0out 0out global global

9/14.1.02 - 33 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 34 37-023 Systemprogrammierung © Alonso/Stricker

Register Window Underflow Trap Register Window Underflow Trap • Trap handler: • Trap handler: • WIM[CWP+3 mod NWINDOWS]=1 • Register set 3 restored new invalid set (set #0) • restore, restore (CWP++) • CWP-- (save, save, rett) • Load of %lx, %ix from mem[%sp] • CWP just as before trap on set 2 WIM Registers Stack WIM Registers Stack

in in save save 0 CWP local area 0 local area %sp %fp out in out in 3 save 3 save 0 local area 0 CWP local area %sp 2out 2out 0 local %npc 0 local %npc 1%pc 1%pc 1 1 0in of set 3 0in of set 3 global global

9/14.1.02 - 35 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 36 37-023 Systemprogrammierung © Alonso/Stricker Register Window Underflow Trap Underflow Handler in tkisem wunder_vect: set wunder, %l3 • restore instruction jmpl %l3, %r0 nop • WIM[++CWP] == 0 ⇒ is okay now wunder: !two registers sets from underflowed set !open and restore underflowed set set nreg_sets, %l0 • Register window shift, work in set #3 ld [%l0], %l0 mov %psr, %l6 and %l6, 0x1f, %l5 !get CWP from PSR WIM Registers Stack add %l5, 3, %l5 cmp %l0, %l5 bgt 1f in nop save sub %l5, %l0, %l5 0 CWP local area 1: !%l5 holds the cwp we want to make invalid %sp set 1, %l7 out sll %l7, %l5, %l7 3 mov %l7, %wim !adjust WIM nop !wait until CWP has been updated 0 nop nop restore !change to underflowed reg. set 2 restore 0 !restore the locals and inputs add %sp, 8, %l0 ldda [%l0]10, %l2 1 inc 8, %l0 ... 1 ldda [%sp]10, %l0 save !back to original registers set 0in of set 3 save !return -- re-execute restore instruction global jmpl %r17, %g0 rett %r18

9/14.1.02 - 37 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 38 37-023 Systemprogrammierung © Alonso/Stricker

Similarities Trap Table – switch Similarities Trap Table – switch

TBA tt zero Switch Statement (Language C): 31 1211 4 3 0 • Branch based on table. • Execution of Instructions at target. Difference: • Trap table: Always 4 instructions • Switch: Varying number of instr. Baseadress Trap-Junmptable switch-Beispiel (C-Syntax): switch (i + 3) { case 1: i += 1; First four Instruktions of trap tt break; case 2: i += 2; break; case 15: i += 15; case 3: i += 3; break; case 4: i += 4; case 6: i += 6; Handling of a trap (Hardware): break; • Unconditional jump into table. case 5: i += 5; break; • Execution of instructions in table. default: i--; }

9/14.1.02 - 39 37-023 Systemprogrammierung © Alonso/Stricker 9/14.1.02 - 40 37-023 Systemprogrammierung © Alonso/Stricker