R06 R06 A Survey of Enabling Technologies in Successful Consumer Digital Imaging Products

R. Fontaine, TechInsights1

 The early trend for both types of masked PDAF pixels was Abstract—The image quality and customized functionality of to deploy them within a relatively small central region of the small- mobile camera systems continues to bring true active pixel array, or as linear arrays (periodic rows of product differentiation to . Recently, phase PDAF pixel pairs). Today, masked pixel PDAF arrays in detection autofocus (PDAF) pixels, pixel isolation structures, marquee products occupy more than 90% of the host active chip stacking and other technology elements have contributed to a remarkable increase in mobile camera performance. pixel arrays and display a trend of increasing density Other imaging applications continue to benefit from small- generation-over-generation. pixel development efforts as foundries and IDMs transfer leading edge technology to active pixel arrays for emerging A. Masked PDAF in Front-Illuminated CCDs imaging and sensing applications. Hybrid PDAF systems were introduced to the camera market by a FujiFilm press release in July 2010. The Index Terms—CMOS , through silicon via, FinePix Z800EXR featured a hybrid AF system with a Cu-Cu hybrid bonding, direct bonding interconnect, stated AF performance of 0.158 s [1]. This front-illuminated homogeneous wafer-to-wafer bonding (oxide bonding), stacked chip, phase detection autofocus, image signal processor charge-coupled device (CCD) imager, fabricated by Toshiba, employed metal half-masks in two of 32 pixels I. INTRODUCTION within a rectangular PDAF subarray occupying the central ~7% of the active pixel array [2]. In the case of the CCD MOS image sensor (CIS) pixel scaling has nearly structure, the W-based shielding metal, already in use in ended, and indeed some camera conventional CCDs, was patterned to form PDAF half- development teams have reversed the pixel scaling race in masks just above the photodiode (PD) region. favor of larger pixels with increased full well capacity. Nevertheless, the pace of image sensor technology B. Masked PDAF in Front-Illuminated CMOS development seems to be increasing. The era of chip Half-masked front-illuminated CMOS PDAF pixels were stacking is well underway and offers increased flexibility in first noted in the Nikon V1, announced in September 2011 terms of manufacturing and systems partitioning. The state- [3]. The Aptina-sourced chip featured PDAF pixels of-the-art smartphone camera chips feature a pixel pitch implemented as nine linear arrays configured as evenly down to 1.0 µm and up to 23 MP resolution. Dual cameras spaced rows across the active pixel array [4]. The PDAF are becoming popular, including the availability of products pixel row segments were all green channel pixels and the featuring dual front- and rear-facing cameras. PDAF aperture mask was implemented in metal 1 (Cu). Alternating systems now employ three distinct and complementary pixels within the row segment featured right/left masks. techniques: contrast, phase, and laser-assisted ranging. At Variable aperture masks emerged in 2012 starting with the chip level, evolutions in direct bond interconnect (DBI) Canon’s Hybrid CMOS AF system in the EOS 650D [5]. and deep trench isolation (DTI) are facilitating the The EOS 650D is the first known instance of the standard performance gains realized by recent stacked imaging chips. Bayer RGB pattern augmented with clear replacement filters in the PDAF array [6]. Clear PDAF pixels were II. PDAF implemented in the selected red and blue channels. Uniform Conventional, passive AF systems relied on contrast-only vertical aperture masks were used in the metal 2 (Al) techniques until locally masked PDAF pixel apertures were interconnect for all PDAF pixels, presumably to reduce the added to active pixel arrays to facilitate hybrid (contrast and fill factor of the clear channel pixels. At least six different phase) AF systems. It is a fortunate circumstance that nearly widths of metal 1 horizontal aperture masks were noted in at all observed masked PDAF pixels to date require little least six different PDAF pair layouts within a central additional processing during chip fabrication, only the “+”-shaped region occupying ~7% of the active pixel array. repurposing of existing structures to serve as PDAF pixel Front-illuminated pixel aperture masking for PDAF has aperture masks. been noted in use in chips produced by Aptina (ON Examples of both half-masking, in which neighboring Semiconductor), Canon, Panasonic, , and Sony. PDAF pixel pairs are simply 50% masked, and variable The preference of interconnect level for aperture masking pixel aperture window sizes have been found in use. varies by manufacturer and has been noted at all levels of pixel back-end-of-line (BEOL) interconnect. Recently, a

Submitted April 14, 2017. Sony chip sourced from the Olympus OM-D E-M1 Mark II 1Ray Fontaine, Senior Technology Analyst, Technology Intelligence was found to use a local W shielding metal just above the Division, TechInsights, 1891 Robertson Road, Suite 500, Ottawa, ON, PD region [7]. K2H 5B7, Canada, email: [email protected]

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C. Masked PDAF in Back-Illuminated CMOS pattern and a green replacement filter in the neighboring Pixel aperture masking techniques for back-illuminated blue position. Two of 64 pixels in an 8x8 block use this lens A Survey of Enabling Technologies in PDAF pixels emerged in 2013, and were first observed in structure and these blocks are distributed across ~95% of the use in the Fujifilm X20 [8]. The chip, fabricated by Toshiba, active pixel array. A similar implementation of 1x2 Successful Consumer Digital Imaging Products employed an X-Trans CMOS II color filter array. The microlenses were found in use in the Sony IMX398 from the rectangular PDAF subarray covered ~13% of the active R9s and have been dubbed “Dual PDAF” [17]. pixel array [9]. Two of six green channel pixels within a row Chip Pixel Pitch PDAF Pixel Sensor Type/ 1 segment were half-masked by the back aperture grid metal Year R. Fontaine, TechInsights Vendor (µm) Configuration Configuration (Al). PDAF pixels were implemented in one in four rows. Toshiba 2010 1.6 Half-mask FI CCD The first 1.0 µm generation masked, back-illuminated Aptina 2011 3.4 Half-mask FI CMOS  The early trend for both types of masked PDAF pixels was PDAF pixels were found in use in May 2016 in the Canon 2012 4.3 Variable-mask FI CMOS Abstract—The image quality and customized functionality of to deploy them within a relatively small central region of the OmniVision OV16880, fabricated by TSMC on the Canon 2013 4.1 Dual PD FI CMOS small-pixel mobile camera systems continues to bring true OmniVision PureCel Plus-S platform [10]. Back-illuminated Toshiba 2013 2.2 Half-mask BI CMOS active pixel array, or as linear arrays (periodic rows of Stacked, product differentiation to smartphones. Recently, phase Sony 2014 1.12 Half-mask PDAF pixel pairs). Today, masked pixel PDAF arrays in masked PDAF systems have been found in use in chips from BI CMOS detection autofocus (PDAF) pixels, pixel isolation structures, marquee products occupy more than 90% of the host active OmniVision, Samsung, Sony, and Toshiba. The revenue Samsung 2014 3.6 Variable-mask BI CMOS chip stacking and other technology elements have contributed market share leaders tend to prefer W metallization for Sony/ Stacked, to a remarkable increase in mobile camera performance. pixel arrays and display a trend of increasing density 2016 1.4 Dual PD generation-over-generation. aperture grid metal on back-illuminated chips, although Al Samsung BI CMOS Other imaging applications continue to benefit from small- Stacked, pixel development efforts as foundries and IDMs transfer grid/mask metal is also common. In 2015 Sony’s hybrid AF Sony 2016 1.0 Dual PDAF A. Masked PDAF in Front-Illuminated CCDs BI CMOS leading edge technology to active pixel arrays for emerging system for the Xperia Z5, incorporating masked PDAF, was Table 1. Noteworthy PDAF System Insertion Dates and Configurations imaging and sensing applications. Hybrid PDAF systems were introduced to the camera reported to have a 0.03 s AF speed [11]. market by a FujiFilm press release in July 2010. The D.Dual PD-Based Pixel PDAF III. STACKED CHIP IMAGE SENSORS Index Terms—CMOS image sensor, through silicon via, FinePix Z800EXR featured a hybrid AF system with a Cu-Cu hybrid bonding, direct bonding interconnect, stated AF performance of 0.158 s [1]. This front-illuminated Given the lossy nature of a masked PDAF system, a The development of low-temperature wafer bonding and homogeneous wafer-to-wafer bonding (oxide bonding), stacked second type of PDAF emerged in July 2013 when Canon various wafer-to-wafer interconnect techniques have been chip, phase detection autofocus, image signal processor charge-coupled device (CCD) imager, fabricated by Toshiba, employed metal half-masks in two of 32 pixels announced its Dual CMOS AF system for the EOS 70D key enablers for stacked image sensors. Two-die stacks, [12]. This new approach featured dual, front-illuminated comprising a back-illuminated CIS and mixed-signal image I. INTRODUCTION within a rectangular PDAF subarray occupying the central ~7% of the active pixel array [2]. In the case of the CCD PDs at each photosite (two PDs per pixel aperture/color signal processor (ISP), have emerged as the dominant MOS image sensor (CIS) pixel scaling has nearly structure, the W-based shielding metal, already in use in filter). While all pixels featured the same dual PD structure, configuration for leading smartphone camera chips. The CIS ended, and indeed some smartphone camera C conventional CCDs, was patterned to form PDAF half- only the central ~80% were allocated to the AF system. portion can be considered a 'dumb' chip carrying only an development teams have reversed the pixel scaling race in masks just above the photodiode (PD) region. In March 2016 Samsung announced its back-illuminated active pixel array. Most of the signal chain and digital favor of larger pixels with increased full well capacity. dual PD system (Dual Pixel) developed for the Galaxy S7 processing is partitioned onto the ISP and systems Nevertheless, the pace of image sensor technology B. Masked PDAF in Front-Illuminated CMOS smartphone [13]. These 1.4 µm generation dual PD pixels application processor. development seems to be increasing. The era of chip Half-masked front-illuminated CMOS PDAF pixels were were available as AF points across 100% of the active pixel A. Stacked Chip Fabrication Technology Trend stacking is well underway and offers increased flexibility in first noted in the Nikon V1, announced in September 2011 array. Variants of Samsung’s Dual Pixel technology were The recent manufacturing trend for back-illuminated CIS terms of manufacturing and systems partitioning. The state- [3]. The Aptina-sourced chip featured PDAF pixels implemented both in Samsung and Sony-sourced chips in chips in a stacked configuration seems to have stabilized at of-the-art smartphone camera chips feature a pixel pitch implemented as nine linear arrays configured as evenly the Galaxy S7 [14,15]. In both versions, the PD pairs were the 90/65 nm process generation. There doesn’t appear to be down to 1.0 µm and up to 23 MP resolution. Dual cameras spaced rows across the active pixel array [4]. The PDAF isolated by partial-depth back DTI (B-DTI) structures to a driver for further scaling of the CIS chip technology are becoming popular, including the availability of products pixel row segments were all green channel pixels and the reduce crosstalk within the substrate. In addition to the generation, although recently sub-65 nm processing has featuring dual front- and rear-facing cameras. PDAF aperture mask was implemented in metal 1 (Cu). Alternating conventional B-DTI structures used by the Sony variant, the been observed in 1.0 µm generation pixel structures to systems now employ three distinct and complementary pixels within the row segment featured right/left masks. Samsung version employed a 2x2 B-DTI sub-array for green facilitate narrower W aperture grid metal. Samsung’s 28 nm techniques: contrast, phase, and laser-assisted ranging. At Variable aperture masks emerged in 2012 starting with and blue channel dual PDs. high-k metal gate process is currently in use for stacked the chip level, evolutions in direct bond interconnect (DBI) Canon’s Hybrid CMOS AF system in the EOS 650D [5]. The observed dual PD systems from Canon, Samsung and ISPs [14] and the ISP scaling trend is expected to continue and deep trench isolation (DTI) are facilitating the The EOS 650D is the first known instance of the standard Sony use a standard Bayer-patterned RGB color filter array. performance gains realized by recent stacked imaging chips. Bayer RGB pattern augmented with clear replacement filters towards the latest advanced CMOS technology generations. E. Dual PDAF in the PDAF array [6]. Clear PDAF pixels were Chip Stacked CIS Stacked ISP II. PDAF It is a reasonable assumption that both masked PDAF and Year implemented in the selected red and blue channels. Uniform Vendor Foundry/Gen. Foundry/Gen. dual-PD-based systems could exhibit degraded performance Conventional, passive AF systems relied on contrast-only vertical aperture masks were used in the metal 2 (Al) Sony 2013 Sony 90 nm Sony 65 nm techniques until locally masked PDAF pixel apertures were interconnect for all PDAF pixels, presumably to reduce the in low-light conditions. In the case of masked PDAF, the Sony 2014 Sony 90 nm TSMC 40 nm added to active pixel arrays to facilitate hybrid (contrast and fill factor of the clear channel pixels. At least six different lower fill factor of partially-masked apertures results in Sony 2016 Sony 90 nm TSMC 28 nm widths of metal 1 horizontal aperture masks were noted in at photon loss, as compared to a non-masked neighbor. In the OmniVision 2015 XMC 65 nm XMC 65 nm phase) AF systems. It is a fortunate circumstance that nearly OmniVision 2016 TSMC 65 nm TSMC 65 nm all observed masked PDAF pixels to date require little least six different PDAF pair layouts within a central case of dual PD, the twin PDs would require isolation from one another and the surrounding structures. The additional Samsung 2015 Samsung 65 nm Samsung 65 nm additional processing during chip fabrication, only the “+”-shaped region occupying ~7% of the active pixel array. Samsung 28 nm Samsung 2016 Samsung 65 nm repurposing of existing structures to serve as PDAF pixel Front-illuminated pixel aperture masking for PDAF has isolation results in an overall reduced full well capacity, as HKMG compared to a single PD implemented in the same pixel ISSCC aperture masks. been noted in use in chips produced by Aptina (ON Sony 90 nm CIS* 30 nm DRAM* 40 nm ISP* 2017 Examples of both half-masking, in which neighboring Semiconductor), Canon, Panasonic, Samsung, and Sony. size. Recent back-illuminated Sony chips have been found to *announced Feb 2017 PDAF pixel pairs are simply 50% masked, and variable The preference of interconnect level for aperture masking Table 2. Noteworthy Stacked Chip CIS/ISP Configurations pixel aperture window sizes have been found in use. varies by manufacturer and has been noted at all levels of use a new type of PDAF system that could be described as pixel back-end-of-line (BEOL) interconnect. Recently, a lossless. The 1.0 µm pixel generation Exmor RS chip in the B. Wafer-to-Wafer Interconnect Apple iPhone 7 Plus used a 1x2 microlens structure over Sony was first to bring stacked CIS chips to market, Submitted April 14, 2017. Sony chip sourced from the Olympus OM-D E-M1 Mark II 1Ray Fontaine, Senior Technology Analyst, Technology Intelligence was found to use a local W shielding metal just above the two of eight pixel pairs in selected green-blue rows [16]. initially by implementing homogenous wafer-to-wafer Division, TechInsights, 1891 Robertson Road, Suite 500, Ottawa, ON, PD region [7]. The wide microlenses cover a green filter in the Bayer bonding (oxide bonding) and through-silicon-vias (TSVs) in K2H 5B7, Canada, email: [email protected]

− 21 − 2013 and later with Cu-to-Cu hybrid bonding, also known as IV. PIXEL ISOLATION STRUCTURES Cu2Cu bonding or DBI, in 2016 [18,19]. The first A wide range of structures have been fabricated on back- generation TSVs, deployed as three major arrays above and illuminated substrates to provide improved electrical and along both sides of the active pixel array, featured a dual optical isolation. DTI process modules have been TSV structure for the row/column interconnect of a 1.12 µm implemented both early in the process flow (prior to active generation pixel array. One shallow, Cu-filled TSV device formation) and much later (after CIS back-of-die contacted the back of a metal 1 CIS metal pad, one deep, thinning). Most B-DTI structures in use to date have been Cu-filled TSV contacted a top metal Al ISP pad, and final filled with dielectrics, including a variety of high-k films. interconnect was achieved with a planar Cu metal strap. The The first DTI structures for back-illuminated CIS were dual TSV structures had a rectangular footprint and were found in 2010 in the HTC One UltraPixel camera chip placed on a 6.0 µm x 9.0 µm orthogonal pitch [20]. fabricated by STMicroelectronics [25]. These early front- Sony simplified its TSV process flow in 2015 by fabricated DTI (F-DTI) structures were built using silicon- introducing a single, or ‘unified’, structure which contacted on-insulator starting substrates. Current back-illuminated both CIS and ISP landing pads with one cylindrical vertical CIS chips are typically fabricated on back-thinned epi/bulk interconnect [21]. These structures were placed on a 9.1 µm substrates. minimum orthogonal pitch, although TSV rows were half- pitch staggered from neighboring rows. A. Sony OmniVision’s first observed stacked chips, fabricated on Sony’s first observed DTI effort was a B-DTI structure the PureCel-S platform with foundry partner XMC, featured found in the IMX147 in 2013 [26]. The B-DTI penetrated a ‘butted’ TSV structure in which a single, wide TSV about 0.3 µm deep into a 2.8 µm thick substrate and was contacted both a CIS and ISP pad structure. The rectangular filled with a first interfacial oxide followed by HfO, TaO, structures, in use on a 1.12 µm pixel generation chip, had a oxide, a Ti-based liner and W metal. This chip is the only 5.2 µm x 9.9 µm orthogonal pitch [22]. OmniVision later example of a metal filled trench from Sony. By 2015 Sony adopted a unified TSV structure for its 1.0 µm pixel switched to a deeper, dielectric filled B-DTI structure generation PureCelPlus-S chips, fabricated by foundry comprising a thin interfacial oxide, AlO, TaO, and an partner TSMC. These structures were placed on a 4.0 µm x undoped oxide core. Fig. 3 shows a recent, dielectric-filled B-DTI structure 4.1 µm orthogonal pitch [10]. from the 1.4 µm pixel generation IMX260 featuring a The observed Samsung stacked chips in production also 2.9 µm thick substrate. The B-DTI extends to a nominal feature a butted TSV structure, but instead use a W-based depth of 1.9 µm from the back surface, although it extends TSV window liner for vertical interconnect. The first- to a depth of 2.4 µm deep at B-DTI intersections. generation Samsung TSVs, incorporated on a 1.12 µm pixel generation chip, were placed on an 8.8 µm x 9.6 µm orthogonal pitch [23]. Sony recently shifted its interconnect strategy to incorporate DBI initially as a TSV array replacement. This implementation of DBI featured active DBI pads in the same regions as had been occupied by TSVs, with dummy DBI pads covering most of the active pixel array and peripheral regions. The current state of the art for production DBI is square pads having a 3.0 µm width placed on a 6.0 µm orthogonal pitch. A DBI pitch of 1.6 µm has been reported [24] and it is expected that future generations of DBI- enabled chips will feature per-pixel interconnect.

Fig. 3. Sony IMX260 – Exmor RS with DBI Technology Platform B. Samsung (a) (b) (c) B-DTI and F-DTI structures have been integrated to Fig. 1. Sony 1st gen. dual TSVs (a), 2nd gen. unified TSV (b), 1st gen. DBI (c) Samsung’s ISOCELL technology platform. Analyses to date indicate Samsung’s preference for full-depth F-DTI for 1.0 µm pixel generation ISOCELL and partial-depth B-DTI for 1.12 µm and 1.4 µm pixel generation ISOCELL structures. First-generation 1.0 µm pixel F-DTI ISOCELL structures, analyzed in 2015, were fabricated on a 2.7 µm thick (a) (b) (c) substrate. The DTI structure comprised a first deposited Fig. 2. OmniVision 1st gen. butted TSV (a), 2nd gen. unified TSV (b), Samsung butted TSV (c) oxide trench liner followed by an undoped poly fill [27]. No examples of a biased F-DTI fill have been found in mass produced chips.

− 22 − 2013 and later with Cu-to-Cu hybrid bonding, also known as IV. PIXEL ISOLATION STRUCTURES The first observed B-DTI structures from Samsung, REFERENCES Cu2Cu bonding or DBI, in 2016 [18,19]. The first A wide range of structures have been fabricated on back- implemented in a 1.12 µm pixel generation chip in 2015, [1] FujiFilm press release, Jul. 21, 2010. generation TSVs, deployed as three major arrays above and illuminated substrates to provide improved electrical and featured B-DTI trenches extending 1.3 µm deep into a [2] “Fujifilm MS3961 Die Markings 12.0 MP, 1.6 μm Pixel along both sides of the active pixel array, featured a dual 2.6 µm deep substrate. Size CCD Image Sensor from Fujifilm FinePix optical isolation. DTI process modules have been Z800EXR Focused Technology Analysis (FTA) Report”, TSV structure for the row/column interconnect of a 1.12 µm implemented both early in the process flow (prior to active IPR-1009-801-01, -03, -04, -05, Oct. 2010. generation pixel array. One shallow, Cu-filled TSV device formation) and much later (after CIS back-of-die [3] Nikon press release, Sep. 2011. contacted the back of a metal 1 CIS metal pad, one deep, [4] “Aptina MT9J007C1HS 12 Megapixel (10.1 Megapixel thinning). Most B-DTI structures in use to date have been Effective) CMOS Image Sensor with DR-Pix™ Cu-filled TSV contacted a top metal Al ISP pad, and final filled with dielectrics, including a variety of high-k films. Technology from a Nikon V1 Camera Imager Process interconnect was achieved with a planar Cu metal strap. The The first DTI structures for back-illuminated CIS were Review”, IPR-1110-804, Dec. 2011. dual TSV structures had a rectangular footprint and were [5] Canon EOS 650D press release, Jun. 2012. found in 2010 in the HTC One UltraPixel camera chip [6] “Canon LC1270 18.0 MP, 4.3 μm Pixel Size, APS-C placed on a 6.0 µm x 9.0 µm orthogonal pitch [20]. fabricated by STMicroelectronics [25]. These early front- Format CMOS Image Sensor from Canon EOS Rebel T4i Sony simplified its TSV process flow in 2015 by fabricated DTI (F-DTI) structures were built using silicon- (EOS 650D/EOS Kiss X6i)”, IPR-1206-802, Aug. 2012. introducing a single, or ‘unified’, structure which contacted [7] “Sony IMX270, Micro Four Thirds, 20.4 MP Resolution, on-insulator starting substrates. Current back-illuminated 3.3 µm Pixel Pitch, Front-Illuminated “Live MOS” both CIS and ISP landing pads with one cylindrical vertical CIS chips are typically fabricated on back-thinned epi/bulk CMOS Image Sensor from Olympus OM-D E-M1 Mark interconnect [21]. These structures were placed on a 9.1 µm substrates. II MILC”, DEF-1703-802, Apr. 2017. minimum orthogonal pitch, although TSV rows were half- [8] Fujifilm press release, Jan. 2013. A. Sony [9] “Toshiba TCM5112CL CMOS Image Sensor from pitch staggered from neighboring rows. Fujifilm X20 Device Essentials Summary”, DEF-1311- OmniVision’s first observed stacked chips, fabricated on Sony’s first observed DTI effort was a B-DTI structure 803, Nov. 2013. the PureCel-S platform with foundry partner XMC, featured found in the IMX147 in 2013 [26]. The B-DTI penetrated [10] “OmniVision OV16880, 1/3.06” Format, 16 MP a ‘butted’ TSV structure in which a single, wide TSV about 0.3 µm deep into a 2.8 µm thick substrate and was Resolution, 1.0 μm Pixel Pitch Stacked (PureCel Plus-S) Back-Illuminated CMOS Image Sensor”, DEF-1606-804, contacted both a CIS and ISP pad structure. The rectangular filled with a first interfacial oxide followed by HfO, TaO, Aug. 2016. structures, in use on a 1.12 µm pixel generation chip, had a oxide, a Ti-based liner and W metal. This chip is the only [11] Z5 product page, Oct. 2015. 5.2 µm x 9.9 µm orthogonal pitch [22]. OmniVision later example of a metal filled trench from Sony. By 2015 Sony [12] Canon EOS 70D press release, Jul. 2013. switched to a deeper, dielectric filled B-DTI structure Fig. 4. Samsung S5K3P3SX Stacked ISOCELL Technology Platform [13] Samsung press release, Mar. 2016. adopted a unified TSV structure for its 1.0 µm pixel [14] “Samsung S5K2L1, 1/2.6” Format, 12 MP Resolution, generation PureCelPlus-S chips, fabricated by foundry comprising a thin interfacial oxide, AlO, TaO, and an C. OmniVision 1.4 μm Pixel Pitch Back-Illuminated Stacked ISOCELL partner TSMC. These structures were placed on a 4.0 µm x undoped oxide core. OmniVision introduced partial B-DTI structures through CMOS Image Sensor from S7 (Model Fig. 3 shows a recent, dielectric-filled B-DTI structure SM-G930FD)”, DEF-1603-804, Apr. 2016. 4.1 µm orthogonal pitch [10]. its PureCel Plus-S technology platform, analyzed in 2016 from the 1.4 µm pixel generation IMX260 featuring a [15] “Sony IMX260 12 MP, 1.4 μm Pixel Pitch Stacked BI The observed Samsung stacked chips in production also [10]. The TSMC-fabricated structures for a 1.0 µm pixel CIS with DBI and Full Chip PDAF from the Samsung 2.9 µm thick substrate. The B-DTI extends to a nominal feature a butted TSV structure, but instead use a W-based generation CIS, extended 0.45 µm deep into the back Galaxy S7 edge Rear-Facing Camera Imager Process depth of 1.9 µm from the back surface, although it extends surface of a 2.5 µm thick substrate. The B-DTI trench fill Review”, IPR-1603-802, May 16, 2016. TSV window liner for vertical interconnect. The first- to a depth of 2.4 µm deep at B-DTI intersections. [16] “Sony 12 MP Resolution, 1.0 μm Pixel Generation generation Samsung TSVs, incorporated on a 1.12 µm pixel comprises an interfacial oxide, first deposited HfO, TaO, Stacked (Exmor RS) Back-Illuminated CMOS Image generation chip, were placed on an 8.8 µm x 9.6 µm oxide, Ti-based liner, and a W core. To date, this is the only Sensor from iPhone 7 Plus Telephoto iSight Camera”, observed DTI structure on an OmniVision chip and the first DEF-1612-801, Jan. 2017. orthogonal pitch [23]. [17] Oppo R9s landing page, Oct. 2016. Sony recently shifted its interconnect strategy to metal filled B-DTI trench since Sony’s effort in 2013. [18] Kagawa, et. al, “Novel Stacked CMOS Image Sensor incorporate DBI initially as a TSV array replacement. This with Advanced Cu2C2 Hybrid Bonding” ISSCC2017. implementation of DBI featured active DBI pads in the same Feb. 2017. [19] Invensas corporate web site, Apr. 2017. regions as had been occupied by TSVs, with dummy DBI [20] “Sony ISX014 1/4 Inch 8 MP, 1.12 μm Pixel Size Exmor pads covering most of the active pixel array and peripheral RS Stacked Back Illuminated CIS Imager Process regions. The current state of the art for production DBI is Review”, IPR-1302-801, Mar. 2013. [21] “Sony IMX278 13.0 MP Exmor RS™ RGBW Stacked square pads having a 3.0 µm width placed on a 6.0 µm BI CMOS Image Sensor Extracted from the P8 orthogonal pitch. A DBI pitch of 1.6 µm has been reported Imager Process Review”, IPR-1505-801, Jul. 2015. [24] and it is expected that future generations of DBI- [22] “OmniVision OV23850 PureCel-S 1.12 μm Pixel, 23.8 MP Stacked CMOS Image Sensor from Gionee enabled chips will feature per-pixel interconnect. GN9008”, DEF-1508-802, Sep. 2015. [23] “Samsung S5K3M2 13 MP Stacked, ISOCELL CMOS Image Sensor from Vivo X5Pro”, DEF-1507-801, Jul. 2015. [24] P. Enquist, “Stacked image sensors - the new image Fig. 3. Sony IMX260 – Exmor RS with DBI Technology Platform sensor standard”, 2015 Image Sensors Europe, Mar. 2015. B. Samsung [25] “STMicroelectronics 5 MP, 1.4 μm Pixel Pitch CMOS Image Sensor (5953BA Die Markings) Imager Process (a) (b) (c) B-DTI and F-DTI structures have been integrated to Fig. 1. Sony 1st gen. dual TSVs (a), 2nd gen. unified TSV (b), Review”, IPR-1003-802, Apr. 2010. 1st gen. DBI (c) Samsung’s ISOCELL technology platform. Analyses to date Fig. 5. OmniVision OV16880 PureCel Plus-S Technology Platform [26] “Sony IMX147 20 MP, 1.2 μm Pixel Pitch Back Illuminated (Exmor R) CMOS Image Sensor from the indicate Samsung’s preference for full-depth F-DTI for Sony Cyber-shot HX300 Digital Compact Camera”, IPR- 1.0 µm pixel generation ISOCELL and partial-depth B-DTI V. ACKNOWLEDGEMENTS 1307-801, Sep. 2013. for 1.12 µm and 1.4 µm pixel generation ISOCELL The author would like to thank the TechInsights’ lab staff [27] “Samsung S5K3P3SX 16 MP, 1.0 μm Pixel Pitch structures. and analysts, in particular Lee Riggins, Eric Rutulis and Stacked BSI Full ISOCELL CIS from the Samsung First-generation 1.0 µm pixel F-DTI ISOCELL structures, Galaxy A8 Smartphone Primary Camera Imager Process Wilson Machado for their numerous contributions to the Review”, IPR-1509-801, Jan. 2016. analyzed in 2015, were fabricated on a 2.7 µm thick Chipworks/TechInsights technical analysis library. (a) (b) (c) substrate. The DTI structure comprised a first deposited Fig. 2. OmniVision 1st gen. butted TSV (a), 2nd gen. unified TSV (b), Samsung butted TSV (c) oxide trench liner followed by an undoped poly fill [27]. No examples of a biased F-DTI fill have been found in mass produced chips.

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