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An Architecture for High-Speed Packet Switched Networks (Thesis) Purdue University Purdue e-Pubs Department of Computer Science Technical Reports Department of Computer Science 1989 An Architecture for High-Speed Packet Switched Networks (Thesis) Rajendra Shirvaram Yavatkar Report Number: 89-898 Yavatkar, Rajendra Shirvaram, "An Architecture for High-Speed Packet Switched Networks (Thesis)" (1989). Department of Computer Science Technical Reports. Paper 765. https://docs.lib.purdue.edu/cstech/765 This document has been made available through Purdue e-Pubs, a service of the Purdue University Libraries. Please contact [email protected] for additional information. AN ARCIITTECTURE FOR IDGH-SPEED PACKET SWITCHED NETWORKS Rajcndra Shivaram Yavalkar CSD-TR-898 AugusL 1989 AN ARCHITECTURE FOR HIGH-SPEED PACKET SWITCHED NETWORKS A Thesis Submitted to the Faculty of Purdue University by Rajendra Shivaram Yavatkar In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy August 1989 Il TABLE OF CONTENTS Page LIST OF FIGURES Vl ABSTRACT ................................... Vlll 1. INTRODUCTION 1 1.1 BackgroWld... 2 1.1.1 Network Architecture 2 1.1.2 Network-Level Services. 7 1.1.3 Circuit Switching. 7 1.1.4 Packet Switching . 8 1.1.5 Summary.... 11 1.2 The Proposed Solution. 12 1.3 Plan of Thesis. ..... 14 2. DEFINITIONS AND TERMINOLOGY 15 2.1 Components of Packet Switched Networks 15 2.2 Concept Of Internetworking .. 16 2.3 Communication Services .... 17 2.4 Flow And Congestion Control. 18 3. NETWORK ARCHITECTURE 19 3.1 Basic Model . ... 20 3.2 Services Provided. 22 3.3 Protocol Hierarchy 24 3.4 Addressing . 26 3.5 Routing .. 29 3.6 Rate-based Congestion Avoidance 31 3.7 Responsibilities of a Router 32 3.8 Autoconfiguration ... .. 33 3.8.1 Adding a New Node 35 3.8.2 Node Recovery ... 37 3.8.3 Adding aNew Link 38 3.9 Summary .......... 39 111 Page 4. HIGH-SPEED PROPAGATION OF CONTROL INFORMA- TION. .......... 41 4.1 Basic Algorithm 43 4.2 Possible Problems 45 4.2.1 Node restart 45 4.2.2 Network Partitions 46 4.2.3 Packet Corruption 46 4.3 Algorithm...... ... 46 4.3.1 Status Information At Each Node 48 4.3.2 Link Status Message .. 48 4.3.3 Additional Parameters . 50 4.3.4 Specific Actions. 52 4.4 Discussion. 55 4.5 Summary ........ 57 5. CONGESTION AVOIDANCE AND CONTROL. 59 5.1 Problem of Congestion .... 59 5.2 Related Work ......... 60 5.2.1 Preallocation of Buffers 60 5.2.2 Implicit Feedback. 61 5.2.3 Explicit Feedback . 61 5.3 Overview Of Our Scheme . 65 5.3.1 Avoidance and Control 66 5.3.2 Potential Users 66 5.4 Congestion Avoidance . 67 5.5 Congestion Control . 68 5.5.1 Rate Control Message 68 5.5.2 Generating Rate Control Messages 69 5.5.3 Using Rate Control Messages 73 5.5.4 Changing Transmission Rates . 74 5.5.5 Examples Of Uses 76 5.6 Features of Our Scheme .. 76 5.7 Performance Considerations 77 5.8 Summary . 78 6. A RESOURCE RESERVATION MODEL 80 6.1 Need for Predictable Performance ... 80 6.2 Existing Communication Abstractions 81 6.2.1 Circuit Switching . 81 6.2.2 Packet Switching . .. .. 82 6.2.3 Integrated or Hybrid Switching 83 IV Page 6.2.4 Discussion.......... 84 6.3 Providing Predictable Performance 85 6.4 Flow Semantics . ...... .. 87 6.4.1 Operations On A Flow. 88 6.4.2 Flow Parameters ... 90 6.5 Implementation........ 91 6.5.1 Architectural Support 93 6.5.2 Terminology ... .. 95 6.5.3 Precomputation of Flow Paths 95 6.5.4 Flow Initiation 97 6.5.5 Discussion. 100 6.6 Examples of Uses . 102 6.7 Related Work . 102 6.7.1 Type Of Service Routing with Loadsharing (BBN) 102 6.7.2 Real-Time Message Streams .. 104 6.7.3 Connection-Oriented Transport. 104 6.8 Summary ............ ... 105 7. EXPERIMENTAL EVALUATION 106 7.1 Introduction............ 106 7.2 Overview Of Prototype Network 108 7.3 Packet Switch Architecture .. 109 7.4 Packet Switch Implementation 111 7.4.1 Software Emulation 113 7.4.2 Point-to-Point Links. 116 7.5 Hosts and Routers ...... 116 7.5.1 A Review of Architectural Details 117 7.5.2 Software Implementation .. ... 119 7.6 Evaluation Methodology. ......... 119 7.6.1 Transmission Capacity of Network and Individual Links 119 7.6.2 Verification of Correctness. 122 7.7 Experimental Results. ...... 124 7.7.1 Predictable Performance. 125 7.7.2 Flows vs. Datagrams .... 131 7.7.3 Congestion Avoidance and Control 133 7.8 Summary ... 136 8. CONCLUSIONS 137 8.1 Predictable Performance. 137 8.2 Rate-based Congestion Avoidance and Control 138 8.3 Fast Propagation Of Link Status Updates 139 8.4 Future Directions ................. 140 v Page 8.4.1 Congestion Control. 140 8.4.2 Flows 140 8.5 Summary .. 142 BIBLIOGRAPHY. 143 VI LIST OF FIGURES Figure Page 1.1 A logical view of a computer network. ........ 3 1.2 The ISO Reference Model for Network Architectures 5 3.1 Basic model of UPDS in the context of an internet 21 3.2 Multi-Level Organization in upns 25 3.3 Protocol Hierarchy in UPDS . 27 3.4 A bidireclionallink in UPDS 28 3.5 Link (m,n) partitions the network. 38 4.1 A node with three adjacent links 46 4.2 A network with two partitions . 47 4.3 Algorithm to merge two link status update tables . 54 4.4 Recovery of node k merges two partitions 55 6.1 An abstract view of components of a flow 89 7.1 The basic hardware building block used for input 110 7.2 The basic hardware building block used for output 110 7.3 The structure of a multiprocessor packet switch. 112 7.4 Organization of the Software Emulator. ... .. 114 7.5 Organization of the Router software on input side 118 7.6 Organization of the Router software on output side. 120 7.7 Representative topologies used in experiments . ... 123 VIl Figure Page 7.8 Average per-packet delay for flow traffic with no datagram traffic. The dashed vertical line indicates the point at which interpacket ar- rival time equals per-packet processing time. 126 7.9 Effect of datagram traffic on per packet delays for flows when data­ gram traffic constitutes 15% of the total capacity. The average delays are same as those observed when datagram. traffic is absent. 127 7.10 Effect of datagram traffic on per packet delays for flows when data­ gram traffic constitutes 30% ofthe total capacity. The dashed vertical line marks the point at which the total tr~c starts exceeding the path capacity. 128 7.11 Effect of datagram traffic on flow throughput, where dashed line plots throughput when datagram traffic constitutes 30% of network capac~ ity, and solid line plots throughput when datagram traffic varies from oto 15% 130 7.12 Five plots in the graph show the effect of How traffic on per packet delays for datagrams depending on the amount of How traffic present. For the rightmost plot, no How traffic is present, whereas in the left­ most plot, amount of flow traffic equals 65% of the total path capac~ ~ rn 7.13 Two sources of traffic share a path to a common destination. 133 7.14 Congestion avoidance with two sources of traffic.The dashed vertical line marks the point at which both the sources start adjusting their transmission rates in response to rate control messages. The solid plot shows the throughput behavior for source 1 whereas dashed. plot shows the same for source 2. The dotted plot at the top shows the combined throughput of both the sources. ............... 134 VUl ABSTRACT Yavatkar, Rajendra Shivaram. Ph.D., Purdue University, August, 1989. An Architecture For High~Speed Packet Switched Networks. Major Professor: Douglas E. Comer. The emergence of performance intensive distributed applications is making new demands on computer networks. Distributed applications access computing re­ sources and information available at multiple computers located across a network. Realizing such distributed applications over geographically distant areas reqUIres access to predictable and high performance corrununication. Circuit switching and packet switching are two possible techniques for providing high performance communication. Circuit switched networks preallocate resources to individual sources of traffic before any traffic is s"ent, whereas packet switched networks allocate resources dynamically as the traffic travels through the network. The advantage of circuit switching lies in guaranteed performance due to reserved capacity, but the the network capacity is wasted when circuits are idle. Packet switched networks have been preferred in data networks due to their lower cost and efficient utilization of network resources. However, the major limitation of current packet switched networks lies in their inability to provide predictable performance. This dissertation proposes a new architecture for providing predictable high performance in high speed packet switched networks. The architecture combines the advantages of circuit switching and packet switching by providing two services: datagramlJ and jlOWlJ. The datagram service supports best-effort delivery of traffic. The main liability of a datagram service lies in congestion. To avoid congestion, the architecture uses a novel, rate-based congestion control scheme. To support IX applications that demand specific performance guarantees, the architecture provides an abstraction called a flow. A flow is a communication channel that has specific performance characteristics associated with its traffic. When requesting a flow, a source specifies the performance needs and a destination. The underlying delivery system guarantees to meet those needs by pre-allocating resources along a selected path to the destination. An experimental evaluation using a prototype network demonstrates the viabil­ ity of the architecture in providing predictable, high performance.
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