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How to Evaluate Reference-Clock Phase Noise in High-Speed Serial Links

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How to Evaluate Reference-Clock Phase Noise in High-Speed Serial Links TECHNICAL FEATURE How to Evaluate Reference-Clock Phase Noise in High-Speed Serial Links Gary Giust SiTime ost high-speed serial-data 1a shows an example PLL whose phase detector communications standards do compares corresponding input and feedback not include specifications for edges, and outputs a pulse proportional to their reference-clock (refclk) jitter. phase difference, which is then filtered to control Instead, jitter is specified for a voltage-controlled oscillator. In this example, the serial-data signal, a portion the phase detector samples its inputs at their of which originates from the refclk. Thus, these rising-edge midpoints. Therefore, the average Mstandards limit refclk jitter indirectly. Such a sampling (FS) and input clock frequencies (FIN) scheme gives designers more freedom to choose are equal. refclks, and budget jitter accordingly. Spectral components of jitter located Traditionally, real-time oscilloscopes have above the Nyquist frequency (FS/2) alias, or been used to determine jitter compliance fold back, below the Nyquist frequency after in serial-data signals. This analysis is sampling. Figure 1b illustrates the PLL jitter- straightforward because an oscilloscope-based transfer function, whose lowpass filtering time-interval error (TIE) jitter measurement characteristic is mirrored across spectral observes jitter similar to an actual system, whose boundaries at integer multiples of the Nyquist jitter filtering may be emulated in software frequency, FS/2. Below the Nyquist frequency, executed in the oscilloscope. jitter frequencies falling inside the PLL loop On the other hand, clock-jitter analysis bandwidth pass unattenuated, whereas jitter traditionally derives jitter from a phase noise frequencies falling outside this bandwidth get analyzer due to its inherently lower instrument attenuated by the response of the loop. Figure noise floor. Since an oscilloscope and phase noise 1c uses a logarithmic x-axis to plot a similar analyzer observe jitter differently, obtaining transfer function for a PLL having a closed- the same value from both instruments can be loop bandwidth of 5 MHz. The plot is drawn challenging. This article presents a phase noise arbitrarily to 1 GHz. based methodology that provides similar values Figure 2 illustrates how phase noise in a as TIE jitter derived from an oscilloscope, and 100 MHz input clock signal gets filtered by an therefore the actual system. This methodology example PLL2 with a closed-loop bandwidth of is used by PCI Express® BASE Specification 1 MHz. The green “Filter” curve shows the jitter- Revision 5.0 for refclk jitter compliance. An transfer function of the PLL up to an arbitrary expanded version of this article is available offset frequency of 500 MHz. Note that the x-axis online at Signal Integrity Journal.1 represents frequency offset from the carrier, as appropriate for phase noise, so that a 500 MHz HOW PLLs OBSERVE PHASE NOISE offset on the x-axis would appear at 600 MHz in A phase locked loop (PLL) is a basic building the signal spectrum (e.g., 500 MHz offset plus block in many digital and RF systems. Figure 100 MHz carrier). The 100 MHz input signal’s 42 | JULY 2019 SIGNALINTEGRITYJOURNAL.COM TECHNICAL FEATURE phase noise is also shown in Figure 2 using a black curve frequency. The Raw Data curve drawn in Figure 2 is thus for labeled “Raw Data.” Adding the Filter and Raw Data curves illustration only. In reality, phase noise in a 100 MHz clock produces the blue “Filtered Data” curve, which represents signal can only be directly measured up to a maximum offset how much of the input signal’s phase noise passes through frequency of 30 or 40 MHz, depending on the instrument. the PLL to appear in the output signal. The filtered phase Phase noise at higher offset frequencies can be estimated noise curve can then be integrated over an offset-frequency using a spectrum analyzer. However, since a spectrum range of interest to convert it to jitter.3 analyzer cannot distinguish between phase and amplitude However, a few issues complicate this integration. First, noise, any spectrum analyzer analysis of phase noise assumes the Raw Data curve shown in Figure 2 is not possible to that phase noise dominates at all offset frequencies. When measure at high offset frequencies. A phase noise analyzer this is not true, accuracy degrades, which may cause the measures phase noise directly, but it can only measure up to an result to be optimistic or pessimistic depending on several offset frequency equal to a fraction of the fundamental clock factors.4 For precision clock sources, phase noise usually dominates at near-in offset frequencies. Amplitude noise and/or modulation may dominate further out. 1/F S High +V Secondly, before the filtered phase noise can be integrated, V D Q I OUT the integration limits must be identified. The lower V IN CLR Delay VCO integration limit is typically set by the application, such Sample Points High as the bandwidth of a receiver’s observed jitter transfer D Q I Loop Filter function. The upper integration limit should extend until the –V CLR Phase phase noise falls to an insignificant level. One might assume Locked Loop this occurs near the analog input-bandwidth of the phase- (a) detector block in the transmit SERDES PLL. For example, if the phase-detector’s analog input bandwidth is 600 MHz, then the filtered phase noise curve 0 Fold Fold Fold Fold should be integrated to a 500 MHz offset (e.g., 600 MHz analog bandwidth minus a 100 MHz carrier equals 500 MHz offset frequency). However, a signal’s measured phase noise Jitter Gain (dB) Fs Fs 3×Fs 2×Fs is independent of its amplitude, at least until its amplitude 2 2 approaches the instrument’s noise floor. Thus, to first order, Jitter Frequency (Hz) (b) the input signal’s phase noise is not influenced by the analog input bandwidth of the phase detector, as the signal passes 0 through the PLL. −5 These issues make it difficult to determine an upper −10 integration limit for converting the filtered phase noise into −15 jitter, which we will address below. Jitter Gain (dB) −20 100k 1M 10M 100M 1G Jitter Frequency (Hz) HOW SERIAL-DATA LINKS OBSERVE REFCLK (c) PHASE NOISE s Fig. 1 Phase locked loop (a) block diagram illustrating Knowing how input phase noise aliases when sampled sampling at the phase detector, and example jitter-transfer by a PLL, we can now model the jitter-transfer function of function with (b) linear and (c) logarithmic x-axis. a serial-data communications link. As an example, we will use the common-clock timing architecture used by PCI 0 Express,5-6 as shown in Figure 3. Here, the refclk phase noise, –20 X, is filtered by the transmit PLL jitter-transfer function, 1H , and the receive PLL and CDR jitter-transfer functions, H –40 2 and H3, respectively. Note that H3 is modeled for 32 GT/s –60 links in Figure 3. The overall system jitter transfer function, –80 Y, is a function of H1, H2, H3, and T, which is the refclk time delay between transmit and receive paths. The phase noise –100 Filter Raw Data contribution from the reference clock that appears on the –120 Filtered Data output data is therefore computed as X × Y. –140 PCI Express 5.0 at 32 GT/s requires filtering the refclk with 16 different system jitter transfer functions. The worst- –160 case function, which leads to the highest jitter, for a given Phase Noise (dBc/Hz), Filter Gain (dB) –180 refclk is computed and plotted between 10 kHz and 30 MHz –200 as the green Filter curve in Figure 4a. The raw measured 100k 1M 10M 100M phase noise data is also plotted in Figure 4a, as a black curve Offset Frequency (Hz) labeled Raw Data. Finally, the filtered phase noise data is computed by adding the Filter and Raw Data curves and s Fig. 2 Illustration of phase noise in a 100 MHz input clock aliasing in a PLL by adding a PLL jitter-transfer function (green) plotted in Figure 4a as a blue curve labeled Filtered Data. to the input phase noise Raw Data (black) to derive an output A traditional PCI-SIG analysis evaluates TIE jitter in a Filtered Data phase noise (blue). 100 MHz refclk using a real-time oscilloscope. This method SIGNALINTEGRITYJOURNAL.COM JULY 2019 | 43 TECHNICAL FEATURE Tx Latch Channel Rx EQ Rx Latch Y 0 T = | T1 – T2 | CDR H3(s) –50 Filter Tx PLL Refclk, X(s) Rx PLL –100 Raw Data Filter Data 2sζ ω + ω 2 2sζ ω + ω 2 H (s) = 1 n1 n1 2 n2 n2 1 2 2 H2(s) = 2 2 –150 s +2sζ1ωn1+ ωn1 s +2sζ2ωn2+ ωn2 2 2 2 s s +2sζ2ω0+ ω0 s H (s) = –200 3 2 2 s + ω (s + ω0) (s + ω1) s +2sζ1ω0+ ω0 LF Phase Noise (dBc/Hz), Filter Gain (dB) Y = (H1 × e-sT – H2) × H3 –250 104 105 106 107 108 s Fig. 3 Illustration of PCIe5 32 GT/s system jitter-transfer Offset Frequency (Hz) (a) function (Y) used to filter refclk phase noise (X) in a common- clock timing architecture. 0 samples TIE jitter at each rising edge in the clock waveform, –50 such that spectral components of jitter above the Nyquist Filter frequency of 50 MHz alias below 50 MHz, as done in the –100 Raw Data Filtered Data real system. Therefore, a TIE jitter spectrum extends up to 50 MHz, and correctly aliases higher frequency components of –150 jitter (as done in the real system). By contrast, a phase noise analyzer includes a low-pass –200 filter that prevents measuring phase noise up to an offset frequency equal to half the clock frequency (e.g., 50 MHz).
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