Research Review 2001

Integrated Systems Laboratory Eidgenössische Technische Hochschule Zürich Swiss Federal Institute of Technology Zurich Microelectronics Design Center

Research Review 2001

W. Fichtner Q. Huang H. Kaeslin N. Felber D. Aemmer Grid Adaptation for Device Simulation

Automatic grid adaptation is a useful method to construct suitable simulation meshes, to control the solution accuracy, and to rllieve the user from manual work. The time-consuming and error-prone grid generation phase of a TCAD simulation suite can thus be shortened which reduces costs in commercial and industrial applications. Though state-of-the-art in many application areas, grid adaptation is not widely used within semiconductor device simulation because the mathematical nature of the underlying partial differential equations, expressed in terms of strong internal and boundary layers of the solutions, poses tremendous difficulties both for suitable adaptation criteria and the overall robustness of the adaptation module. In this project a novel anisotropic grid adaptation procedure for the stationary 2D drift-diffusion model has been developed. It implements the Scharfetter- Gummel box method on quad-tree based boundary Delaunay grids. The major concern has been to meet practical requirements by addressing the most interesting quantities as device terminal currents, to account for practical simulation cases, to achieve sufficient robustness, and to respect customer’s use of reasonable but quite coarse simulation meshes. The approach is based on estimates of the error of the system dissipation rate, gained by the solution of local Dirichlet Adaptively generated mesh for a 0.18µm nMOSFET suitable for the problems or residual methods. The ro- extraction of Id(Vd)-characteristics. bust recomputation of the solution on The junction layers are unresolved, adaptively achieved grids is crucial for anisotropic refinement is visible in the practical adaptive simulations and has channel, and the grid size (1397 ver- been remarkably stabilized even for tices) is smaller than manually optimized simulation grids with compara- large avalanche generation (refer to the ble accuracy. contribution on page 64 left).

Adaptively generated mesh for a power diode with several floating regions, complex geometrical features, and indicated jumps J(AGM-DR) of the element dissipation rate serving as error estimator.

Left Figures: Effect of grid adaptation on simulation grids of a reverse-biased 2D pn-diode with curved junction: Sequence of grids with indicated element error distribution at a fixed bias. Bottom figure: Reduction of the relative error of the global dissipation rate (black) and estimated relative errors based on different criteria as a function of the number of vertices.

Integrated Systems Laboratory Eidgenössische Technische Hochschule Zürich Swiss Federal Institute of Technology Microelectronics Design Center

Research Review 2001

W. Fichtner Q. Huang H. Kaeslin N. Felber D. Aemmer

Cover Image: World’s First RF Simulation of a Commercial Multi-Band Handset The trend toward mobility and the tremendous progress in communication technologies has created an exponen- tially growing market for wireless applications. Further advances in miniaturization and complexity require efficient and powerful tools in the R&Dphase of these products. A project jointly funded by industry and MINAST/KTI has the objective of creating the most advanced TCADtool for the analysis and optimization of the electromagnetic radio-frequency near-field. This study incorporated the most detailed analysis of a real-world handset scenario ever conducted, based on one of the latest commercially available multi-band mobile phones. Simulations were performed on the Finite-Differ- ence Time-Domain (FDTD)-based platform SEMCAD. The detailed CADdataset of the phone (Figure 1) consists of about 40 distinguished electromechanical parts. More- over, the PCB was modeled by 5 PEC/dielectric layers in- terconnected by more than 50 vias. The application of combined graded meshing and subgridding enabled grid resolutions of 100µm, embedded within computational domains extended by 0.5m. All measurements were performed using the DASY4 near-field scanner equipped with the latest probes. The agreement between measurement and simulation (Figure 2) for all examined parameters was considerably better than what the uncertainty assessment of the method would predict. Compared were all parameters significant for RF engineers, including impedance, efficiency, Fig. 1: Physical phone and its detailed CADequivalent within the 3-D far-field as well as near-field distributions (E, H, SAR) ACIS-based solid modeling environment of the SEMCADsimulation (Figure 3). An initial investigation of the antenna itself lead platform. to small deviations in gain and resonance frequencies (~1%), and for the averaged SAR, variations lower than 10% were obtained. Related subprojects are outlined on pages 80ff.

Fig. 2: Comparison of simulation (SEMCAD) and measurement (DASY4) for the E- and H-fields in a plane at 10mm above the phone. Fig. 3: Assessment of near- and far-field data in a real-world configura- All fields are normalized to the same input power. tion (head-phone: SAR and radiation pattern).

Address of the laboratory: Integrated Systems Laboratory Phone: +41 1 632 42 68 ETH Zentrum, ETZ Fax: +41 1 632 11 94 Gloriastrasse 35 e-mail: [email protected] CH-8092 Zürich WWW: http://www.iis.ee.ethz.ch Switzerland

Contents

Preface 9

Organization of the Integrated Systems Laboratory 12

Representative Figures 13

Staff 16

Former PhD Students 18

Academic Guests 23

Partners and Funding Agencies 26

Awards 36

Patents 37

History of the Integrated Systems Laboratory 38

Research Projects: IC and System Design and Test 43 GALS: Globally-Asynchronous Locally-Synchronous System Design 44 Multi-Point Interconnects for Globally-Asynchronous Locally-Synchronous Systems 44 Testability of Globally-Asynchronous Locally-Synchronous Wrapper Modules 45 Clock Generators for Globally-Asynchronous Locally-Synchronous Wrapper Modules 45 Multimedia Network Chips 46 Reconfigurable Hardware Accelerator for Real-time Multimedia Data Processing 46 Synchronization of an IEEE-1394 Network for Audio and Video 47 All-Digital Standardcell-Based PLL for Audio and Video 47 New Wireless Communication Systems 48 UMTS-MIMO-Transceiver 48 IP Core for Real-Time Solution of Least Squares Problems using CORDIC and QRD-RLS 49 Lower Bounds on Power Dissipation in Digital VLSI 49 Control of Combined Parallel/Series-Connected IGBTs 50

Research Projects: Analog and Mixed-Signal Design 51 Transmit I/Q Modulator for UMTS (Universal Mobile Telecommunications System) 52 Baseband Circuits for Direct Conversion UMTS Mobile Receiver 52 IQ Demodulator for Direct-Conversion UMTS Mobile Receiver 53 Baseband Circuit for UMTS Transmitter 53 A 33mW, 14-bit, 2.5Msample/s Sigma-Delta A/D Converter 54 A Low-Power 8-bit Folding and Interpolating Analog-to-Digital Converter 54 A High-Speed D/A Converter with Background Calibration 55 Broadband Sigma-Delta D/A Converter 55 Optimization of OTAs for Application in Sampled Data Systems 56 High-Speed Multibit Sigma-Delta Modulator for Telecom Applications 56 An 18mW 1800MHz Quadrature Demodulator in 0.18µm CMOS 57 Mobile Telemonitoring System for Biomedicine 57

Research Projects: Technology CAD 59 Modeling and Simulation of Quantum Effects in MOSFETs 60 Quantum Drift Diffusion (QDD) Modeling of Tunneling through Insulators 60 Simplified Model for Inelastic Acoustic Phonon Scattering 61 Hot-Carrier Degradation of MOSFETs 61 Conductance of Nano-Scale Silicon-On-Insulator (SOI) Single Electron Devices 62 3D Simulation of Noise in Bipolar Transistors 62 Monte Carlo Generated Noise Sources 63 Coulomb Enhancement of Radiative Recombination Rates 63 Robust Grid Adaptation in Device Simulation for Large Avalanche Generation 64 Process Simulation with "noffset3d" Meshes 64 "Moving Boundary" Algorithm with Volume Triangulations 65 Simulation of Substrate Leakage in Semiconductor Lasers 65 Calculation of the Spontaneous Emission Coupling for Edge-Emitting Lasers 66 Simulation of a Tunable Twin-Guide Distributed-Feedback Semiconductor Laser 66 Simulation of a Weakly Index-Guided Buried-Stripe Type Laser Diode 67 Self-Heating Effects in Multi-Dimensional Simulations of Quantum-Well Lasers 67 Temperature and Carrier Density Effects on Optical Modes in Quantum-Well Lasers 68 LUMI2 Optical Mode Solver 68 Numerical Simulation of InP/InGaAs High-Speed Photodetectors 69 Intraband Photon Absorption in Multi-Quantum-Well (MQW) Structures 69 Optoelectronics Characterization Laboratory (OptoLab) 70 Molecular Dynamics-Kinetic Monte Carlo Calculations of Ion Implantation 70 Ab-Initio Study of Arsenic Activation and Deactivation in Silicon 71 Diffusion Mechanisms of Highly Arsenic-Doped Silicon 71 Ab Initio Calculations for the Self-Interstitial in Silicon 72 Parallel Iterative Methods for Large Sparse Linear Systems from Semiconductor Simulation 72

Research Projects: Physical Characterization 73 Reliability of Power Semiconductors for Automotive Applications Thermal and Computational Fluid Dynamics Simulation of Integrated Modules 74 Electrical Characterization of Silicon at Very High Temperatures 74 Extraction of Doping Profiles by Scanning-Capacitance Microscopy 75 Characterization of the Offset Matching for MOS Transistor Structures 75 Measurements and Device Simulations of Transient Substrate Effect in Smart-Power ICs 76 Minimization of Transient Substrate Effects 76 Device Simulation of Transient Latchup 77

Research Projects: Bio Electromagnetics and Electromagnetic Compatibility 79 RF Design of Mobile Phones by Technology Computer Aided Design (TCAD) 80 A Robust FDTD Subgrid Scheme for General Application to Enhanced Antenna Analysis 80 Hybridization of a Post-Processing Environment for MTE Analysis and Optimization 81 A Phase-Corrected FDTD Algorithm for the Simulation of Optical Structures 81 Novel High-Resolution Temperature Probe for Micro-Dosimetry 82 Advanced Evaluation of Measurement Results 82 Pilot Study Time-Domain Field Sensors 83 Improved Methodology for Base-Station Site Evaluations 83 Risk Assessment: Exposure Systems for Combined Toxicity/Carcinogenicity Studies in Mice 84 Risk Assessment: Exposure Systems for Combined Toxicity/Carcinogenicity Studies in Rats 84 Risk Assessment: Preliminary Dosimetry of the Mouse Setup 85 Risk Assessment: Preliminary Dosimetry of Rat Setup 85 Risk Assessment: Characterization of a RF Setup for In-Vitro Studies 86 Risk Assessment: Characterization of an ELF Setup for In-Vitro Studies 86 Risk Assessment: Detailed Dosimetry of Human Exposure Setup 87 Effect of EMF Exposure on Cerebral Blood Flow and Sleep EEG 87 Controlling and Monitoring Software of Exposure Systems 88 Data Processing and Analysis of Exposure and Environmental Parameters 88 Risk Assessment: Advanced Animal Models 89 Standards: Scalability of In-Vivo to Human Exposures 89

Standards: Evaluation of Human-Head Phantoms for MTE Compliance Testing 90 Standards: Implementation and Application of Novel IEEE SCC34 SAR Extraction 90

Education Program: Student Projects 91 EDGE Equalizer Acceleration Unit 93 Tempo Rex – A GPS Reference Time Controller for FireWireTM 93 MP3 Player Chip: Decoder Part 94 MP3 Player Chip: Digital Signal Processing Part 94 Development of a Reusable M68000 Microprocessor Core 95 8-bit Microprocessor Core 95 Performance Analysis of AMD Southbridge “Zorak” 96 Low-Voltage, Low-Power DDA-based Frontend with Improved Dynamic Range 96 Design and Implementation of a Fast Sample-and-Hold Circuit 97 Arithmetic Coding and its Efficient Implementation 97 Real-Time Video Compression System and Error Resilience Methods 98 JPEG-3D Video CoDec Software 98 Digital Precision Altimeter 99 Battery Charge Controller for a Diving Lamp 99 High-Precision Audio Signal Generator based on Direct Digital Synthesis (DDS) 100 DDS-based High-Frequency Function Generator on a PCI Board 100 Audio Transmission over FireWireTM 101 Compact Model Parameter Extraction for Semiconductor Laser Simulation 101 Spontaneous Emission in Surface-Emitting Lasers 102 Calculation of Electronic Band Structures for Laser Simulations 102 Simulation of Twin-Guide Tunable Lasers 103 Device Simulator Calibration for Substrate Effect Investigations in Smart-Power ICs 103

PhD Theses – Abstracts 104

Diploma Theses – Overview 108

Student Theses – Overview 109

Microelectronics Design Center 110

Joint Research Cooperation with IT'IS 112

Workshops and Courses 113

Lectures 114

IC Design Projects – Overview 117

Research Projects – Overview 119

Presentations 128

Publications 133

Technical Reports 138

Design, Electronic Test, and Physical Characterization Equipment 140

Computer Equipment 144

Preface

This is a report on the academic and research ac- NANO 21 and eleven by industry in Switzerland, tivities of the Integrated Systems Laboratory (IIS) Europe, USA and Japan. and the Microelectronics Design Center (DZ) at A total of 47 job positions at IIS were financed by the Department of Information Technology and third-party projects, which, in relation to the 21 Electrical Engineering (D–ITET) of the Swiss Fed- ETH positions, and in comparison with other labo- eral Institute of Technology in Zurich (ETH Zurich) ratories of ETH Zurich, is a tribute to the quality of for the year 2001. research performed by our staff. The IIS staff includes two professors, five research In 2001, eight PhD students finished their doctoral associates, five post docs, forty four (44) PhD stu- thesis successfully. IIS offers an excellent and dents, three computer system administrators, highly stimulating research environment that per- three secretaries and five technicians. mits PhD students to work on very attractive topics Research topics in digital, mixed, and analog inte- and, nevertheless, to finish their thesis in a com- grated circuit (IC) design range from sensitive paratively short time. It must be stated, however, sensor interfaces to GHz RF circuits on the analog that very attractive positions in industry and the side, over analog-to-digital converters to the digital service sector make it increasingly harder to find field covering projects from low-power design qualified PhD students. At present, this is a severe methodologies to complex systems-on-a-chip problem of our laboratory, especially for projects in (SoC). Technology CAD (TCAD), technology and the areas of analog and digital design. We try the device development, characterization, and bio- best to overcome this situation by an appropriate electromagnetics complement the research fields salary policy and by focusing the student activities of IIS towards professional tools for modeling and on scientific work in order to reduce the adminis- optimizing micro-electronic and opto-electronic trative and educational overhead. devices in the deep-submicron and nanometer During 2001, IIS' research results led to many range as well as micro-systems and bio-electro- publications in scientific journals and presentations magnetic systems. at international conferences. Within the context of The Microelectronics Design Center, headed by the research activities several important scientific Dr. H. Kaeslin, with four staff members, is a ser- results have been achieved by IIS members. vice organization of the Department of Information The strength of the research group of Professor Technology and Electrical Engineering. It is closely Huang in the development of high-speed, low- co-operating with IIS and other D–ITET and ETH power A/D converters is demonstrated in the Zurich laboratories in their design research and world's first implementation of a Sigma-Delta con- teaching activities for VLSI, analog and system verter to be used in UMTS/GSM dual-standard electronics (see page 110). applications. The realization in a standard digital Following the trends of earlier years, our co- CMOS process as well as the optimization for both operation with national and international partners standards that leads to a very low power is at the center of our activities. In 2001 two new consumption makes it very attractive for use in European (funded by BBW, Swiss Federal Office highly integrated, hand-held equipment. The A/D for Education and Science), one new KTI (Swiss converter has been presented at ISSCC 2001. A Commission for Technology and Innovation), three second presentation at ISSCC reports the new TOP NANO 21 (Swiss technology-oriented successful implementation of an ultra-low offset research program) and four new industrial re- low-noise amplifier that employs a new clocking search projects with a total funding volume of 5.2 scheme to suppress residual offset down to million Swiss Francs have started in the fields of 200 nV. The analog research group participates in semiconductor process and device development two major EU research projects that both have and simulation, complex digital systems on chip, their focus on new telecommunications and sensitive analog circuits. Overall, IIS was in- techniques. The first project concentrates on the volved in a total of 38 research projects. Nine of development of wire-bound internet access via them were EU projects funded by BBW, eleven by standard power lines with Professor Huang's KTI, one by ETH Zurich, two by SNF, four by TOP research group being responsible for high-speed data converters, while the second project focuses

the second project focuses on CMOS RF trans- robustness of grid adaptation was improved. An ceivers for third-generation mobile communica- interface between the process simulator DIOS and tions equipment. the meshing engine "noffset3d" and a moving The digital design group of the Integrated Systems boundary algorithm with volume triangulation were Laboratory contributed with its research to the developed. A new linear solver has been imple- success of the very first multimedia network ASIC mented which improves the robustness of the it- of the startup company BridgeCo. The globally- erative method to solve large problems in semi- asynchronous locally-synchronous design meth- conductor device simulation. odology for large systems-on-a-chip has moved In the physical characterization group, important closer towards industrial applicability: Multi-point results have been obtained concerning the thermal interconnects have been integrated and a test management and the reliability prediction of power method has been developed. For a multi-antenna devices used in hybrid vehicles. In particular, new (MIMO) wireless communications system, the IIS procedures and tools have been developed for the group contributed to a project with Lucent Wireless fast extraction of accurate compact thermal mod- Research with a receiver frontend and optimiza- els for highly integrated power IGBT and power tions of the MIMO decoder. An intelligent driver MOSFET assemblies. Furthermore, based on chip for parallel- and series-connected power de- thermo-mechanical considerations, new models vices (IGBTs) was successfully implemented and have been proposed to estimate the lifetime of tested. power devices used in traction applications. In or- TCAD has been a main research area in our labo- der to characterize silicon at temperatures up to ratory. During the last year, a broad range of activi- 1000 K, new test structures and experimental set- ties led to interesting results in the fields of ultra- ups have been designed for the extraction of the small electronic devices, optoelectronic devices, mobility and impact-ionization coefficients. The first-principle mechanical modeling, mesh genera- design has been based on extensive simulation of tion, and linear solvers. Quantum effects in scaled the test structures with a special focus on the MOSFETs were studied by the density gradient thermal generation of carriers. Considerable pro- model in order to further validate this tool for gresses have been made in the one- and two- TCAD applications. Advancements of the full-band dimensional profiling of dopants in silicon by single-particle Monte Carlo simulator SPARTA al- Scanning-Capacitance Microscopy (SCM). The lowed its use for more routinely TCAD, e.g. in preparation of reproducible SCM samples and the process calibration and for the simulation of hot- wear-out of the scanning probes could be taken carrier degradation. Noise modeling focused on under control by extensive experiments and with 3D noise simulation of state-of-the-art bipolar tran- diamond-coated cantilevers. sistors and the generation of realistic RF noise IT'IS, the "Foundation for Research on Information sources using bulk full-band Monte Carlo. Our Technologies in Society" (headed by ETH adjuct SIMNAD code for the physics-based simulation of Prof. Niels Kuster), a non-profit research institution single-electron transistors was further developed, supported by ETH Zurich, established its scientific now also applicable to SOI devices. The laser and technical work in close collaboration with our module of the device simulator DESSIS was ex- laboratory. The research activities of IT’IS are in tended facilitating the self-consistent simulation of the domain of the interaction of electromagnetic temperature and density effects on optical modes, radiation with biological organisms, and in ad- a physics-based VCSEL device simulation, the vanced measurement equipment for electromag- optimization of tunable laser diodes, and the netic radiation. A growing number of research pro- realistic modeling of photo-detectors. Conceptual jects and PhD students at IIS is funded by the work was carried out for the joint OptoLab facility global wireless communications industry, several that will allow to systematically characterize governmental agencies and the Commission of the optoelectronic devices. Activities in the field of European Union. It turned out that this collabora- microscopic process simulation concentrated on tion with IT'IS is very fruitful and a benefit for both the simulation of implantation and annealing by a institutions (see page 112). combination of molecular dynamics and kinetic Next to research, teaching occupies a central role Monte Carlo. Ab-initio studies of diffusion of our activities. Our staff is responsible for several mechanisms in highly doped silicon and of the core lectures in the Electrical Engineering and contribution of the self-interstitial to dopant other departments (see page 114). The chapter on diffusion were carried out. The robustness of grid

student projects (page 91) gives an overview on and its services and administration.Finally, we the manifold diploma theses and term projects. would like to express our gratitude to the Swiss While most of these student theses are in the field Commission for Technology and Innovation (KTI), of IC design, some hardware and software activi- the Swiss National Science Foundation (SNF), the ties are included as well. Swiss Federal Office for Education and Science Two new contributions to the PPS (Practical Exer- (BBW), the Swiss program TOP NANO 21, and the cises – Projects – Seminars) have been started in Commission of the European Union for their finan- 2001. This initiative aims at motivating young EE cial support. Just as much we would like to thank students for their future profession. The "Video our partners ABB Switzerland, AMS Austria, Ava- Compression Project" let students experiment with lon Photonics Switzerland, Bernafon Switzerland, real-time video data streams. In the "Digital Audio Bosch Germany, BridgeCo Switzerland, Concept Project" they realized a Digital-Signal-Processor Switzerland, Conexant USA, Fraunhofer- system with audio codec and implemented algo- Gesellschaft Germany, Fujitsu Japan, German rithms to take effect on musical instruments and Government Germany, IMEC Belgium, Infineon voice. Germany, INRIA France, ISE Integrated Systems Engineering AG Switzerland, IT'IS Foundation Prof. Fichtner is currently Head of the Department Switzerland, Lucent Technologies USA, Motorola of Electrical Engineering, and he was reelected to USA, Nortel Networks Switzerland, NTT Japan, hold this position till the end of September 2003. Opto Speed Switzerland, Philips Semiconductors The activities of our laboratory were only possible Zurich Switzerland, SPEAG Switzerland, ST Mi- through the support from the governing board of croelectronics Italy and France, Toshiba Japan, our university, and several national and interna- Toyota Japan, University of Bologna Italy, Univer- tional institutions and industrial parties. Special sity of Pisa Italy, WIAS Germany, and the ETH Zu- thanks go to our school, to the computing services rich laboratories IBT, IfE, IFH, IKT, IWR, and TIK of ETH Zurich, as well as to the Department of for the fruitful cooperation in research projects as Information Technology and Electrical Engineering well as for their financial support.

11 Organization

12 Representative Figures Staff

Number of full job positions at the Integrated Systems Laboratory from 1992 to 2001.

PhD Theses

Number of completed PhDtheses per year at the Integrated Systems Laboratory from 1992 to 2001. Abstracts of PhD theses 2001: see page 104.

13 Journal and Book Publications

Number of journal and book publications by the Integrated Systems Laboratory from 1992 to 2001. Ref- erences: see page 133.

Conference and Workshop Presentations

Number of conference and workshop presentations by the Integrated Systems Laboratory from 1992 to 2001. References: see page 127.

14 IIS Research Projects

Number of research projects with external funding at the Integrated Systems Laboratory from 1992 to 2001. Overview research projects: see page 119. Partners and funding agencies: see page 26.

Research Partners of IIS

CH Europe USA Japan Others World Industry 16 32 6 3 0 57 Academia 10 15 2 1 1 29

Research partners of the Integrated Systems Laboratory in Switzerland (CH), Europe and worldwide. Addresses of partners: see page 26.

Staff

Professors Fichtner Wolfgang, Dr., Professor for Electronics, Head since 1 Sep 1985 Huang Qiuting, Dr., Professor for Electronics since 1 Jan 1993

Microelectronics Design Center Kaeslin Hubert, Dr., dipl. El. Ing. ETH, Head since 1 Jan 1986 Brändli, Matthias, dipl. El. Ing. ETH since 1 May 2001 Haldemann Richard, dipl. El. Ing. ETH since 1 July 1998 Köppel Rudolf, FEAM since 1 Apr 1995 Wieland Andreas, dipl. El. Ing. ETH 5 Mar 1990 – 31 Jul 2001

Scientific Staff Aemmer Dölf, Dr., dipl. Phys. ETH, Senior Scientist since 1 Sep 1985 Alonso Eduardo, Dr., Industrial Engineer since 1 Jul 2000 Bachmann Andreas, dipl. El. Ing. ETH since 1 Dec 1998 Balmelli Pio, dipl. El. Ing. ETH since 1 Apr 1998 Bösch Thomas, dipl. El Ing. ETH since 1 Apr 2000 Brändli, Matthias, dipl. El. Ing. ETH 1 Dec 1997 – 30 Jul 2001 Brenna Gabriel, dipl. El. Ing. ETH since 1 Mar 2000 Brugger Simon, dipl. El. Ing. ETH since 1 Jan 2001 Bufler Fabian, Dr.-Ing. since 1 Nov 1997 Burg Andreas, dipl. El. Ing. ETH since 6 Nov 2000 Burger Thomas, Dr., dipl. El. Ing. ETH since 1 Oct 1994 Chavannes Nicolas, Dr., dipl. El. Ing. ETH since 1 Oct 1999 Chen Xinhua, M. Sc. EE since 1 Sep 2001 Cherubini Emilio, dipl. Phys. ETH since 8 Jan 2001 Chevtchenko Serguei, Eng.-Phys. since 1 Aug 2001 Christ Andreas, Dipl.-Ing. der Nachrichtentechnik since 1 Oct 1999 Ciampolini Lorenzo, Dr., Dipl.-Phys. 1 Sep 1997 – 31 Jul 2001 Ciappa Mauro, Dr., Dipl.-Phys. since 1 Jan 1998 Deiss Armin, Dr., dipl. El. Ing. ETH since 15 Feb 1997 Ebert Sven, Dipl.-Phys. since 15 May 2000 Felber Norbert, Dr., dipl. Phys. ETH, Senior Scientist since 1 Jul 1987 Francese Pier-Andrea, Dipl. El. Ing. since 1 Sep 2000 Geelhaar Frank, Dipl.-Phys. since 1 Oct 1998 Glass Boris, Dipl.-Phys. since 1 Mar 1998 Gürkaynak Frank, Dipl. El. Ing. since 15 Sep 2000 Hammerschmied Clemens, Dr., dipl. El. Ing. ETH since 1 Jun 1994 Heinz Frederik, dipl. Phys. ETH since 25 Apr 2000 Hertle Jürgen, Dipl. Ing. Elektrotechnik since 2 Mar 1998 Höhr Tim, Dipl.-Phys. since 15 Mar 2001 Interlandi Gianluca, dipl. Phys. ETH 1 Mar 1997 – 31 Jul 2001 Kouchev Ilian, M. of Science since 1 Sep 2000 Krause Jens, Dr., Dipl.-Phys. since 1 Nov 1997 Martelli Chiara, Dipl. El.-Ing. since 17 Jan 2001 Mertens Rainer, Dipl.-Phys. 15 May 2000 – 14 May 2001 Müller Christoph, dipl. Phys. ETH since 1 Jun 2000 Oberle Michael, Dr., dipl. El. Ing. since 1 Sep 1994 Oesch Walter, dipl. Natw. ETH since 15 Aug 2000 Oetiker Stephan, dipl. El. Ing. ETH since 13 Aug 2001 Oila Kari, M. Sc. (Mech. Eng.) since 1 Jan 2001 Perels David, dipl. El. Ing. ETH since 1 Feb 2001 Pfaff Dirk, dipl. El. Ing. ETH since 1 Mar 1997 Pfeiffer Michael, Dipl.-Phys. since 1 Oct 1999 Pomp Andreas, Dr. rer. nat. since 1 Jan 1999 Reutemann Robert, dipl. El. Ing. ETH since 15 Jan 1998 Rogin Jürgen, dipl. El. Ing. ETH since 1 Apr 1999

Röllin Stefan, dipl. Math. ETH since 1 Apr 2000 Roth Eric, dipl. El. Ing. ETH since 5 Apr 2000 Sahli Beat, Dipl.-Phys. since 1 Jun 2000 Schaldach Markus, Dipl.-Ing. since 1 Mar 2000 Schenk Andreas, PD, Dr., Dipl.-Phys., Senior Scientist since 1 Aug 1991 Schenkel Michael, dipl. El. Ing. ETH since 1 Mar 1999 Schmithüsen Bernhard, Dr., Dipl.-Mathematiker since 27 May 1996 Schneider Lutz, dipl. Phys. ETH since 7 May 2001 Schuderer Jürgen Rudolf, Dipl.-Phys. since 1 Oct 1999 Stangoni Maria, Dipl. El.-Ing. Uni-Cagliari since 15 Feb 2001 Streiff Matthias, dipl. El. Ing. ETH since 7 Feb 2000 Thalheim Jan, Dipl.-Ing. Elektrotechnik since 5 Nov 1996 Tschopp David, dipl. El. Ing. ETH since 1 Mai 1999 Villiger Thomas, dipl. El. Ing. ETH since 1 Mai 1998 von Allmen Alain, dipl. Phys. ETH 1 Oct 1996 – 31 Jul 2001 Wassner Jürgen, Dr., Dipl.-Ing. Elektrotechnik 9 Oct 1997 – 31 Dec 2001 Witzig Andreas, Dr., dipl. El. Ing. ETH since 1 Aug 1997 Zelenka Stefan, Dr., Dipl.-Phys. 1 Sep 1997 – 15 Sep 2001

Computer Staff Böhm Anja, Dipl. Geologe since 1 Apr 2001 Richardet Christoph, Oberstufenlehrer since 10 May 2000 Wicki Christoph, dipl. El. Ing. ETH since 1 Oct 1985

Technical Staff Balmer Christoph, dipl. El. Ing. HTL since 1 Aug 1989 Gisler Hansjörg, Industriespengler since 1 Sep 1989 Illien Fritz, dipl. El. Ing. HTL since 1 Mai 1998 Mathys Hanspeter, Elektromonteur since 15 Dec 1990 Rheiner Rudi, dipl. El. Ing. HTL since 15 Nov 1996

Administrative Staff Boksberger Margit (50%) since 1 Jan 2000 Fischer Bruno, dipl. El. Ing. HTL since 14 Apr 1992 Haller Christine, Betriebsökonom HWV (95%) since 8 Mar 1993 Plank Eva (55%) since 1 Jul 1998 Roffler Verena (50%) since 1 Sep 1999

Former PhD Students

Name degree now with received

Bach Carlo 1993 Interstaatliche Hochschule für Technik (NTB) Werdenbergstrasse 4 CH-9470 Buchs, Switzerland Basedau Philip 1999 Philips Semiconductors AG, Binzstrasse 44, CH-8045 Zürich, Switzerland Bonnenberg Heinz 1993 Micronas Munich GmbH Frankenthalerstrasse 2 D-81539 München, Germany Bürgler Josef 1990 Hochschule Technik+Architektur Luzern Technikumstrasse 21 CH-6048 Horw, Switzerland Burger Thomas 2002 Integrated Systems Laboratory ETH Zentrum CH-8092 Zürich, Switzerland Ciampolini Lorenzo 2001 CEA-Grenoble, LETI/DTS/SCPC, 17, rue des Martyrs, F- 38054 Grenoble Cedex 9, France Ciappa Mauro 2000 Integrated Systems Laboratory ETH Zentrum CH-8092 Zürich, Switzerland Conti Paolo 1991 esmertec ag, CFO & Head HR Lagerstrasse 14 CH-8600 Dübendorf, Switzerland Curiger Andreas 1993 Omnisec AG, Rietstrasse 14, CH-8108 Dällikon, Switzerland Deiss Armin 2002 Integrated Systems Laboratory ETH Zentrum CH-8092 Zürich, Switzerland Dettmer Hartmut 1994 Infineon Technologies, AI IP DD LV 1, Balanstr. 73, D-81541 München, Germany Doswald Daniel 2000 ATI Technologies Inc. 55 Commerce Valley Drive West Suite 100, Thornhill, Ontario L3T 7V9, Canada Eicher Simon 1996 ABB Semiconductors AG R&D Lb2, Fabrikstrasse 3 CH-5600 Lenzburg, Switzerland Esmark Kai 2001 Infineon Technologies, DAT LIB TI-ESD/Latch-up Postfach 80 17 09 D-81609 München, Germany

Fillo Marco 1993 Quadrics Supercomputers World Ltd., Via Marcellina 11, I-00131 Roma, Italy Gappisch Steffen 1996 Philips Semiconductors AG, Binzstrasse 44, CH-8045 Zürich, Switzerland Garreton Gilda 1998 UBS AG, Stamford Branch Washington Blvd. 677, Stamford, CT 06901, USA Gull Ronald 1996 BridgeCo AG, Ringstrasse 14, CH-8600 Dübendorf, Switzerland Hager Christian 2000 McKinsey & Company Alpenstrasse 3 CH-8065 Zürich, Switzerland Hammerschmied Clemens 2000 Integrated Systems Laboratory ETH Zentrum CH-8092 Zürich, Switzerland Heeb Hansruedi 1989 esmertec ag, CFO & Head HR Lagerstrasse 14 CH-8600 Dübendorf, Switzerland Heiser Gernot 1991 School of Computer Science & Engineering, University of New South Wales, P.O. Box 1, Sydney, 2052 NSW, Australia Herkersdorf Andreas 1991 IBM Research Center, Zurich Research Lab, CH-8803 Rüschlikon, Switzerland Herrigel Alexander 1990 R3 Security Engineering AG, Zürichstrasse 151 CH-8607 Aathal-Seegräben, Switzerland Heusler Lucas 1990 IBM Research Division, Zurich Research Lab, Säumerstrasse 4 CH-8803 Rüschlikon, Switzerland Hitschfeld Nancy 1993 Departamento Ciencias de la Computacion, Universidad de Chile, Blanco Encalada 2120, Santiago, Chile Höfler Alexander 1997 Motorola, Inc., 6501 West William Cannon Drive, Mail Drop OE341 Austin, Texas 78735, USA Humbel Oliver 2000 ABB Semiconductors AG Produktion Lb2 Fabrikstrasse 3 CH-5600 Lenzburg, Switzerland Kells Kevin 1994 179 Capital Lane, Roseburg, OR 97470, USA Körner Thomas 1999 ABB Business Services Ltd., SLE-I Intellectual Property, Brown Boveri Strasse 6 CH-5400 Baden, Switzerland

Krause Jens 2001 Integrated Systems Laboratory ETH Zentrum CH-8092 Zürich, Switzerland Krumbein Ulrich 1996 Infineon Technologies, WS SD D TrMOS, Postfach 80 09 49, D-81609 München, Germany Kuratli, Christoph 1999 Bernafon Ltd., IC-Design, Morgenstr. 131, CH-3018 Bern, Switzerland Lamb Peter 1990 55 Gilbert ST Hackett 2602 Canberra, Australia Lendenmann Heinz 1994 ABB Corporate Research, Dept. G, SE-721 78 Västerås, Sweden Leonhardt Götz 2000 Sun Microsystems 901 San Antonio Road M/S USUN02-301 Palo Alto, CA 94303-4900, USA Liegmann Arno 1995 Rüti 18, CH-8357 Guntershausen, Switzerland Litsios James 1996 Actant AG, Bahnhofstr. 10, CH-6300 Zug, Switzerland Menolfi Christian 2000 IBM Zurich Research Lab Säumerstrasse 4 CH-8803 Rüschlikon, Switzerland Mergens Markus 2001 Sarnoff Corporation, 201 Washington Road CN-5300, Princeton, NJ 08543-5300, USA Müller Stephan 1994 371 Maeve Ct, San Jose, CA 95136, USA Muttersabach Jens 2001 Phonak AG, Systems Design, Laubisrütistrasse 28, CH 8712 Stäfa, Switzerland Neeracher Matthias 1998 Apple Computer, Inc. MS 301-3KM, 1 Infinite Loop, Cupertino, CA 95014, USA Nussbaum Miguel 1988 Departamento Ciencia de La Computacion, Escuela de Ingenieria, Universidad Catolica de Chile, Casilla 6177, Santiago, Chile Omura Ichiro 2001 Toshiba Corp. Semiconductor Comp. Discrete Semiconductor Division 1, Komukai Toshiba-cho, Saiwai-ku Kawasaki 212-8583, Japan Orsatti Paolo 2000 TChip Semiconductors SA Via Cantonale 35A CH-6928 Manno, Switzerland Pfäffli Paul 1999 ISE Integrated Systems Engineering AG, Balgriststrasse 102, CH-8008 Zürich, Switzerland

Piazza Francesco 2000 Tchip Semiconductors SA Via Cantonale 35A CH-6928 Manno, Switzerland Pommerell Claude 1992 CH-I Information Technology ABB (Switzerland) Ltd., Brown Boveri Strasse 6, CH-5400 Baden, Switzerland Röwer Thomas 2000 IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights NY 10598 USA Rogenmoser Robert 1996 Broadcom Corp., 2451 Mission College Blvd., Broadband Processor Business Unit, Santa Clara, CA 95054, USA Rothacher Fritz 1995 Infineon Technologies, WS BB D CR FE2, P.O. Box 80 09 49 D-81609 München, Germany Rühl Roland 1992 PDF Solutions, Inc. 333 West San Carlos Street San Jose, CA 95110, USA Ryter Roland 1996 Philips Semiconductors AG, Binzstrasse 44, CH-8045 Zürich, Switzerland Schenk Olaf 2000 University Basel Department of Computer Science Klingelbergstrasse 50 CH-4056 Basel, Switzerland Schmithüsen Bernhard 2001 Integrated Systems Laboratory, ETH Zürich, CH-8092 Zürich, Switzerland Schönbächler Edgar 1998 Wallsten Medical SA, Avenue Riond-Bosson 14, CH-1110 Morges, Switzerland Scholze Andreas 2000 Integrated Systems Engineering Inc. 111 North Market Street, Suite 800, San Jose, CA 95113, USA Schuster Christian 2000 IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights NY 10598, USA Seda Steven 1993 Zurich Financial Services, Mythenquai 2, CH-8022 Zürich, Switzerland Stadler Manfred 2000 BridgeCo AG Ringstrasse 14 CH-8600 Dübendorf, Switzerland Stricker Andreas 2000 IBM Microelectronics MS 972C, 1000 Riverstreet Essex Junction, VT 05452 USA Thalmann Markus 2000 BridgeCo AG Ringstrasse 14 CH-8600 Dübendorf, Switzerland

Villablanca Luis 2000 Avant! Corp., Fremont, CA 94538, USA von Arx Christoph 1996 cva technical consulting ag, Geissfluhweg 30, CH-4600 Olten, Switzerland Wassner Jürgen 2001 Schmid Telecom AG, Binzstrasse 35, CH-8045 Zürich, Switzerland Westermann Marc 1995 Logismata AG, Hardturmstrasse 76, CH-8005 Zürich, Switzerland Wettstein Andreas 2000 ISE Integrated Systems Engineering AG Balgriststrasse 102 CH-8008 Zürich, Switzerland Wikström Tobias 2000 ABB Corporate Research AB Dept. D S-721 78 Västeras, Sweden Witzig Andreas 2002 Integrated Systems Laboratory, ETH Zürich, CH-8092 Zürich, Switzerland Witzigmann Bernd 2000 Agere Systems 2015 West Chestnut Street, Building 1 Alhambra, CA 91803-1542, USA Yun Chan-Su 2000 Integrated Systems Engineering Inc., 111 N.Market Street, Suite 710, San Jose, CA 95113, USA Zahir Rumi 1991 428 Glenwood Avenue, Menlo Park CA 94025, USA Zelenka Stefan 2001 Integrated Systems Engineering Inc., 111 N.Market Street, Suite 710, San Jose, CA 95113, USA Zimmermann Reto 1997 Synopsys, Inc. Logic Modeling Group, 19500 NW Gibbs Dr., Beaverton, OR 97006, USA

Academic Guests

Prof. N. Hitschfeld Universidad de Chile, Santiago, Chile 1 Jan - 02 Feb 2001 H. Yabuhara Toshiba Corp., Yokohama, Japan 1 Jan - 31 Dec 2001 Prof. Dr. A. Huang Virginia Polytechnic Institute and State University, Blacksburg, VA, USA 15 Jul - 31 Dec 2001 Dr. I. Omura Toshiba, Kawasaki, Japan 15 Jan - 19 Jan 2001 H. Funaki Toshiba Corporation, Kawasaki, Japan 26 Jan 2001 Prof. A. Germa Ecole Nationale Supérireure des Télécomuni- Cations, Paris, France 29 Jan 2001 M. Hamada Toshiba Corporation, Kawasaki, Japan 29 Jan 2001 T. Masaoka Toshiba Corporation, Tokyo 29 Jan 2001 K. Takenaka Toshiba Corporation, Kawasaki, Japan 29 Jan 2001 H. Tendyck Toshiba Elec. Europe GmbH, Düsseldorf, Germany 29 Jan 2001 Dr. W. Stadler Infinion Technologies, Munich, Germany 31 Jan 2001 K. Esmark Infinion Technologies, Munich, Germany 31 Jan 2001 Dr. H. Bonnenberg Micronas AG, Munich, Germany 1 Feb 2001 Dr. Ch. Heer Infineon Technologies AG, Munich, Germany 1 Feb 2001 J. Muttersbach Phonak AG, Stäfa, Switzerland 1 Feb 2001 Dr. F. Rotacher Infineon Technologies AG, Munich, Germany 1 Feb 2001 Dr. H. Yamaguchi Electrotechnical Laboratory, Ibaraki, Japan 13 Feb - 16 Feb 2001 Prof. S. Anand Royal Institute of Technology, Sweden 19 Feb - 20 Feb 2001 M. Duhajon IMEC, Leuven, Belgium 19 Feb - 20 Feb 2001 Dr. P. Formanek IHP, Frankfurt (Oder), Germany 19 Feb - 20 Feb 2001 Dr. J. Isenbarth University of Hamburg, Hamburg, Germany 19 Feb - 20 Feb 2001 Dr. A. Olbrich Infineon, Munich, Germany 19 Feb - 20 Feb 2001 Dr. V. Raineri CNR-IMETEM, Catania, Italy 19 Feb - 20 Feb 2001 Prof. Y. Rosenwaks Tel-Aviv University, Tel-Aviv, Israel 19 Feb - 20 Feb 2001 Dr. S. Sadewasser HMI-Berlin, Berlin, Germany 19 Feb - 20 Feb 2001 Prof. W. Vandervorst IMEC, Leuven, Belgium 19 Feb - 20 Feb 2001 Dr. M. Verheyen Philips, Eindhoven, The Netherlands 19 Feb - 20 Feb 2001 M. von Sprekelsen University of Hamburg, Hamburg, Germany 19 Feb - 20 Feb 2001 T. Hiraoka Toshiba Corp., Yokohama, Japan 1 Mar 2001 K. Kimura Toshiba Corp., Kitakyushu, Japan 2 Mar 2001 H. Nakajima Toshiba Corp., Yokohama, Japan 2 Mar 2001 H. Saihara Toshiba Corp., Kitakyushu, Japan 2 Mar 2001 K. Shimai Kanematsu Electronics Ltd., Tokyo, Japan 2 Mar 2001 R. Becker Philips Semiconductors AG, Zurich, Switzerland 6 Mar 2001

Dr. K. Azadet Agere Systems, Jew Jersey, USA 6 Mar 2001 Dr. J. Lorenz Fraunhofer Institut, Erlangen, Germany 6 Mar 2001 Dr. T.-P. Liu Agere Systems, Jew Jersey, USA 15 Mar 2001 Prof. Wachutka TU Munchen, Munich, Germany 5 Apr 2001 Dr. P.-L. Yeh Realtek Corp., Taipei, Taiwan 18 Apr 2001 Dr. M. Mergens Robert Bosch GmbH, Reutlingen, Germany 15 May 2001 Dr. P.-L. Yeh Realtek Corp., Taipei, Taiwan 16 May 2001 W.-H. Ouyang Realtek Corp., Taipei, Taiwan 16 May 2001 D.-C. Twu Realtek Corp., Taipei, Taiwan 16 May 2001 Y.-S. Lin Realtek Corp., Taipei, Taiwan 16 May 2001 T.-M. Su Realtek Corp., Taipei, Taiwan 16 May 2001 Dr. Y. Yamada Toyota Central R&D Labs. Inc., Aichi, Japan 28 May - 30 May 2001 Prof. Dr. S. Selberherr TU Wien, Vienna, Austria 1 Jun 2001 Dr. P. Frey INRIA, Le Chesny, France 10 Jul 2001 Prof. P.-L. George INRIA, Le Chesny, France 10 Jul 2001 Dr. G. Kiralyfalfi ISE AG, Zurich Switzerland 10 Jul 2001 Dr. J. Lorenz Fraunhofer Institut, Erlangen, Germany 10 Jul 2001 Dr. T. Schwartzmann SGS Thomson Microelectronics, Crolles, France 10 Jul 2001 Prof. Dr. E. Gornik TU Wien, Vienna, Austria 8 Aug 2001 Dr. M. Blaser Opto Speed Zurich AG, Rüschlikon, Switzerland 8 Aug 2001 Dr. W. Hunziker Opto Speed Zurich AG, Rüschlikon, Switzerland 8 Aug 2001 Dr. N. Shigyo Toshiba Corporation, Yokohama, Japan 3 Sep 2001 Dr. T. Aida ATR Adaptive Communications, Kyoto, Japan 24 Sep 2001 Dr. Y. Yamada Toyota Central R&D Labs. Inc., Aichi, Japan 28 Sep 2001 R. Goyal Intel Capital Corp., Folsom, USA 18 Oct 2001 S. Rawat Intel Capital Corp., Folsom, USA 18 Oct 2001 N. Bektas Opto Speed Zurich AG, Rüschlikon, Switzerland 22 Oct - 31 Dec 2001 L. Degiorgi Electronics Laboratory, IFE, Zurich, Switzerland 22 Oct - 24 Oct 2001 Dr. S. Eitel Avalon Photonics Ltd., Zurich Switzerland 22 Oct - 24 Oct 2001 Dr. N. Hashizume Furukawa Electric Co., Ltd., Japan 22 Oct - 24 Oct 2001 M. Isshiki Kanematsu Electronics Ltd., Tokyo, Japan 22 Oct - 24 Oct 2001 R. Kohli Integrated Systems Engineering AG, Zurich, Switzerland 22 Oct - 24 Oct 2001 N. Matuschek Nortel Networks Optical Componenets, Zurich, Switzerland 22 Oct - 24 Oct 2001 F. Monti di Sopra Avalon Photonics Ltd., Zurich Switzerland 22 Oct - 24 Oct 2001 E. Moreno Electronics Laboratory, IFE, Zurich, Switzerland 22 Oct - 24 Oct 2001 L. Nadai Furukawa Electric Institute of Technology, Hungary 22 Oct - 24 Oct 2001

S. Palmgren Institute for Micro- and Optoelectronics, EPF, Lausanne, Switzerland 22 Oct - 24 Oct 2001 Prof. Dr. J. Piprek University of California, Santa Barbara, CA, USA 22 Oct - 24 Oct 2001 Z. Puskas Furukawa Electric Institute of Technology, Hungary 22 Oct - 24 Oct 2001 Dr. M. Rottinger Integrated Systems Engineering AG, Zurich, Switzerland 22 Oct - 24 Oct 2001 Dr. B. Schmidt Nortel Networks Optical Components, Zurich, Switzerland 22 Oct - 24 Oct 2001 Dr. R. Scheieck Opto Speed Zurich AG, Zurich, Switzerland 22 Oct - 24 Oct 2001 R. Shau Walter-Schottky-Institute, TU Munich, Munich, Germany 22 Oct - 24 Oct 2001 L. Sirigu Institute for Micro- and Optoelectronics, EPF, Lausanne, Switzerland 22 Oct - 24 Oct 2001 Dr. Tikhomirov Integrated Systems Engineering AG, Zurich, Switzerland 22 Oct - 24 Oct 2001 T. Yoshida Kanematsu Electronics Ltd., Tokyo, Japan 22 Oct - 24 Oct 2001 Dr. Ch. Velez Opto Speed Zurich AG, Zurich, Switzerland 22 Oct - 24 Oct 2001 Dr. W. Vogt Opto Speed Zurich AG, Zurich, Switzerland 22 Oct - 24 Oct 2001 Dr. H. Weman Institute for Micro- and Optoelectronics, EPF, Lausanne, Switzerland 22 Oct - 24 Oct 2001 C.-M. Chou Realtek Corp., Taipei, Taiwan 31 Oct - 2 Nov 2001 Y.-S. Lin Realtek Corp., Taipei, Taiwan 31 Oct - 2 Nov 2001 W.-H. Ouyang Realtek Corp., Taipei, Taiwan 31 Oct - 2 Nov 2001 K. Agawa Toshiba Corporation, Kawasaki, Japan 20 Nov 2001 M. Hamada Toshiba Corporation, Kawasaki, Japan 20 Nov 2001 S. Kousai Toshiba Corporation, Kawasaki, Japan 20 Nov 2001 Dr. W. Stadler Infineon Technologies, Munich, Germany 10 Dec 2001 K. Esmark Infineon Technologies, Munich, Germany 10 Dec 2001 Prof. H. Melchior Freudenbergstr. 101/F1, Zurich, Switzerland 10 Dec 2001 Prof. Dr. G. Baccarani Universita degli Studi di Bologna, Bologna, Italy 11 Dec 2001 Dr. R. Wohlgemuth Siemens Schweiz AG, Wallisellen, Switzerland 13 Dec 2001 Dr. Y. Yamada Toyota Central R&D Labs. Inc., Aichi, Japan 19 Dec - 20 Dec 2001

Partners and Funding Agencies

ABB Corp. Research ABB Corporate Research Ltd. Segelhof CH-5405 Dätwil AG Switzerland ABB Semiconductors ABB Semiconductors AG Fabrikstrasse 3 CH-5600 Lenzburg Switzerland AMS Austria Mikro Systeme International AG (AMS) Schloss Premstätten A-8141 Unterpremstätten Austria AMUW Wien Universitätsklinik für Innere Medizin IV Klinische Abteilung Arbeitsmedizin Währinger Gürtel 18-20 A-1090 Wien Austria Ansaldo Ansaldo Transporti SpA Ingegneria Divisione Veicoli Via Nuove delle Brecce 260 I-80147Napoli Italy Avalon Avalon Photonics Badenerstrasse 569 CH-8048 Zürich Switzerland BBT Bundesamt für Berufsbildung und Technologie (Federal Office for Professional Education and Technology, a Swiss Government Agency) Effingerstrasse 27 CH-3003 Bern Switzerland BBW Bundesamt für Bildung und Wissenschaft (Federal Office for Education and Science, a Swiss Government Agency) Wildhainweg 9 CH-3001 Bern Switzerland Bernafon Bernafon AG Morgenstrasse 131 CH-3018 Bern Switzerland BfS Bundesamt für Strahlenschutz Willy-Brandt-Strasse 5 D-38226 Salzgitter Germany

Bosch Robert Bosch GmbH Tübinger Strasse 123 D-72703 Reutlingen Germany

and

Robert Bosch GmbH Wernerstrasse 1 D-70442 Stuttgart Germany BridgeCo BridgeCo AG Ringstrasse 14 CH-8600 Dübendorf Switzerland Cisco Cisco Systems Internatinal B.V. Hoogoorddreef 9 NL-1101 BA Amsterdam-Zuidoost The Netherlands CNR-IMETEM Consiglio Nationale di Metodolgie e Tecnologie per la Microelettronica (IMETEM) Stradale Primosole 50 I-95121 Catania Italy Concept CT-Concept Technology AG Renferstrasse 15 CH-2504 Biel Switzerland CRF Centro Ricerche Fiat SCpA Strada Torino 50 I-10043 Orbassano Italy CSEM Centre Suisse d'Electronique et de Microtechnique SA (Swiss Center for Electronics and Microtechnology, Inc.) Maladière 71 CH-2007 Neuchâtel Switzerland diAx diAx Hertistrasse 25 CH-8304 Wallisellen DS2 Diseno de Sistemas de Silicio S.L. Plaza Fadrell2, primero E-12002 Castellon Spain EDF Electricite de France 2, rue Louis Murat F-75008 Paris France Elektrovac Electrovac Fabrikation Elektrotechnischer Spezialartikel GmbH Zentrale Forschung und Entwicklung Aufeldgasse 37-39 D-3400 Klosterneuburg Germany ENSCPB Talence Ecole Nationale Supérieure de Chimie et de Physique de Bordeaux Avenue Pey Berland F-33405 Talence France

EPFL Ecole Polytechnique Fédéral Lausanne (Swiss Federal Institute of Technology Lausanne) CH-1002 Lausanne Switzerland ESD-MSD Cluster Electronic Systems Design and Mixed Signal Design Cluster Centro Nacional de Microelectrónica IMSE Avda. Reina Mercedes s/n (Edificio CICA) 41012 - Sevilla Spain ESPRIT ESPRIT Information Technology Program Directorate General XIII European Commission Rue de la Loi 200 B-1049 Bruxelles Belgium ETHZ Eidgenössische Technische Hochschule Zürich (Swiss Federal Institute of Technology Zürich) ETH-Zentrum CH-8092 Zürich Switzerland EU-GROWTH Community Research in the Fifth Framework Programme "Competitive and sustainable growth (GROWTH)" of the European Union. EU-IST Community Research in the Fifth Framework Programme "User-friendly information society (IST)" of the European Union. EU-QUAL Community Research in the Fifth Framework Programme "Quality of life and management of living resources" of the European Union. EU-RTN Community Research in the Fifth Framework Programme "Improving human research potential and the socio-economic knowledge base: Research Training Networks (RTN)" of the European Union. EUPEC EUPEC GmbH Max-Planck-Strasse 5 D-59581 Warstein Germany Ferraz Ferraz Date Industries S.A. Les Revoulin – Route de St-Honore F-38350 La Mure France FH Aargau Fachhochschule Aargau CH-5210 Windisch AG Switzerland FhG-IIS-B Fraunhofer-Institut für Integrierte Schaltungen Bauelementetechnologie Schottkystr. 10 D-91058 Erlangen Germany FNM Forschungskoperation Nachhaltiger Mobilfunk c/o Institut für Feldtheorie und Höchstfrequenztechnik (Laboratory for Electromagnetic Fields and Waves) ETH Zürich Gloriastrasse 35 CH-8092 Zürich Switzerland

HERCULAS Consortium CNR-IMEHEM, Catania (Italy) HMI, Berlin (Germany) IHP, Frankfurt (Germany) IMEC, Leuven (Belgium) KTH, Kista (Sweden) Philips Nederland, Eindhooven (The Netherlands) ST Crolles, Crolles (France) TAU, Ramat Aviv (Israel) Uni Hamburg, Hamburg (Germany) HIMRATE Consortium Ansaldo, Napoli (Italy) CRF, Orbassano (Italy) Electrovac, Klosterneuburg (Germany) EUPEC, Warstein (Germany) Ferraz, La Mure (France) INTRETS, Arcueil (France) Regienov, Guyancourt (France) Siemens München, München (Germany) TU München, München (Germany) TU Wien, Wien (Austria) HMI Hahn-Meitner-Institut Berlin GmbH Glienicker Strasse 100 D-14019 Berlin Germany HMT HMT Microelectronic AG A. Aebi-Strasse 75 CH-2503 Biel Switzerland IBM Research IBM Research Laboratory Säumerstrasse 4 CH-8803 Rüschlikon Switzerland IfE Institut für Elektronik (Laboratory for Electronics) ETH Zürich Gloriastrasse 35 CH-8092 Zürich Switzerland IFH-ETHZ Institut für Feldtheorie und Höchstfrequenztechnik (Laboratory for Electromagnetic Fields and Waves) ETH Zürich Gloriastrasse 35 CH-8092 Zürich Switzerland IFBH Hannover Institut für Biophysik Universität Hannover Herrenhäuserstr. 2 D-30419 Hannover Germany IHP Institute for Semiconductor Physics (IHP) Walter-Korsing-Strasse 2 D-15230 Frankfurt (Oder) Germany IIS Integrated Systems Laboratory ETH Zürich Gloriastrasse 35 CH-8092 Zürich Switzerland (i.e. the publisher of this “Research Review 2001”)

IKT-ETHZ Institut für Kommunikationstechnik (Laboratory for Communication Trechnology) ETH Zürich Sternwartstrasse 7 CH-8092 Zürich Switzerland IMEC Interuniversity Microelectronics Centre Kapeldreef 75 B-3001 Leuven Belgium IMT Institute de Microtechnique, Université Neuchâtel rue A.-L.-Breguet 2 CH-2000 Neuchâtel Switzerland Infineon Infineon Technologies AG Otto-Hahn-Ring 6 D-81730 München Germany

and

Infineon Technologies AG Balanstrasse 73 D-81609 München Germany

and

Infineon Technologies AG St Martin Strasse 53 D-81541 München Germany INRETS Institut National de Recherche sur les Transport et leur Sécuruité, 2, Avenue du Général Malleret-Joinville F-94114 Arcueil France INRIA Institute Natinal de Recherche en Informatique et Automatique BP 105 Domaine de Voluceau F-78153 Le Chesnay France IPK Gatersleben Institut für Pflanzengenetik und Kulturpflanzenforschung Gatersleben Correnstr. 3 D-06466 Gatersleben Germany ISE AG ISE Integrated Sysems Engineering AG Balgriststrasse 102 CH-8008 Zürich Switzerland

and

ISE Integrated Systems Engineering Inc. 111 N, Market Street Suite 710 San Jose CA 95113 USA

IT’IS IT’IS Foundation for Research on Information Technologies in Society ETHZ VAW Gebäude Gloriastr. 37/39 CH-8006 Zürich Switzerland

and

Zeughausstrasse 43 CH-8004 Zürich Switzerland IT'IS Partners ARCS, Seibersdorf (Austria) Ericsson, Stockholm (Sweden) GSM-Association, Genève, (Switzerland) IMTEK, Freiburg, (Germany) IPK-UNIZH, Zürich (Switzerland) MMF, Brussels (Belgium) Motorola, Ft. Lauderdale (USA) Nortel, Harlow (UK) IWR-ETHZ Institut für Wissenschaftliches Rechnen) (Institute for Scientific Computing) ETH Zürich Haldeneggsteig 4 CH-8092 Zürich Switzerland KTH Kungl Tekniska Högskolan Department of Electronics - Laboratory of Semiconductor Materials Isafjordsgatan 22-26 S-16440 Kista Sweden KTI Kommission für Technologie und Innovation (Commission for Technology and Innovation, a Swiss Government Agency) Effingerstrasse 27 CH-3003 Bern Switzerland Lucent Lucent Technologies Wireless Research Department 791 Holmdel-Keyport Road Holmdel, NJ 07733-400 USA MATH-ETHZ Forschungsinstitut für Mathematik (Research Institute for Mathematics) ETH Zürich Rämistrasse 101 CH-8092 Zürich Switzerland Microdul Microdul AG Grubenstrasse 9 CH-8045 Zürich Switzerland MPG Stuttgart Max-Planck-Institut für Festkörperforschung Heisenbergstasse 1 D-70565 Stuttgart Germany

Nortel Networks Nortel Networks Optical Components (Switzerland) AG Binzstrasse 17 CH-8045 Zürich Switzerland NTT Nippon Telegraph and Telephone Corporation 3-1, Otemachi 2-Chome, Chiyoda-Ku Tokyo Japan Opto Speed Opto Speed AG Moosstrasse 2 CH-8803 Rüschlikon ZH Switzerland PERFORM A Consortium Partners of the research project "PERFORM A - In vivo Research on possible Health Effects related to Mobile Telephones and Base Stations" FhG-ITA, Hannover (Germany) RCC, Ittingen (Switzerland) ARCS, Seibersdorf (Austria) RBM, Colleretto Giacosa (Italy) IT'IS, Zürich, Switzerland RCL/AUTH, Thessaloniki, Greece Philips Nederland Philips Electronics Nederland B.V. Professor Holstlaan 4 NL-5656 AA Eindhoven The Netherlands Philips Zurich Philips Zürich AG, Semiconductors Binzstrasse 44 CH-8045 Zürich Switzerland REFLEX Consortium AMUW Wien, Wien, Austria) ENSCPB Talence, Talence (Belgium) IFBH Hannover, Hannover (Germany) IPK Gatersleben, Gatersleben (Germany) STUK Helsinki, Helsinki (Finland) UKFB Berlin, Berlin (Germany) UMIL Milano, Milano (Italy) Uni Bologna, Bologna (Italy) VERUM, München (Germany) VERYC Madrid, Madrid (Spain) Regienov Regienov – Renault Recherche et Innovation 1, Avenue du Golf F-78288 Guyancourt France Siemens München Siemens AG Otto-Hahn-Ring 6 D-81730 München Germany SNF Swiss National Science Foundation Wildhainweg 20 CH-3012 Bern Switzerland SPEAG Schmid & Partner Engineering AG Zeughausstrasse 43 CH-8004 Zürich Switzerland

ST Crolles ST Microelectronics 850 rue Jean Monnet F-38921 Crolles France ST Gentilly ST Microelectronics 937 Avenue Gallieni F-94253 Gentilly France STUK Helsinki STUK – Radiation and Nuclear Safety Authority Laippatie 4 FIN-00880 Helsinki Finland TAU Tel-Aviv University (TAU) Department of Physical Electronics Tel-Aviv University, Ramat Aviv IL-69978 Israel TIK-ETHZ Institut für Technische Informatik ETH Zürich Gloriastr. 35 CH-8092 Zürich Switzerland TOP NANO 21 Swiss Technology Oriented Program NANO 21 Universität Basel Institut für Physik Klingelbergstrasse 82 CH-4056 Basel Switzerland

and

Themas AG Egnecherstasse 69 CH-9320 Arbon Switzerland

Toshiba Toshiba Corporation 1-1. Shibaura 1-chome, Minato-ku Tokyo 105 Japan

and

Toshiba Corporation 2-5-1, Kasama, Sakae-ku Yokohama 247-8585 Japan

and

Toshiba Corporation 1, komukai, Toshibacho, Saiwai-ku Kawasaki 210 Japan

Toyota Toyota Central R&D Labs. Inc. Nagakute-cho, Aichi-gun Aichi 480-1192 Japan

TU München Technische Universität München Lehrstuhl für technische Elektrophysik Arcisstrasse 21 D-80290 München Germany

and

Technische Universität München Walter Schottky Institut E26 Am Coulombwall D-85748 Garching Germany TU Wien Technical University Vienna Institute for Microelectronics Gusshausstrasse 27-29 A-1040 Wien Austria

and

Technical University Vienna Department of Materials Science and Testing Karlsplatz 13 A-1040 Wien Austria UKBF Berlin Universitätsklinikum Benjamin Franklin der freien Universität Berlin Institut für klinische Chemie und Pathobiochemie Hindenburgdamm 30 D-12200 Berlin Germany UMIL Milano Universita degli Studi di Milano Dipartimento di Farmacologia Via Vanvitelli 32 I-20129 Milano Italy Uni Bologna Universita degli Studi di Bologna Dipartimento di Elettronica Informatica e Sistemistica Via Zamboni 33 I-40126 Bologna Italy

and

Universita degli Studi di Bologna Dipartimento di Fisica Viale Berti Pichart 6/2 I-40127 Bologna Italy Uni Cork University College Cork National Microelectronics Research Centre Lee Maltings, Prospect Row Cork Ireland Uni Hamburg Universität Hamburg Institut für Angewandte Physik Jungius-Strasse 11 D-20335 Hamburg Germany

Uni Linz Johannes Kepler Universität Linz Institute for Communications and Information Engineering Altenbergstrasse 69 A-4040 Linz Austria Uni Pisa Universita degli studi di Pisa Dipartimento di Ingegneria della Informazione: Elettronica, Informatica, Telecomunicazioni Lungarno Pacinotti 43/44 I-56126 Pisa Italy Uni Würzburg Bayerische Julius-Maximilians Universität Würzburg Sanderring 2 D-97070 Würzburg VERUM Stiftung für Verhalten und Umwelt Pettenkoferstr. 33 D-80336 München Germany VERYC Madrid Investigacion Bioelectromagnetismo Hospital Ramon y Cajal Carretara de Colmenar km.9 E-28034 Madrid Spain WIAS Weierstrass-Institut für Angewandte Analysis und Stochastik Mohrenstrasse 39 D-10117 Berlin Germany

Awards

Qiuting Huang

has been elected to the grade of IEEE Fellow

for outstanding contributions to integrated circuits for wireless communications.

Christian Schuster* and Wolfgang Fichtner

Received the Best Paper Award IEEE Transactions on Electromagnetic Compatibility 2001

Parasitic Modes on Printed Circuit Boards and their Effects on EMC and Signal Integrity, pp 416-425, November Issue, 2001.

*(now with IBM Research Center, Yorktown Heights, USA)

Andreas Witzig

was awarded with a Scholarship for a Research Project

in the Exchange Program of ETH Zurich, Switzerland with the University of California, Santa Barbara, USA

Peter Lüthi

received the first AMD Fab 30 Vice President's Award

for the outstanding results and excellent documentation of his master thesis (ETH Diploma) "Performance Analysis of AMD Southbridge Zorak".

Patents

Title: Method for Testing Integrated Circuits

Owner: Philips Semiconductors Inventors: Norbert Felber, Hubert Kaeslin

Patent No.: additional US Patent Application following the European Patent Application 00124076.1

Title: Reference Time Distribution Over a Network

Owner: BridgeCo AG Inventors: Thomas Thaler, Georg Dickmann, Eric Roth Christoph Heidelberger

Patent No.: PCT / IB01 / 00368 (International); 09/785.598 (US) WO0161898 (Publication No., international)

Title: Multi-Portal Bridge for Providing Network Connectivity

Owner: BridgeCo AG Inventors: Thomas Thaler, Georg Dickmann, Thomas Boesch, Manfred Stadler, Marcel Dasen, Christoph Heidelberger

Patent No.: PCT / IB01 / 00433 (International); 09/784,831 (US) WO0161939 (Publication No., international)

History of the Integrated Systems Laboratory (IIS)

1985 Appointment of Wolfgang Fichtner, Professor for Electronics, Department of Electrical Engi- neering ETH Zurich. Formation of the research group "VLSI" in the Electronics Laboratory. First research project (2D device simulation, funded by KTI). Installation of 3 minicomputer DEC VAX-11/785 (1 CPU, 16 MBytes memory).

1986 Foundation of the "Integrated Systems Laboratory" by merging of the research groups of Prof. Wolfgang Fichtner (Department of Electrical Engineering) and Prof. Martin Morf (De- partment of Computer Science). Start of the lecture "Electronics Systems" (undergraduate EE students). Start of the lecture series "Design of Integrated Circuits I, II, III" (graduated EE, CS and physics students). Summerschool "VLSI Design" in Beatenberg/Switzerland (2 weeks, 85 participants from Europe and Switzerland), organization as well as scientific and technical responsibility by IIS. 15 invited talks by well known experts from USA, Europe and Switzerland, presentations and hands-on experience on workstations.

1987 Leaving of Prof. Martin Morf. Appointment of Marco Annaratone, assistant professor for Parallel Computing, Department of Computer Science ETH Zurich. Start of the lecture "Digital Design and Processor Structures" (undergraduate CS students). Design and integration of the first student ICs (20 MHz, 7,000 transistors). Installation of the HILEVEL TOPAZ 50 ASIC test system (50 MHz, 96 I/O channels). Installation of a mini-supercomputer Alliant FX/80 (6 CPUs, 112 MBytes shared memory). Introduction of the first professional CAD tool for IC design in teaching and research (VLSI Technology Inc., later Compass Design Automation Inc.). Installation of the parallel computer Sequent Symmetry (26 CPUs, 160 MBytes shared memory).

1988 Foundation of the Microelectronics Design Center (Department of Electrical Engineering, associated to the Integrated Systems Laboratory). First PhD thesis of a computer science student at IIS. Design and integration of the first VLSI chip (Viterbi decoder, 35,000 transistors).

1989 First European research project (parallel computer architecture). First PhD thesis of a physics student at IIS. 2nd prize "Seymour Cray Competition" Switzerland for "Multi-dimensional Semiconductor Device Simulation" to members of scientific staff of IIS. First "Intensive Course on ASIC Design and Test" with ETH-internal and -external participants. First functional 2D simulation program for semiconductor devices developed by IIS scientific staff.

1990 First PhD thesis of an electrical engineering student at IIS. Start of the lecture "Semiconductor Devices: Technology and Modeling". CEI-Europe Elsevier course "VLSI Process and Device Simulation" in Davos/Switzerland. Organization as well as scientific and technical responsibility by IIS (1 week, 35 participants). Start of the project "Education and Research in Microelectronics", generous funding by the board of ETH Zurich for IC integration and measurement equipment.

Evaluation of the Department of Electrical Engineering ETH Zurich and the laboratories of the Department by a group of international experts. Qualification of the research at the Integrated Systems Laboratory compared at the international level: • process and device simulation: outstanding. • VLSI: design: very efficient. • parallel computer architectures: very good ideas, realization has to be proven. Prof. Wolfgang Fichtner elected to IEEE Fellow for the "application of numerical modeling to device scaling and submicron transistor optimization".

1991 Leaving of Prof. Marco Annaratone. 4th International Conference on "Simulation of Semiconductor Devices and Processes - SISDEP'91", ETH Zurich/Switzerland (3 days, 200 participants), organization by IIS, Confer- ence Co-Chairman Prof. Wolfgang Fichtner, 3 invited papers, 44 regular papers, 18 poster presentations. Start of the national program "Microswiss" to support microelectronics in Swiss SMEs and education. Microelectronics Design Center acted as a support center. Presentation of the IIS activities in "Modeling of Microelectronic Devices" at CEBIT'91 exhibition Hannover/Germany, as a winner of the competition "Technology Location Switzerland 1991". Installation of the IMS XL60 Mixed Signal ASIC Verification System (60 MHz, 96 I/O channels).

1992 Start of the Swiss priority program "LESIT - Power Electronics, Systems, Information Tech- nology", 11 research projects in the module "Silicon Power Device Technology" (module co- ordinated by Prof. Wolfgang Fichtner). Start of the first European ESPRIT project ("DESSIS - Device Simulation for Smart Inte- grated Systems"). Start of a European JESSI project (Circuits for Communication Technology). Design and integration of a high-speed data encryption IC (177 Mbit/sec, 250,000 transistors). First functional 3D grid generation program developed by IIS scientific staff.

1993 Appointment of Qiuting Huang, assistant professor for Analog Integrated Circuits, Depart- ment of Electrical Engineering ETH Zurich. Foundation of the IIS spin-off "ISE Integrated Systems Engineering AG" Zurich by IIS members (scope of business: software and application support in Technology CAD). Location for the first one and a half years at IIS with support of ETH Zurich. Start of the lecture "Analog Integrated Circuits" (graduated EE students). First functional 3D simulation program for semiconductor devices developed by IIS scientific staff.

1994 "6th International Symposium of Power Semiconductor Devices & ICs - ISPSD'94", Davos/Switzerland (3 days, 195 participants), organization by IIS, symposium chairman Prof. Wolfgang Fichtner, 3 invited presentations, 29 regular papers, 41 poster presentations. Planing phase of the Swiss priority program MINAST, designated program director Prof. Wolfgang Fichtner (1994/95), provisional program direction established at IIS. Installation of the HP83000 ASIC Verification System (660 MHz, 128 I/O channels). Microelectronics Design Center also assumes responsibility for PCB support.

1995 Completion of the Swiss priority program LESIT with outstanding scientific results and efficient transfer of research to industry. First functional simulation program for semiconductor processes developed by IIS scientific staff. Move of spin-off ISE AG from ETH Zurich location to Technopark Zurich. First course "Getting started with VHDL Synthesis" with ETH-internal and -external participants.

Installation of the parallel computer IBM SP2 (6 CPUs, 4.5 GBytes distributed memory).

1996 Start of the Swiss priority program "MINAST - Micro and Nano System Technology", program director Prof. Wolfgang Fichtner (1996-1997), program direction established at IIS, total 56 Mio CHF granted by Swiss authorities and more than 60 Mio CHF contributions from Swiss industrial enterprises; IIS research projects: 2 in the module "Integrated Microsystems Tech- nology", 4 in the module "Design, Simulation and Engineering of Microsystems" and 1 in the module "Microsystems Applications".

1997 Postdoctoral thesis (habilitation) of PD Dr. Andreas Schenk for the subject "Advanced Physi- cal Models for Silicon Device Simulation". Public workshop "3D Semiconductor Simulation" of the European ESPRIT Project "PROMPT II -Process Optimization in Multiple Simulations for Semiconductor Technology II" (3 days, 56 participants), Monte Verità Ascona/Switzerland, 8 presentations as well as demonstrations and hands-on experience, organization by IIS and spin-off ISE AG. Installation of the first parallel computer DEC Alphaserver (4 CPUs, 2 GBytes shared memory).

1998 Promotion of Qiuting Huang to Professor for Electronics, Department of Electrical Engineer- ing ETH Zurich. Accommodation of the research group "Physical Characterization" including well known experts and advanced equipment from the former Reliability Laboratory at the Department of Electrical Engineering, ETH Zurich. Start of 3 new European research projects. 2 patents on telecommunication ICs, inventors: IIS scientific staff, owner: Siemens Schweiz AG. Migration to Synopsys and Cadence EDA systems for IC design in teaching and research. First functional simulation program for electromagnetic fields developed by IIS scientific staff.

1999 Accommodation of the research group "Bioelectromagnetics/EMC" from the Electromagnetic Fields and Microwave Electronics Laboratory at the Department of Electrical Engineering, ETH Zurich. Election of Prof. Wolfgang Fichtner as head of the Department of Electrical Engineering Oct 1999 - Sep 2001. Start of the lecture "Electrical Engineering I" (undergraduated mechanical and process engineering students). Completion of the Swiss priority program MINAST with outstanding scientific results and efficient transfer of research to industry. Public workshop "ESD Protection Design Methodology" of the ESPRIT Project ESDEM as an open meeting of the "EMC '99 Zurich Symposium", (1 day, 86 participants), ETH Zu- rich/Switzerland, 5 invited talks by well known experts from USA and Europe, demonstrations of the methodology, organization by IIS and spin-off ISE AG. Design and integration of a high-quality video image processor (100 MHz, 1.8 Giga Ops/sec, 2.7 Mio transistors). Establishment of the "Foundation for Research on Information Technologies in Society – IT'IS" (Zurich, director Dr. Niels Kuster,). Associated to ETH Zurich and a close research partner of the IIS research group Bio Electromagnetics/EMC.

2000 Graduation of no less than 21 PhD students at IIS due the conclusion of the 4th framework program of the European Union as well as the Swiss priority program MINAST. IEEE Andrew S. Grove Award of the Year 2000 to Prof. Wolfgang Fichtner "For outstanding contributions to semiconductor device simulations". World's first chip of relevant complexity in GALS (Globally Asynchronous Locally Synchro- nous) technique, a SAFER SK-128 cipher implementation. Ultra low offset (200 nV) chopper amplifier. First functional simulation program for semiconductor lasers by IIS scientific staff.

Simulation platform SEMCAD for design and optimization of antennas in complex environments by IIS and IT'IS scientific staff. Evaluation of the Department of Electrical Engineering ETH Zurich by a group of international experts with high scientific reputation. Overall qualification: "The international standing of In- tegrated Systems Laboratory regarding its core activities is definitely among the best of the world." Introduction of a new organization structure of ETH Zurich with autonomous departments and global budget.

2001 Prof. Qiuting Huang elected to IEEE Fellow for outstanding contributions to integrated circuits for wireless communications. Election of Prof. Wolfgang Fichtner as head of the Department of Electrical Engineering Oct 2001 - Sep 2003. Start of the lecture "Semiconductor Devices" (undergraduated EE students). Start of the lecture "Communication Electronics" (undergraduated EE students). Start of the lecture series "Optoelectronic Devices" (graduated EE students). Three contributions from IIS to the new Project Oriented Work program (undergraduated EE students). Configurable hardware optimization and timing recovery for the first multimedia chip of the research partner company BridgeCo AG. 13.5 mW 185 MSample/s Delta-Sigma Modulator for UMTS/GSM Dual-Standard IF Recep- tion. Completition of the European research project SUBSAFE with excellent review results. First functional optical eigenmodes solver for Vertical-Cavity Surface-Emitting Lasers (VCSELs). ESPRIT-Project MADBRIC One-Day "Workshop on A/D Converters for Telecommunication" in Pfäffikon, Switzerland with 42 participants from 12 different countries. Pilot User Workshop "Simulation of Semiconductor Laser Devices" at ETH Zu- rich/Switzerland (2 days, 29 participants from Europe, USA and Japan), 3 invited talks by well known experts from USA and Europe, 5 talks, 1 tutorial, computer lab, organization by IIS.

40 Research Projects

IC and System Design and Test

Coordinator:

Norbert Felber

43 GALS: Globally-Asynchronous Multi-Point Interconnects for Locally-Synchronous System Globally-Asynchronous Design Locally-Synchronous Systems

Personnel: Stephan Oetiker, Thomas Villiger, Personnel: Thomas Villiger Frank Gürkaynak

Funding: KTI-4897.1 IRRQ, Funding: Infineon, KTI-4897.1 IRRQ Philips Zurich, Infineon

Partners: Philips Zurich, Infineon Partners: Infineon, Philips Zurich

The demand for smaller and cheaper products with ever In Globally-Asynchronous Locally-Synchronous (GALS) more functionality asks for integration of large systems on Systems the interfacing between a functional module and a single chip. New technologies support this demand by its self-timed environment is handled by the self-timed drastically enhancing transistor density, but long develop- wrapper. A library of predesigned technology-indepen- ment cycles for such systems contradict the hard require- dent elements simplifies the assembly of such wrappers. ment of short time-to-market. The key to resolve this So far, wrappers for point-to-point connections can be contradiction is modular design, re-use of approved func- generated almost automatically. tional blocks, and the application of purchased virtual In many applications however, a shared system bus or components. While the increase in area and operation other forms of multi-point data exchange are key compo- speed already make clock distribution difficult, the multi- nents for modularly designed Systems-on-a-Chip (SoC). tude of clock frequencies and design strategies of the Different interconnection topologies are being considered modular units prohibit any global clocking solution. to enhance the current GALS technique. Two versions are The Globally-Asynchronous Locally-Synchronous design studied in more detail within this project: methodology (GALS) is a possible answer to the problem. It enables systems consisting of several independent The first one is a shared bus solution. It is realized by ex- modules, each of which has been designed independent- tending the port controllers that manage the self-timed ly, with available, well known methodologies and tools. data transfers between different GALS modules. The abil- ity of proper arbitration for the shared bus resources is GALS design encloses each module by a wrapper which added in order to support multiple transmitters and receiv- handles the interfacing between synchronous islands in a ers. Arbitration as well as address decoding are handled self-timed manner. The local clocks are generated inside centrally for sake of area and power efficiency. the wrappers, in a way to enable metastability-free data exchange between GALS modules. The second variant is a ring topology. All nodes are connected by a circular path. At each node local address de- coders decide whether a received data word is allotted to the local synchronous module or whether it is to be passed on to the successor node. Dedicated self-timed GALS ring transceivers are developed which are able to decouple the synchronous island from the ring’s timing.

Block-level schematics of two GALS multi-point intercon- Two communicating locally synchronous islands. nection solutions.

44 Testability of Globally-Asyn- Clock Generators for Globally- chronous Locally-Synchro- Asynchronous Locally-Syn- nous Wrapper Modules chronous Wrapper Modules

Personnel: Frank Gürkaynak Personnel: Stephan Oetiker, Frank Gürkaynak

Funding: KTI-4897.1 IRRQ, Funding: KTI-4897.1 IRRQ, Philips Zurich Philips Zurich, Infineon

Partners: Philips Zurich Partners: Philips Zurich, Infineon

Globally-Asynchronous Locally-Synchronous (GALS) ar- One of the major advantages of Globally-Asynchronous chitectures have the potential to overcome clock distribu- Locally Synchronous (GALS) systems is the reduction of tion and synchronization problems associated with the power consumption by avoiding the global clock tree, design of large Systems on a Chip (SoC). This project ad- which can be responsible for dissipating up to 30 per cent dresses the testability problem of GALS-based systems of the chip’s total power consumption. While the pausable which has not been solved so far. ring oscillator used in our first GALS designs certainly met the requirements of low power dissipation, it could not ful- A new functional test methodology has been developed to fill the expectations on frequency resolution which is nec- provide testability for the GALS system. In this methodol- essary to get optimum performance. ogy, each GALS module is augmented by a test extension element, that allows a centralized test controller to access In this project, a test chip has been developed which con- the GALS module. The test controller can activate individ- tains 24 different oscillator architectures. The oscillators ual data transfer channels between GALS modules. Test- consist of standard cells routinely available in any stan- ing is achieved by observing correct data transfers dard cell library. Some newly developed standard cells between GALS modules. are applied too. The implemented variants are designed to achieve sub gate-delay resolution. They include delay- This methodology calls for customized test extension ele- banks of tristatable inverters, cascaded phase blender cir- ments for all GALS modules within a system. This is cuits, digitally controlled capacitive loads, and several de- achieved by a design and test automation script that au- lay slice alternatives. The oscillators can be configured tomatically generates all test related hardware and as- individually either over an RS232 interface or directly sembles the entire GALS system through multiplexed pins. In conjunction with an FPGA this chip can therefore be used to develop adaptive delay adjustment strategies based on reference clocks and PLLs. The picture shows a simulation of a cascaded phase blender, considering the interconnect capacities.

Basic flow diagram of the GALS design and test automa- Post-layout simulation of a cascaded phase blender: Ris- tion script. ing edges dependent on programmed delay.

45 Multimedia Network Chips Reconﬁgurable Hardware Accelerator for Real-time Multi- media Data Processing

Personnel: Eric Roth, Thomas Boesch Personnel: Thomas Boesch TIK-ETHZ: Alex Maxiaguine, Philipp Blum BridgeCo: Markus Thalmann

Funding: KTI-4957.2 LANWAN, Funding: KTI-4957.2 LANWAN, BridgeCo BridgeCo

Partners: BridgeCo, TIK-ETHZ Partners: BridgeCo, TIK-ETHZ

Multimedia networks that transport real-time digital audio Multimedia data processing devices have to deal with and video content require special network devices. This high data bandwidth and processing-intensive tasks like KTI project consists of several sub-projects investigating decompression, compression, ciphering and signal pro- the problems of such network devices. cessing. This requires dedicated high-performance Two sub-projects focus on the problems of reference-time ASICs. At the same time the huge amount of different and distribution over the network and clock recovery: To pro- changing algorithms, the high development risk and high vide high-quality real-time transportation of audio and vid- cost of dedicated chip designs ask for programmable so- eo data very precisely synchronized clock sources are lutions. indispensable. The problems of transporting time informa- In this project run-time reconfigurable hardware acceleration over the network are investigated in the first, those of tors together with a general purpose host-CPU are fore- their application by means of low-cost, low-jitter clock seen to provide superior performance and flexibility for generation circuits in the second sub-project. multimedia network devices. The host CPU is used to run The third topic concerns run-time reconfigurable hard- the operating system, to control the dataflow, and to con- ware accelerator engines. They aim at providing high pro- figure the accelerators. The hardware accelerators oper- cessing performance for decoding, encoding, encryption ate on the data streams and deliver the required signal and signal processing. The hardware accelerator consists processing performance. of several small signal processors with adaptable instruction sets. Each processor contains reconfigurable hard- The hardware accelerator consists of several small retar- ware structures and is retargetable to a specific task at getable signal processors with dynamically reconfigurable run-time. instruction sets. Each processor can be reconfigured at In the fourth sub-project the software development envi- run-time and optimized for a specific task by adding new ronment for complex multimedia network devices with specialized instructions to the basic instruction set. A re- host CPU and reconfigurable hardware accelerators is configurable hardware mesh within the processor per- developed. The problems of integrating a host CPU and forms operations previously defined and configured by the reconfigurable hardware accelerators in one user-friendly programmer. A high-bandwidth shared memory is used to programming environment are investigated. buffer the data streams and to interconnect the processors and the on-chip bus.

Host-CPU and reconfigurable hardware accelerators on Multimedia Network. a System-on-Chip.

46 Synchronization of an All-Digital Standardcell-Based IEEE-1394 Network for Audio PLL for Audio and Video and Video

Personnel: Eric Roth Personnel: Eric Roth BridgeCo: Georg Dickman

Funding: KTI-4957.2 LANWAN, Funding: KTI-4957.2 LANWAN, BridgeCo BridgeCo

Partners: BridgeCo, TIK-ETHZ Partners: BridgeCo, TIK-ETHZ

Its Quality-of-Service capabilities has established the The growing popularity of digital multimedia consumer IEEE-1394 bus (FireWireTM) as the superior technology equipment such as video cameras, DVD players, and Hi- for multimedia content transportation. In order to stream Fi systems increases the demand for an interconnectivity audio data, data rates at the sending nodes and the re- network between these devices. Distribution of real-time ceiving nodes must be aligned to prevent buffer overflows multimedia data over such a network requires alignment and underflows. The goal of this project is to investigate of data rates at the sending and receiving nodes in order and develop synchronization methods that align phase to prevent data losses due to buffer overflows and under- and frequency of all sample clocks on the network. flows. Timing information is broadcast through the IEEE-1394 Phase-locked loops (PLL) are commonly used to synchro- network such that bus nodes can adjust their sampling nize phase and frequency of clocks to a reference clock. rates to a common reference. Variable transmission laten- Classical PLLs deploy an analog VCO that often cannot cy of timing packets causes jitter that must be removed be integrated on standard digital CMOS ASICs. The goal before timing information can be used as audio clock. of this project is the development of a digital PLL that has Several approaches have been analyzed for different net- a jitter performance comparable to the analog counterpart work configurations with respect to time accuracy, jitter and that consists exclusively of standard cell library ele- performance, and reliability. ments available in any digital CMOS technology. To analyze the problems and verify the feasibility a very flexible clock recovery circuit has been realized. It draws The most critical element of a digital PLL is the digitally the precision from a quartz oscillator and uses a (so far controlled oscillator DCO. A new DCO principle has been partially) on-chip phase-locked loop to re-generate the developed to gain high frequency resolution and low jitter. high-quality audio clock. The edges of a fixed-frequency input clock are constantly shifted using a digitally controlled delay line. The amount of the phase shift defines the frequency offset of the output clock relative to the input clock.

Typical IEEE-1394 network application with transmission of audio data (top) and jitter of timing packets (bottom) Circuit diagram of digital PLL (top) and principle of devel- when transmitted through the network. oped DCO (bottom).

47 New Wireless Communication UMTS-MIMO-Transceiver Systems

Personnel: Andy Burg, David Perels, Boris Glass Personnel: Andy Burg, David Perels

Funding: Lucent, ETHZ Funding: Lucent, ETHZ

Partners: Lucent, IKT-ETHZ Partners: Lucent

Mobile Communication is gaining importance in today’s The upcoming Universal Mobile Telecommunications societies, markets, as well as in the research community. Standard (UMTS) is the first step towards truly mobile To meet the new requirements posed by future multime- multimedia communication. However the latest studies dia telecommunication services, data rates need to be in- show that it will not provide enough capacity to support creased. Since the radio bandwidth available remains high-bandwidth applications for a large number of users in constant while the number of users is ever increasing, the real environments. Spatial multiplexing is a new technique network capacity must be enhanced. that uses multiple antennas at both the transmitter and receiver to directly increase data rates in rich scattering en- Exploring space-and time diversity allows to develop new vironments. This technique is often referred to as MIMO algorithms to optimize the data rate and estimate the cur- (Multiple Input/Multiple Output). rent channel quality between the transmitter and receiver. One major field to investigate are MIMO (Multiple Input In this project which is a collaboration with the Lucent/ Multiple Output) techniques, which allow to increase the Bell-Labs Wireless Research group in New Jersey (USA), data rates drastically while truly enhancing the capacity of MIMO concepts have been integrated into the UMTS wireless networks. These systems are characterized by downlink. In a first step the necessary modifications to the multiple antennas on both the receiver and transmitter UMTS standard were investigated and simulations were side. The goal is to develop and demonstrate a working carried out for initial performance assessments. These real-time prototype of a MIMO system based on the showed promising results, giving raise to the hope that the UMTS standardization framework. theoretically predicted gains could actually be realized. In the next phase of the project a prototype of such a system The basic modulation techniques investigated are CDMA was developed. It consists of an RF frontend, a digital (Code Division Multiple Access) as used for UMTS, as multi-antenna receiver frontend and the MIMO decoder. well as OFDM (Orthogonal Frequency Division Multiplex- The latter two parts were realized on FPGAs and DSPs. ing) as a possible candidate for fourth generation mobile The implementation uses four antennas at the transmitter telecommunication systems. and at the receiver side. This configuration is theoretically Investigations are focused on VLSI feasibility. The re- able to increase the throughput by a factor of four com- search is conducted in collaboration with partners outside pared to a standard UMTS downlink with a single transmit as well as inside the ETH. IIS’ first experiences with adap- and receive antenna. tive receiver antenna arrays stem form a project that re- The main project parts of IIS were the realization and op- sulted in an efficient architecture well suitable for ASIC timization of the complete receiver frontend and contribu- implementations (see page 49 left). tions to the optimization of the MIMO decoder for real-time operation. The system has been completed and is currently being used for real-time measurements under real- world conditions.

Time-variant MIMO channel profile and possible use case for high-speed data applications. UMTS-MIMO receiver diagram and prototype.

48 IP Core for Real-Time Solution Lower Bounds on Power Dissi- of Least Squares Problems pation in Digital VLSI using CORDIC and QRD-RLS

Personnel: Boris Glass Personnel: Jürgen Wassner

Funding: ETHZ Funding: KTI-5025.1 DSP, Bernafon

Partners: Ascom Partners: Bernafon

A frequent problem in science and engineering is to fit a With ongoing advances of semiconductor technology, theoretical model to observations that suffer from errors. power dissipation has been moving higher on the list of The Least Squares Method is the most common approach VLSI design constraints. Today it is at or near the top of to an optimal solution. Mathematicians investigated the this list, notably for ICs in portable equipment where bat- problem for over 200 years. Nowadays image processing, tery lifetime is of major concern. robotics or communications are demanding real-time so- An compelling question arising in this context is the exist- lution of least squares problems. ence of an absolute lower bound on power dissipation. The combination of QR (triangular) Decomposition and Besides its theoretical significance such a lower bound Recursive Least Squares computation is known as the would also provide useful guidance for practical low-pow- QRD-RLS algorithm. It is robust and effective. And it is er design. Knowing the minimum dissipation achievable well suited for an efficient VLSI implementation based on for certain operations would allow to rate the energy effi- a systolic array of CORDIC processors. ciency of state-of-the-art implementations for these oper- The developed CORDIC processor array is reusable as ations. Implementations with poor energy efficiency Virtual Component (VC) in other applications since it is should then be prime candidates for future optimization largely scalable. A graphical user interface has been de- efforts. veloped to easily handle all parameters during design: To tackle the lower bound problem, a systematic view of Transformations from fully parallel to fully sequential pro- minimum power dissipation in consideration of data statis- cessing can be selected for one or several cascadable tics has been developed, which culminates in a classifica- chips. This enables customizations that closely meet the tion of this problem. The lower bound for data requested throughput with minimal area consumption. A transmission is directly related to the minimum switching preview shows the resulting architecture as well as the ar- activity achievable by proper encoding, and, can be given rays’ overall area. Finally, the systolic CORDIC array can analytically using information-theoretic arguments (see be exported as Matlab and VHDL source.. figure). On the other hand, it has been shown that a useful lower bound on the dissipation of an arbitrary data processing task can not be derived without knowledge of its optimal implementation, which in general is unknown. In this case, existing information-theoretic bounds do not provide adequate means for solving the problem of a lower bound on power dissipation.

Illustration of the QR Decomposition (top), graphical user interface of the systolic array generator (middle), a graph representation of the scheduling and binding problem Lower and upper bounds on the switching activity of a (bottom), and a chip photograph in the background. data stream achievable by encoding.

49 Control of Combined Parallel/ Series-Connected IGBTs

Personnel: Jan Thalheim

Funding: ETHZ, KTI-3367.1 SIGU

Partners: CONCEPT

For high-voltage high-current power converters, it may be necessary to realize a switch by connecting smaller devices in parallel and series. Beyond higher voltage and current capability, this approach also helps to achieve high availability, high-frequency operation, and low cost due to built-in redundancy, reduced dynamic losses, and the use of modular standardized units. Insulated Gate Bipolar Transistors (IGBTs) are very convenient to realize such units because of their quasi-linear controllability via a gate terminal. In this project it has been proposed to provide each IGBT driver with a primary local control which is monitoring and adjusting the IGBT’s static and dynamic behavior. Sec- ondary control is then realized to synchronize the operation of multiple IGBTs. The discovery of a globally synchronous signal, that can be derived locally, makes it possible to use low-cost low-bandwidth data links between series-connected units. Furthermore, a flexible master-slave approach can avoid the need of a dedicated global controller. That is, the entire system becomes man- ageable by the local gate drive circuitry. A prototype ASIC has been fabricated in CMOS technology with high-voltage extension. The gate driver is partitioned into fourteen clusters with a measured gate current capability of 1A each. It allows for real-time reconfigura- tion of the structure to optimize the dynamic response of the system.

ASIC for dynamic control of series-connected IGBTs.

50 Research Projects

Analog and Mixed-Signal Design

Coordinator:

Qiuting Huang

51 Transmit I/Q Modulator for Baseband Circuits for Direct UMTS (Universal Mobile Conversion UMTS Mobile Telecommunications System) Receiver

Personnel: Gabriel Brenna Personnel: Jürgen Rogin

Funding: BBW, EU-IST-11828 LEMON Funding: BBW, EU-IST-11081 LEMON

Partners: Infineon, Uni Linz Partners: Infineon, Uni Linz

Third-generation cellular radio networks based on WCD- In the near future, 3rd generation mobile services based MA are poised to come into service within a couple of on UMTS (Universal Mobile Telecommunications Sys- years. Recently, receiver IC’s in both BiCMOS and SiGe tem) will hit the market. To allow a smooth migration from BiCMOS technologies have been reported for the new today’s systems such as GSM, multi mode mobile termi- standard. nals will be required. To keep their size competitive, the highest integration level must be sought, leading naturally The goal ofthis overall project is to demonstrate the fea- to zero IF receiver structures, eliminating most bulky pas- sibility ofa highly integrated UMTS transceiver in deep sive filters. submicron CMOS technology using a direct-conversion architecture in the receive as well as the transmit path. In this project, a single chip zero IF transceiver is being developed. In the zero IF concept, the Rx baseband In the transmit path, to minimize the carrier leakage, a blocks are a crucial part because they have tougher noise double-balanced, current-commutating mixer is used for and linearity requirements due to less gain and filtering in the upconversion. The implemented mixer topology guar- front of them, and because they suffer from offset prob- antees a wide and accurate gain control range, high lin- lems. earity, low noise while at the same time minimizing the voltage headroom requirements. A first version of the baseband filter and programmable gain amplifier (PGA) has been realized in a 0.25 mm pro- The complete transmit modulator including a baseband fil- cess and has been fully characterized. The filter is real- ter, an I/Q divider and an I/Q modulator has been imple- ized as a sixth order leapfrog filter with a first order allpass mented and fully characterized in a 0.25 mm CMOS for group delay equalization. It meets all specifications ex- process and shows excellent results. Currently, a cept for its offset behavior. 0.12 mm CMOS version including an RF Pre-amplifier is in fabrication. A new and improved version has been designed in an advanced 0.12 mm CMOS process, including a new offset compensation approach and an automatic corner frequency alignment circuit. This new version will consume significantly less power and is currently being processed.

Chip micrograph ofthe transmit I/Q modulator including Magnitude response and block diagram ofthe complete on-chip inductor. Baseband filter and amplifier

52 IQ Demodulator for Direct- Baseband Circuit for UMTS Conversion UMTS Mobile Transmitter Receiver

Personnel: Ilian Kouchev Personnel: David Tschopp

Funding: BBW, EU-IST-11081 LEMON Funding: BBW, EU-IST-11081 LEMON

Partners: Infineon, Uni Linz Partners: Infineon, Uni Linz

UMTS technologies offer a major step forward in terms of The air interface of the new 3rd generation mobile com- services and capabilities to mobile end users in the early munications standard UMTS (Universal Mobile Telecom- part ofthe 21 century. The direct conversion architecture munications System) is based on a wide band, spread is a very attractive candidate for highly integrated UMTS spectrum modulation scheme, with several users occupy- receivers. It avoids the image suppression problem and ing the same frequency at the same time (W-CDMA). This allows higher integration by reduction ofthe bulky external requires sophisticated control ofeach mobile’s output components at the price oftougher building block specifi- power in order to establish reliable communications. cations. The developed baseband circuit implements accurate The design ofan IQ demodulator fora direct conversion output power control by providing a 40 dB gain control receiver is a challenging task. The mixer should provide range with a step size of1 dB and an accuracy of sufficient amplification at RF to reduce the contribution of < 0.5 dB. noise from the base-band circuitry to a minimum while si- Basically the circuit acts as a reconstruction filter for the multaneously providing high linearity and contributing preceding D/A converter. A low pass filter removes spec- minimum to the overall receiver noise. tral duplicates at multiples ofthe sampling frequency which would otherwise violate the output spurious emis- For the implementation ofthe firstversion ofthe IQ de- sion mask. modulator, an active double balanced Gilbert cell based mixer with a RC output stage was chosen. It was realized The filter has been extended by the possibility of lowering in 0.25 mm CMOS process and was successfully tested. the current consumption ifthe output signal is small. In addition, means for adjusting the output offset have been For the second version ofthe IQ demodulator, a new im- added. The corner frequency is controlled by an integrat- proved architecture ofa double balanced Gilbert cell ed, automatic tuning circuit. based mixer with a folded cascode output stage has been The filter is implemented in Infineon’s C9N 0.25 mm chosen. The new architecture allows operation with lower CMOS process and has been successfully tested. A ver- voltage supply which results in power saving. Further- sion for the C11 0.12 mm CMOS process is currently in more, it gives more design freedom and thus makes the fabrication. design more robust. The IQ demodulator has been fabricated in a 0.12 mm CMOS advanced technology and is currently being processed.

Simplified block diagram for a direct up conversion trans- IQ demodulator for direct-conversion UMTS receiver. mitter (one base band filter channel enlarged).

53 A 33mW, 14-bit, 2.5Msample/s A Low-Power 8-bit Folding and Sigma-Delta A/D Converter Interpolating Analog-to-Digital Converter

Personnel: Pio Balmelli, Robert Reutemann Personnel: Jürgen Hertle

Funding: BBW, ESPRIT-29649 MADBRIC Funding: BBW, ESPRIT-29649 MADBRIC

Partners: EDF, DS2, Cisco Partners: EDF, DS2, Cisco

In both wired and wireless communications applications, In this project an 8 Bit folding and interpolating analog-to- such as DSL, PLC or DECT, low power consumption is digital converter has been developed. Simultaneous opti- highly desirable. Recent publications show that for mization ofall parts ofthe circuit on architectural level re- 1–2 MHz signal bandwidth, sufficient resolution (more sults in a converter with 4 parallel folding stages each than 13b) for typical communications requirements can be realizing a folding factor of 8. Additional 8-times interpola- achieved by over-sampled converters. Typical power con- tion leads to the final resolution of 8 Bit. sumption, however, is above 150 mW for a SD modulator The circuit was fabricated in a 0.25 mm technology and alone and 190mW with the necessary digital filtering. runs at a single 2.5 V supply. It has a remarkable low pow- In this project, a low-power SD A/D converter has been er consumption ofonly 50 mW, including the digital de- implemented in a 0.25 mm digital CMOS process. The IC coding logic and the digital output drivers, at a conversion consists ofa 5 th order SD modulator with a tri-level quan- rate of50 MS/s. The measured nonlinearity parameters tizer and a multi-stage digital decimation filter. With an in- are INL < 1.25 LSB and DNL < 0.95 LSB. The converter put sampling rate of80 MHz and an oversampling ratio of achieves a SNDR of42 dB up to almost Nyquist frequen- 32, a peak SNR of84 dB and a peak SNDR of79 dB have cy. This corresponds to an effective resolution of 6.7 Bit. been measured at the 2.5 MS/s filtered digital output. The The spurious free dynamic range is higher than 49 dB. signal bandwidth of the converter is 1 MHz. The overall chip area is 2.4 mm2. The modulator is implemented using a fully differential switched capacitor circuit style. It occupies a core area of 0.6 mm2 and consumes 24 mW from a 2.5 V supply. The digital filter, consisting of one comb stage and two FIR stages, uses a core area of0.9 mm 2 and has a power consumption of9 mW, using a core supply voltage of 1.25 V. The complete mixed signal IC has a core area of1.5 mm 2 and a total die area of2.5 mm 2. The total 14-bit, 2.5 MS/s A/D converter consumes only 33 mW, which is significantly lower than the power consumption reported for comparable previous SD converters or modulators.

Chip micrograph ofthe 33 mW, 14-bit, 2.5 MS/s SD A/D Measurement results and chip microphotograph ofan converter. 8 Bit folding and interpolation AD-converter.

54 A High-Speed D/A Converter Broadband Sigma-Delta D/A with Background Calibration Converter

Personnel: Clemens Hammerschmied Personnel: Pier Andrea Francese DTU: Jannik Nielsen

Funding: BBW, ESPRIT-29649 MADBRIC Funding: BBW, ESPRIT-29649 MADBRIC

Partners: EDF, DS2, Cisco Partners: EDF, DS2, Cisco

Wireline communications services such as ADSL, VDSL Wire-line communications systems such as xDSL de- or powerline communications systems provide high data mand for high-speed and high-resolution A/D and D/A rates by using already existing cable connections to the converters. Bandwidths in the range from hundreds of customer premises. In contrast to special high-speed wir- kHz to several MHz and resolutions from 10 to 14 bits are ing such as coaxial cable or fiber connections, the physi- common specifications for this type of converters. cal bandwidth that is available for transmitting the data is While SD modulation is the technique ofchoice in the au- limited in this case. Therefore sophisticated modulation dio band, it is still questionable ifthis technique will find schemes are used to be capable ofproviding high data the same success in the xDSL bands, where the IC de- rates. The implementation ofthese modulation schemes signers are pushed to adopt multi-bit converters and lower requires high linearity and high spurious free dynamic oversampling ratios. range ofthe A/D and D/A converters that finallyconvert In this work a broadband SD D/A converter aimed at pow- the signal from the digital to the analog domain and vice er-line modems has been developed. The architecture versa. This is the reason why the new wireline communi- chosen is a 4th order cascaded demodulator followed by cations services are one ofthe driving forcesbehind the a FIR-IIR analog reconstruction filter. current research effort of new data converters. The digital section has been implemented and verified on For D/A converters, resolutions in the order of14 bits at an FPGA. The analog part, designed in a 0.18 mm CMOS conversion rates ofup to 100 Msample/s are required in process, has been submitted to fabrication. The simulated the head-ends ofwire-based communications systems. SFDR is in the range of75-80 dBc fora signal bandwidth This accuracy normally cannot be obtained by pure of 4 MHz and a power supply voltage of 1.8 V. matching ofpassive or active devices, thereforeon-chip calibration has to be used. The D/A converter implemented in this project utilizes a completely floating current source that allows the measurement and calibration ofthe unit current while in full operation and thus provides a true background calibration. The actual calibration ofthe thirty-two current sources forming the five most significant bits is performed by an analog feedback loop. The D/A converter is implemented in an advanced digital 0.25 mm single-poly CMOS process with six layers ofmetal. The achieved resolution with on-chip calibration is 14 bits with a maximum update rate of 50 Msample/s.

Principle circuit diagram ofthe floatingcurrent source that makes a true background calibration possible Layout of the SD D/A analog reconstruction filter.

55 Optimization of OTAs for High-Speed Multibit Sigma- Application in Sampled Data Delta Modulator for Telecom Systems Applications

Personnel: Thomas Burger Personnel: Pio Balmelli

Funding: ETHZ Funding: ETHZ

Operational amplifiers are a critical building block in ana- Oversampled sigma-delta (SD) analog-to-digital convert- log sampled-data circuits, such as SC filters, delta-sigma ers (ADC) are well known for their advantages, which are: modulators and pipelined A/D converters. Higher clock 1) they do not require a precise sample-and-hold stage, 2) frequencies for those circuits translate directly to higher they relax the requirements on the anti-aliasing filter, and speed requirements for the op-amps. A larger unity gain- 3) they achieve very good linearity despite the use ofrel- bandwidth is essential for accurate dynamic charge trans- atively imprecise building blocks. However, the need for fer during the short sampling period in SC circuits. This al- oversampling reduces the achievable conversion band- lows high-Q and precise poles to be realized, whereas the width. accurate phase behavior as required for ideal integrators The aim ofthis project is to build a SD converter fortele- make 80 dB DC-gain, or more, desirable. communications applications with a conversion rate of In this project an optimal design procedure for cascode 20 MS/s and a resolution higher than 13 bits. The de- OTAs has been developed. It is based on an analytical signed SD modulator achieves a simulated signal-to- formulation and achieves maximum gain-bandwidth for a quantization noise ratio of94 dB employing a single-loop given technology and supply current with constraints on architecture of5th order, an oversampling ratio of8, and output swing, phase margin and slew rate. Regulated- an internal 4bit quantizer (DAC). A data weighted averag- cascode gain-enhancement is used to boost the amplifi- ing algorithm is used to linearize the DAC input-output er’s total gain to the product ofthe main and the auxiliary curve. Thanks to the multibit quantizer, the modulator is amplifier’s gain. With this method sufficient DC-gain is en- stable for signals up to 3 dB below the voltage reference. sured, even at minimum gate length of the transistors. In this design the signal-to-quantization noise ratio is well The optimization method is also capable for closed loop below the thermal noise (kT/C), hence the power con- settling optimization. To do so, open loop optimization sumption is minimized. with the closed loop equivalent capacitive load is carried out. It can be shown that a phase margin of76.35 degress in the equivalent open loop model leads to fast settling in the closed loop model. Analysis ofclosed loop poles and zeros reveal the behavior ofthe regulating amplifierand lead to guidelines for optimized design.

Root locus ofclosed-loop poles and zeros as a function ofthe regulating amplifier’scompensation capacitance (first integrator of a delta-sigma converter) Block diagram and output spectrum ofthe SD modulator.

56 An 18mW 1800MHz Quadrature Mobile Telemonitoring System Demodulator in 0.18mm CMOS for Biomedicine

Personnel: Dirk Pfaff Personnel: Michael Oberle

Funding: ETHZ Funding: ETHZ

Low IF- and zero-IF receivers are attractive architectures The practice ofspace medicine is fraughtby several for highly integrated receivers. However, the required unique challenges, including limitations in spacecraft re- quadrature demodulator at RF tends to increase the pow- sources and medical training opportunities. The great dis- er consumption ofsuch receivers substantially. Innovative tance separating the astronauts from the physicians on design techniques must be used to compete with low Earth further confounds managing their health. The Euro- power superheterodyne receivers. pean Space Agency (ESA) uses computer and telecom- A quadrature demodulator consisting ofa 3.6 GHz oscil- munications technology to bridge this distance and lator, quadrature divider and down-conversion mixers has practice telemedicine in space. been implemented. Among other power saving tech- The Integrated Systems Laboratory has developed a nov- niques, the low phase-noise oscillator’s consumption el, highly flexible and mobile system for the physiological could be kept low at only 3mA because a high-Q radial monitoring ofvital biomedical parameters. Small devices, stripline resonator was used instead ofspiral inductors. which sense medical signals, are attached to the human The stripline is integrated into inner layers ofthe printed body and use the body itselfto communicate with each circuit board to keep the board size small. other wirelessly. The system operates stand alone but Good measured performance on all building blocks (e.g can be integrated into existing IT infrastructures such as 40 dB image rejection, 8.5 dBm mixer IP3, -3 dBm mixer in the International Space Station. compression point) was observed despite the extremely low overall consumption of10 mA. The circuits are imple- To prove the concept, a feasibility study had been per- mented in standard 0.18 mm CMOS. formed prior to the development of a final demonstrator, which transmits recorded and digitized electrocardio- graphy signals along the human body.

Units on-board the International Space Station, which will be affected by the technology are Cardiolab, Physiology Rack, and the Lower Body Negative Pressure Device.

Board photograph and cross section through the multi- layer board. The striplines are outlined by dashed lines Photograph of the digital ECG demonstrator.

57 Research Projects

Technology CAD

Coordinators:

Wolfgang Fichtner Andreas Schenk Doelf Aemmer

59 Modeling and Simulation of Quantum Drift Diffusion (QDD) Quantum Effects in MOSFETs Modeling of Tunneling through Insulators

Personnel: Andreas Schenk Personnel: Timm Höhr, Andreas Schenk ISE AG: Andreas Wettstein ISE AG: Andreas Wettstein

Funding: ETHZ Funding: ETHZ, KTI-4082.2 HYBRID

Partners: ISE AG Partners: ISE AG

It is often argued that source-to-drain tunneling repre- In the deep-submicron regime quantum mechanical (QM) sents a fundamental limitation to CMOS scaling. One-di- effects substantially influence the behavior of semicon- mensional calculations of this effect were performed ductor devices. In MOSFETs a pronounced effect is the frequently, with the evident result of an exponential de- QM-tunneling current through thin gate dielectrics which pendence of the off-state current on barrier width and increases the off-state power consumption. Therefore, height. The question to which extent the strong quantum TCAD solutions capable of modeling these effects are of confinement perpendicular to the Si-SiO2 interface will growing interest. modify such a picture was the subject of this study. By The most accurate quantization model available in the de- means of self-consistent 2D device simulation with the vice simulator DESSIS-ISE is the 1D-Schrödinger solver density gradient model it was found that source-to-drain that can be combined with the Bardeen method to de- tunneling of 2D channel electrons differs qualitatively from scribe direct tunneling. The QDD model is computational- the naive 1D picture. To demonstrate the change of the ly more efficient as it is based on a drift-diffusion sub-threshold behavior, the effective channel length of a description modified by an additional quantum correction test MOSFET was varied between 30 nm and zero. that reduces and smoothes abrupt potential barriers. The tunneling current is then described as a drift-diffusion pro- Reducing the effective channel length results in the clas- cess over these residual barriers. It was found that QDD sical degradation of the sub-threshold swing due to the gate current characteristics of nMOSFETs can be fitted to rapidly decreasing barrier height (increased thermal leak- Schrödinger/Bardeen (SB) results for positive gate voltage), but not in a noticeable quantum-mechanical degra- age, but exhibit a region of negative differential resistance dation of the slope. This is explained by the dominant (NDR) at negative gate voltage. Resonant tunneling de- influence of the Si-SiO2 potential perpendicular to the vices (RTDs) are known to show NDR in reality. Here, weak source-to-drain potential barrier. As the former is QDD and SB simulation results display current peaks at smoothed out by the quantum potential, the source-to- clearly different positions. The effect vanishes -also in drain barrier increases in the vicinity of the interface. This single-barrier MOS-structures - if all semiconductor parts causes the well-known quantum-mechanical VT shift. are equally n-doped. One can, therefore, conclude that Even in the off-state and for vanishing Leff the height of the the apparent NDR found with QDD is not due to a reso- source-to-drain barrier is only slightly smaller compared to nance effect but rather an artifact related to large density the classical counterpart. One can conclude from this in- differences across the barrier. vestigation that the off-state leakage at 300 K will be dom- inated by thermionic emission even in the limit of zero gate length.

Comparison of QDD and SB results: Upper: NMOSFET Gate tunneling currents for two oxide 2D potential barrier at threshold for Leff = 4 nm. Left: clas- thicknesses. Lower: Si-RTD with a 1 nm well between sical conduction band edge, right: smoothed potential. two SiO2 barriers and different doping.

60 Simpliﬁed Model for Inelastic Hot-Carrier Degradation of Acoustic Phonon Scattering MOSFETs

Personnel: F. M. Bufler Personnel: Andreas Schenk, Alain von Allmen, Fabian Bufler ISE AG: Christoph Zechner, Axel Erlebach Funding: KTI-4082.2 HYBRID Funding: ETHZ, Toshiba

Partners: ISE AG Partners: Toshiba, ISE AG

For Monte Carlo (MC) simulation, the elastic equipartition Subject of this project were electrically stressed nMOS- approximation for acoustic phonon scattering of holes is FETs with gate lengths between 90 nm and 150 nm. very useful. On the one hand, the scattering rate depends Based on careful process simulation, the impact of hot- only on energy and thus facilitates the search for after- carrier generated interface-trap profiles on the device per- scattering-states. On the other hand, the experimental ve- formance was studied by combined simulations using full- locity-field characteristics are accurately reproduced. band Monte Carlo (SPARTA), drift-diffusion (DESSIS), However, the results with a momentum-dependent scat- and a post-processing computation of the trap generation tering rate for inelastic acoustic phonons have shown that rate. The latter uses di Maria’s universal trap generation the elastic approximation significantly underestimates the probability PG(E), the electron distribution functions at the number of hot holes. Si-SiO2 interface, and simulated gate tunnel currents to Therefore, a model has been developed which includes obtain the flux of energetic electrons at the poly-oxide in- the energy dissipation of acoustic phonons, but involves terface. The generated interface-trap profiles, which are at the same time a scattering rate which depends only on charged during the bias sweep, change the transfer char- energy. The main ingredient consists of averaging the acteristics in a typical way (VT shift and degradation of on- momentum-dependent acoustic phonon energy with the current), in accordance with experimental data. From help of the Boltzmann distribution yielding a (lattice-tem- these modifications one can, to some extent, gain infor- perature dependent) constant. The figures show a good mation about spatial shape and energetic distribution of agreement of the model with the experiments which also the interface traps. leads to the enhanced hot-hole tail of the distribution.

Simulated change of the transfer characteristics of an nMOSFET with 120 nm gate length caused by a homo- Top: Velocity-field characteristics of holes in silicon. geneous interface-trap density (upper) and by a sharply Bottom: Energy distributions of holes in Si at 250 kV/cm. peaked trap distribution at the drain junction (lower).

61 Conductance of Nano-Scale 3D Simulation of Noise in Silicon-On-Insulator (SOI) Bipolar Transistors Single Electron Devices

Personnel: Frederik Ole Heinz Personnel: Andreas Schenk, Bernhard Schmithüsen ISE AG: Paul Pfäffli, Axel Erlebach

Funding: BBW, EU-IST-10828 NANOTCAD Personnel: ETHZ, Toshiba, ISE AG

Partners: Uni Pisa, Uni Cork, MPG Stuttgart, Partners: Toshiba, ISE AG TU Wien, Uni Würzburg

Single electron devices are promising candidates for ultra 3D RF and 1/f noise simulations on the device level were large scale integration, e.g. for memory applications. performed on well-calibrated vertical NPN transistors of Their operation is based on the discreteness of the ele- Toshiba’s 0.35 mm BiCMOS process. Due to the 2 Gbyte mentary charge and on quantum mechanical tunneling: in RAM restriction, mesh refinement was limited to about a single electron transistor there is no classically conduct- 26,000 vertices. The resulting accuracy of the ac and ing path from source to drain (see fig. a). But tunneling noise analysis was found to be still insufficient for a dis- may allow an electron to traverse the depleted regions crimination between 3D and numerical effects (too coarse (‘tunnel junctions’) on either side of the central island grid, errors in the solution of the linear system). (‘quantum dot’), provided that its energy matches that of Measured Y-parameters as function of frequency and an unoccupied state inside the quantum dot. Should no base voltage were used for a sensitivity analysis with re- such state exist at energies available to electrons from the spect to various model parameters, geometry variations, source, conductance is suppressed — a situation known and doping profiles. Major influence was found to origi- as Coulomb blockade. nate from the built-in potential of the emitter-base junc- The simulation approach to this type of devices comprises tion, the mobility model in the base, the real geometry of self–consistent solving of the Kohn–Sham equations at the STI (shallow trench isolation), and the actual 3D ge- constant temperature for various values of a parametric ometry of the extrinsic collector. Noise simulation in 3D is quantum-dot chemical potential. The resulting data are further complicated by the fact that quantities like noise used to construct the canonical state at each integral elec- figures cannot be scaled, i.e. the full 3D geometry has to tron number N inside the sampling interval by Monte–Car- be used instead of reduced geometries allowed by the lo integration over the N–particle subspace of the phase symmetry of the 3D structure. space of the quantum dot. Finally, Grand canonical statistics is invoked to compute the relative probabilities of the various N. Together with Bardeen’s transfer Hamiltonian formalism for the computation of tunneling rates between the quantum dot and the source/drain leads this yields all the information necessary to compute the linear response conductance of the device from Beenakkers conductance formula. a)

SOI single electron transistor (dot diameter: 20 nm) Spatial distribution of the electron RF noise density (up- a: geometry and iso–surface of the electron density per). Maximum 3D refinement in the critical device re- b: Coulomb staircase and conductance oscillations gions (lower).

62 Monte Carlo Generated Noise Coulomb Enhancement of Sources Radiative Recombination Rates

Personnel: Simon Brugger, Andreas Schenk, Fabian Personnel: Frank Geelhaar Bufler

Funding: ETHZ, TOSHIBA Funding: SNF 21-58811.99

Partners: TOSHIBA

Noise sources used nowadays in device simulators, like In consequence of the Coulomb interaction between the DESSIS, are obtained under the incorrect assumption of charge carriers in a semiconductor device, the probability the validity of the Einstein relation far from thermodynam- of finding two unlike particles in the immediate vicinity of ical equilibrium. We know experimentally that this approx- each other is higher than in the ideal, uncorrelated case. imation is justified only for small electrical field strengths Concerning the modeling of the radiative recombination (up to 1 kV/cm). However, the constant effort to reduce rate, this fact should be taken into account by an en- the size of the transistors leads to devices inside which hancement factor multiplying the usual expression. Quan- the magnitude of the electrical field is far above this level. titatively, this factor is given by the electron-hole pair The goal of this project is to build a table of more accurate correlation function evaluated at zero interparticle dis- noise sources, which may then be used in a device simu- tance. Assuming a Debye interaction potential the latter lator. Working under the less restrictive assumption that has been calculated numerically and compared to electrons in a device behave locally like in bulk silicon, al- Hangleiter’s results. Due to the screening effect, the re- lows one to generate those sources with bulk Monte Carlo sults show a pronounced density and temperature depen- (MC) simulations. dence. Below the excitonic Mott transition the bound state The noise sources were calculated for different electric contribution clearly dominates the total enhancement, es- field strengths and combinations of particle and doping pecially at lower temperatures. This behavior is in qualita- densities. The results show, in agreement with experi- tive agreement with experimental findings. ment, that the longitudinal component of the diffusion tensor is always smaller than the transverse ones. From those simulations emerges that the Einstein relation ap- proximates the noise sources for high field strengths only poorly and that the noise sources were underestimated.

Top: Longitudinal and transverse component of the diffusion tensor, computed with MC, compared with experi- Coulomb enhancement in a symmetrical electron-hole mental data. Good agreement is achieved. plasma in silicon at T = 100 K (top) and T = 300 K (bot- Bottom: Comparison between the noise sources accord- tom). The decomposition into scattering and bound state ing to the Einstein relation and the MC generated ones. contribution is shown.

63 Robust Grid Adaptation Process Simulation with in Device Simulation “noffset3d” Meshes for Large Avalanche Generation

Personnel: Bernhard Schmithüsen Personnel: Jens Krause

Funding: ETHZ, ISE AG Funding: ETHZ, BBW, EU-IST-11433 MAGIC_FEAT

Partners: WIAS, ISE AG Partners: ISE AG, FhG-IIS-B, INRIA, ST Gentilly, TU Wien

A crucial step of a grid adaptation procedure for nonlinear The process simulator DIOS-ISE has the capability to call stationary boundary value problems, essentially deter- external tools as the meshing engine. An interface to the mining the robustness of the module, consists of the re- generator “noffset3d” has been developed and tested in computation of the solution on adaptively generated order to replace the octree-based meshes by more gener- meshes. Starting from the initial guess, obtained by sim- al approaches. ple interpolation of the old solution, the coupled Newton iteration often fails to converge due to the singularly The pictures show a simple test case that has an oxide perturbed character of the solutions of the drift-diffusion layer with an implantation window on the silicon substrate. system and the (partially) layer-ignoring simulation mesh- Both implantation and diffusion were simulated. es. The mesh generator “noffset3d” has two refinement The developed smoothing process for the first initial modes: creation of anisotropic elements at interfaces and guess consists of a correction of the electrostatic potential isotropic refinement in the volume. In this case the aniso- solving a mixed linear and nonlinear Poisson equation fol- tropic layers are created at the silicon/silicon oxide inter- lowed by a nonlinear node-block Jacobi iteration. These face, and the pn-junction is isotropically refined. smoothing iterations lead for most device operating con- The top view show the state after (boron-)implantation ditions to convergence in a subsequent fully coupled and the bottom after a diffusion step. At this time step a Newton iteration, but they often fail for large avalanche re-meshing is necessary since the pn-junction moved into generation. In such situations a homotopy technique is a poorly refined region. used, which freezes the old avalanche generation and in- corporates stepwise its actual value and derivatives. The described recomputation procedure turns out to be quite robust and is even able to handle situations where terminal currents change by several orders of magnitude caused simply by the change of the grid.

Drain current characteristics gained by adaptive simulation (AGM) and on a fixed grid (REF) for a double-gated MOSFET structure: filled symbols indicate currents computed at the same bias on intermediate adaptively gener- Simulation of implantation and diffusion with DIOS-ISE and ated meshes. noffset3d.

64 “Moving Boundary” Algorithm Simulation of Substrate with Volume Triangulations Leakage in Semiconductor Lasers

Personnel: Jens Krause Personnel: Andreas Witzig, Matthias Streiff

Funding: ETHZ, BBW, EU-IST-11433 MAGIC_FEAT Funding: TOP NANO 21 5103.1 VCSEL, ISE AG

Partners: ISE AG, FhG-IIS-B, INRIA, ST Gentilly Partners: Avalon, ISE AG TU Wien

During process simulation steps with time-dependent ge- There are three possibilities for optical losses in an edge- ometries, like oxidation, a full simulation mesh is needed emitting laser diode: mirror loss, absorption loss and scat- for the new geometry at each time step. tering loss. The light that is coupled out through the semi- transparent mirrors is the laser output, while the absorp- Three distinct procedures are needed to accomplish the tion and the scattering losses are undesired contributions task: and must be kept at a minimum in the device design.

• the construction of a geometry description for the new For a wide range of semiconductor lasers, an optical time step, waveguide is grown on top of a substrate with a high refractive index. As a result, the optical wave leaks into the • the generation of a new surface mesh, and substrate. In this project, the waveguide eigenvalue solver has been extended to cover leakage into substrate. • the generation of volume mesh.

In order to solve the first task the prototype of an algorithm was developed that works not with a surface triangulation, like string algorithms do, but with a volume triangulation. The movement of points causes some tetrahedra to be in- verted. These inversions are either artificial and can be solved by local transformations or they correspond to collisions of interfaces. The volume triangulation serves not only as a definition of the current state but also as a search data structure to determine collisions.

With the help of the volume triangulation, collisions can be detected reliably before loops occur; this is a prerequisite for robustness of this algorithm. Note, that these algorithms -in contrast to earlier attempts -do not use the simulation mesh, but can run on any volume triangulation with as few points as possible.

Leakage into substrate for two designs of a laser diode. The device substrate has a high refractive index. In the example, the thickness of the separation layer has been Analytical test example for the “moving boundary”: a thin varied, and the resulting difference in the loss constant is layer is deformed so that it partly disappears shown.

65 Calculation of the Spontaneous Simulation of a Tunable Twin- Emission Coupling for Edge- Guide Distributed-Feedback Emitting Lasers Semiconductor Laser

Personnel: Andreas Witzig, Michael Pfeiffer, Personnel: Lutz Schneider, Andreas Witzig, Michael Matthias Streiff Pfeiffer, Matthias Streiff; Nortel Networks: Berthold Schmidt; Adrian Bregy (Student) Funding: KTI-4146.2 Laser, Funding: KTI-4146.2 Laser ISE AG ISE AG

Partners: Nortel Networks, ISE AG Partners: Nortel Networks, ISE AG

In a semiconductor laser, spontaneous emission and Tunable semiconductor lasers with single-mode emission stimulated emission are the two key processes of photon play an important role in optical communications, mea- generation. Stimulated emission can be investigated by surement and sensing. The tunable twin-guide (TTG) dis- an eigenmode expansion of the optical fields. Spontane- tributed feedback laser represents a transversely ous emission, by contrast, must be seen as the response integrated structure allowing for a continuous tuning to uncorrelated sources within the laser cavity. In conse- range of the order of 10 nm. The tuning mechanism is quence, the spontaneous emission must be investigated based on the change in refractive index due to carrier in- by a full 3D simulation of the wave propagation. For this jection into a tuning region which leads to a decrease in aim, the finite-difference time-domain method (FDTD) is laser wavelength. The tuning region is optically coupled to employed. the active region as described by the high confinement In a typical edge-emitting laser structure, only a small por- factors in both regions. tion of the spontaneous emission is coupled into the las- The goal of this project has been to investigate how the ing mode. The main goal of this project is the calculation TTG laser structure can be optimized with respect to max- of the spontaneous emission coupling factor, i.e. the por- imal tuning range and output power. The tuning range can tion of the electromagnetic radiation that is coupled into a be extended by increasing the tuning layer thickness. This waveguide mode. The result is dependent on the position implies a reduction of the optical confinement factor of the and the frequency of the excitation. active region, however, and ultimately limits the output power. Simulation of laser diodes with different thickness of tuning and spacer layers demonstrate this behavior. Since the optical mode pattern varies due to the refractive index change a self-consistent solution of the optical equation is mandatory.

Wave propagation in an edge emitter laser device. Top: Transverse optical near field distribution and wavelength snapshot of the optical field when the waveguide is excit- tuning behavior of a TTG distributed feedback laser di- ed by an optical pulse. Bottom: radiation through a verti- ode. Note the displacement of the field distribution from cal plane at some distance from the excitation. the tuning towards the active layer during tuning.

66 Simulation of a Weakly Index- Self-Heating Effects in Multi- Guided Buried-Stripe Type Dimensional Simulations of Laser Diode Quantum-Well Lasers

Personnel: Lutz Schneider, Matthias Streiff, Michael Personnel: Michael Pfeiffer, Andreas Witzig Pfeiffer, Andreas Witzig

Funding: KTI-4146.2 Laser Funding: KTI-4146.2 Laser, ISE AG ISE AG

Partners: Nortel Networks, ISE AG Partners: Nortel Networks, ISE AG

Single transverse-mode 980 nm laser diodes are essen- Device self-heating is one of the most severe problems in tial components for next-generation optical amplifier sys- many active optoelectronic devices, limiting their perfor- tems, which are expected to fulfill the increasing mance and shortening their life times. In particular, semi- requirements of rapid and large capacity communica- conductor lasers are subject to thermal problems, tions. They are the most promising devices to provide ex- showing thermal rollover of their output characteristics citation light sources for erbium-doped fiber amplifiers. and catastrophic optical damage. Inclusion of thermal For such laser diodes it is essential to possess a stable simulations in an early stage of device development can transverse mode at high power operation in order to guar- help to improve the device design with respect to thermal antee efficient coupling to the single mode fiber. properties. The existing laser module of the device simulator DESSIS This project addresses the simulation of a weakly index has been extended to allow for the self-consistent electro- guided buried-stripe laser, a design which is expected to thermo-optical simulation of quantum-well lasers in one, meet this requirement.In this structure a confinement lay- two and three dimensions. For the simulation of tempera- er is used for the guidance of the transverse optical mode ture effects, a heat diffusion equation or three energy bal- as well as for the current confinement. ance equations (assuming the lattice temperature and the carrier temperatures not to be in equilibrium) can be solved in addition to Poisson’s equation, the continuity equations and the photon rate equation in a fully self-consistent scheme. As application, a high power pump laser of Nortel Net- works was simulated, investigating the effects of unequal facet reflectivities of the two laser facetes.

80% 20%

Top: Optical near field distribution. A high refractive index step and a narrow waveguide bottom width are responsi- Optical intensity (middle) and temperature distribution ble for maintaining single-mode operation even at high (bottom) in a ridge-guided edge-emitting laser with facet output powers. Bottom: The current streamlines show reflectivities of 80% and 20% respectively. The simula- how the confinement layer also acts as a current blocking tions were carried out for a longitudinal (left) and a trans- region. verse cross section (right) of the device.

67 Temperature and Carrier LUMI2 Optical Mode Solver Density Effects on Optical Modes in Quantum-Well Lasers

Personnel: Michael Pfeiffer, Lutz Schneider, Personnel: Matthias Streiff, Andreas Witzig Matthias Streiff

Funding: KTI-4146.2 Laser, Funding: TOP NANO 21 5103.1 VCSEL, ISE AG ISE AG

Partners: Nortel Networks, ISE AG Partners: IWR-ETHZ, ISE AG

High capacity, long distance optical fiber systems are the This project addresses the comprehensive computation backbones of today’s world wide communication net- of optical modes in the context of physics-based semicon- works. Essential parts of these systems are amplification ductor laser device simulation. In this approach, a generic modules, many of them containing high power pump laser frequency domain finite element (FE) formulation of the diodes used for optical pumping of erbium-doped fiber dielectric optical resonator problem is used. The FE ex- amplifiers. In order to achieve good coupling of the diode pansion of a realistic vertical-cavity surface-emitting laser output to the fiber system, the multimode behavior of the (VCSEL) device yields very large (order ~500,000) sparse laser diodes has to be analyzed and optimized over a generalized complex non-Hermitian eigenproblems. In wide range of operation. the course of solving the device equations self-consistently over the entire operation range of the laser device a se- In this project, the laser module of the device simulator quence of many such large eigenproblems has to be DESSIS has been extended to self-consistently simulate solved. the effects of temperature and carrier density on the multiple transverse optical modes of edge-emitting lasers. LUMI2 is a software implementation of this approach, that These effects are due to the change in the refractive index is being developed in the framework of this TOP NANO 21 of the semiconductor materials. As for high power opera- research project addressing physics-based VCSEL de- tion the mode patterns can change considerably, self-con- vice simulation. LUMI2 is implemented in the form of a sistent solutions of optical, electronic and temperature C++ library that can either be used stand-alone using a equations have to be calculated for given bias voltages. Tcl script interface or in conjunction with the laser device simulator DESSIS.

Top: Nearfield intensities of the first order transverse mode of an edge-emitting laser calculated at an injection current of 550 mA. For the top left picture, the refractive index was assumed constant. For the top right picture, carrier and temperature effects were included in the simulation. Due to a change in refractive index, the mode is shifted towards the device center, thus gaining a larger fraction of the injection current, consequently lasing at higher intensity. Bottom: Overall optical nearfield intensity (sum of fundamental and first order mode) on a cut along the active region of the device shown above (dashed line). Clearly visible is the shift of the intensity Etched mesa VCSEL with oxide confinement, 25 DBR maximum out of the center of the device due to higher pairs at top and 40 DBR pairs at bottom. Normalized in- first order mode intensity. tensity of electric field on logarithmic color scale.

68 Numerical Simulation of InP/ Intraband Photon Absorption in InGaAs High-Speed Multi-Quantum-Well (MQW) Photodetectors Structures

Personnel: Serguei Chevtchenko, Andreas Witzig, Personnel: Serguei Chevtchenko, Andreas Witzig, Opto Speed: Markus Blaser, Nejla Bektas Michael Pfeiffer

Personnel: TOP NANO 21 5782.2 Photodetector, Funding: Fujitsu ISE AG

Partners: Opto Speed, ISE AG Partners: Fujitsu, ISE AG

The pin-diode photodetectors are designed for optoelec- Intersubband (i.e. intraband) absorption in semiconductor tronic receivers used in high speed optical communica- quantum wells is of major interest for far-infrared photode- tions systems. The pin-photodetector consists of three tectors. The intraband absorption based on transitions layers of semiconductors with different doping profiles. In- within the same band, instead of the usual interband ab- cident photons of sufficient energy generate the electron- sorption mechanism (involving transitions between the hole pairs in the intrinsic region. The diode is operated un- conduction and valence bands). N-doped quantum wells der reverse bias. Charge carriers are accelerated by the are used, in order to create these states within the con- applied voltage and produce the photo current. duction band. The first aim of this project is the simulation of the related important parameters of pin-diode. These parameters In this project, the AlGaAs-GaAs-AlGaAs multi-quantum are: CV characteristics; temperature and voltage depen- well structure is studied. Using different approximation dencies of dark current, bandwidth, impulse response. techniques and zero-field limit, intersubband absorption The second task is the optimization of the existing simula- spectra of particular structure have been estimated. We tion tools for high-speed photodetector applications. treat absorption in a single quantum well, and assume The main benefit of computer simulation is the possibility that the absorption in n multiple, uncoupled quantum of design parameter variation and design optimization wells, can simply be obtained by multiplication with n. The without the need to perform long-winded and costly exper- QW under consideration can be a system with initial state iments. In the simulation, the top-versus bottom illumina- and final bound state (bound-to-bound transitions) or con- tion, high-field and non-equilibrium carrier transport tinuum states (bound-to-continuum transitions). models should be considered.

Absorption spectra, calculated for the bound-to-bound transitions using the finite potential box. The broadening of the absorption spectra due to the optical scattering re- laxation included by replacing the Dirac function in the absorption coefficient formula by a Lorentzian function with a line width 0.03 eV. The optical dipole moment, de- The InGaAs/InP high speed photodiode chip, produced termining the value of the absorption coefficient, has a z- by Opto Speed. component only.

69 Optoelectronics Molecular Dynamics-Kinetic Characterization Laboratory Monte Carlo Calculations of Ion (OptoLab) Implantation

Personnel: Matthias Streiff, Fridolin Illien, Personnel: Eduardo Alonso, Christoph Müller Norbert Felber IFH-ETHZ/IfE-ETHZ: Daniel Erni Funding: ETHZ Funding: TOP NANO 21 5779.2 MOLDYN, ISE AG

Partners: IFH-ETHZ, IfE-ETHZ Partners: ISE AG

In traditional electronics, standard characterization meth- Low energy boron implantation and post-implantation an- ods have been developed over the past decades. Today, nealing are simulated by a combination of molecular dy- any work performed in the field of electronics demands namics (MD) and kinetic Monte Carlo (KMC). A collision both expertise in, and access to, device characterization. cascade database generated with a modified Tersoff po- This standardization process has started in optoelectron- tential at the Complutense University of Madrid is used as ics (OE) and will continue to develop in the future. input to the KMC diffusion simulation. As opposed to the binary collision approximation (BCA), MD offers a full de- In this project the conceptual work for OptoLab -a joint scription of the damage state. Unknowns for BCA, such (IIS-ETHZ, IFH-ETHZ, IfE-ETHZ) facility to systematically as the ratio of interstitial to substitutional boron or the clus- characterize OE devices -was carried out. The aim of Op- ter size distribution can be easily determined. Interesting toLab is to provide users with ready-to-use OE character- conclusions may be drawn by comparing experimental ization set-ups, some of which are common standard data of as-implanted and annealed profiles with BCA- measurements of today, others are potential “standard KMC and MD-KMC simulations. measurements of tomorrow”. To this end, OptoLab is one of the core building blocks of OE research at the Depart- BCA performs extremely well at energies as low as 500 ment of Information Technology and Electrical Engineer- eV. This is not entirely surprising, given that BCA codes ing (D-ITET). Moreover, OptoLab will enable D-ITET to are fitted to extensive profile databases. More remarkable provide students with practical education in the field of is the agreement between MD implantation and the exper- OE. imental profiles, since the MD potential was developed without previous knowledge of the experimental data. On . the downside, MD predicts excessive boron activation during annealing. The simulated annealing profiles show no significant differences, both for MD and BCA implantation. The starting conditions for low energy implants are therefore correctly handled by MD and BCA. Any dis- agreement between annealing experiments and diffusion simulations which might arise must be hence ascribed to diffusion models.

Selection of planned OptoLab characterization set-ups: IVPDC terminal current / voltage / light power DC characteristics, IPSMR terminal current / light power small signal modulation response, OSPEC optical emission Simulated profiles by MD and BCA and measured pro- spectrum, RIN relative intensity noise files of boron implanted at 500 eV.

70 Ab-Initio Study of Arsenic Diffusion Mechanisms of Highly Activation and Deactivation in Arsenic-Doped Silicon Silicon

Personnel: Christoph Müller Personnel: Christoph Müller

Funding: BBW, EU-IST-11433 MAGIC_FEAT Funding: BBW, EU-IST-11433 MAGIC_FEAT

Partners: ISE AG Partners: ISE AG, TU Wien

As silicon device dimensions shrink and electron device The microscopic mechanisms of dopant impurity diffusion junctions become shallower, it is becoming more impor- in Si are of intrinsic scientific interest and also constitute tant to increase the conductivity of these regions. For n- the cornerstones of modeling programs for the design and type doping, arsenic is incorporated into these layers in fabrication of devices. Prerequisite for predictive simula- excess of its solubility limit. The subsequent deactivation tion of dopant profiles is a thorough understanding of the of arsenic during thermal annealing is the subject of ongo- diffusion mechanisms at the atomic scale. The complicat- ing research. In order to study the underlying reactions on ed diffusion behavior of the n-type dopant arsenic in high- atomic scales, first principles calculations offer invaluable ly doped crystalline silicon is subject to investigation. By theoretical support to experimental work. means of potential energy diagrams, different diffusion This project aims at examining various vacancy-impurity mechanisms are examined, which provide temperature clusters that play a predominant role in arsenic deactiva- and doping concentration dependencies of the diffusion tion. Formation energies, band structures and charge process. density distributions are calculated using density function- The main focus of this project is the study of correlated, al theory (DFT) in both the local density approximation vacancy-mediated diffusion mechanisms of the dopant at- (LDA) and the generalized gradient approximation (GGA). oms. Various types of migration paths for ring mecha- In addition, energy barriers of deactivation processes are nisms and percolation models are investigated. evaluated by means of the nudged elastic band method. Determination of energy barriers as well as total energy Such data is of great importance for an examination of re- calculations are performed with VASP, an ab-initio code action kinetics and thus temperature dependence of both from TU Wien using both ultra soft (US) and projector dopant activation and deactivation in bulk silicon. augmented-wave (PAW) pseudo potentials.

Frenkel pair generation in highly As doped silicon: Deac- tivation of four As dopants in a cluster (red spheres) upon migration of the center silicon atom. Top: Calculated en- Vacancy-mediated arsenic diffusion: Potential energy di- ergy barrier for the reaction. Bottom: Migration path of agram of a six-fold vacancy migration path around the As the center silicon atom (depicted at consecutive posi- (red sphere in the lower picture). The corresponding lat- tions) and electron density calculated with DFT. tice sites are indicated with white spheres.

71 Ab Initio Calculations for the Parallel Iterative Methods for Self-Interstitial in Silicon Large Sparse Linear Systems from Semiconductor Simulation

Personnel: Beat Sahli Personnel: Stefan Röllin, Andreas Pomp

Funding: TOP NANO 21 5779.2 MOLDYN, Funding: KTI-4922.1 Numerik II, ISE AG ISE AG

Partners: ISE AG Partners: ISE AG

The self-interstitial in silicon plays an important role in the In semiconductor simulation, a large part of the simulation coupled diffusion of dopants and native point defects. The time is used to solve large sparse linear systems. Both di- diffusivity and the equilibrium concentration are two im- rect and iterative methods are currently used to solve portant properties of the self-interstitial which determine these systems in the device simulator DESSIS and the its contribution to dopant diffusion. These properties are process simulator DIOS. difficult to measure and ab initio simulations allow to cal- The advantages of iterative solvers are the lower memory culate them from first principles. requirements and the better performance compared to di- The goal of this project is to calculate the equilibrium con- rect solvers, especially for large systems. Unfortunately, centration and the diffusivity of the self-interstitial in sili- the iterative methods sometimes perform poorly. A robust con. Density functional theory calculations have been iterative method is therefore essential. performed with the VASP code developed at the Vienna In this project, a new linear solver has been implemented, University of Technology. It uses a plane-wave basis set which uses nonsymmetric permutations and scalings as a and supports the local density approximation and the gen- preprocessing step for the iterative methods to improve eralized gradient approximation with ultra-soft pseudopo- the robustness. The idea is to convert the matrices, such tentials and also with the projector augmented-wave that the diagonal elements of the matrices are larger than method. the off-diagonal elements. As a result, the iterative meth- To calculate the equilibrium concentration and the diffu- ods are more stable and the convergence rates are better. sivity, it is necessary to find the ground state configuration The mentioned technique was integrated and tested in and the saddle-point of the transition path and the corre- DESSIS. A comparison of the new technique with the iter- sponding energies. Searching for the minimum energy ative methods used up to now, shows a significant reduc- configuration is done by starting energy minimizations tion of the solution time. from different configurations. Searching for the transition path is done with the nudged elastic band method.

Comparison of the solution time for four typical matrices extracted from 3D DESSIS simulations. The iterative pre- From left to right and from top to bottom: idealized self- conditioned BiCGStab method with an incomplete LU- interstitial configurations: tetrahedral, hexagonal, factorization was used to solve the matrices in the shown split<110> and extended. examples.

72 Research Projects

Physical Characterization

Coordinators:

Wolfgang Fichtner Mauro Ciappa

73 Reliability of Power Semicon- Thermal and Computational ductors for Automotive Fluid Dynamics Simulation of Applications Integrated Modules

Personnel: Mauro Ciappa, Flavio Carbognani Personnel: Kari Oila, Mauro Ciappa

Funding: BBW, EU-GROWTH-00275 HIMRATE Funding: BBW, EU-GROWTH-00275 HIMRATE

Partners: HIMRATE Consortium Partners: HIMRATE Consortium

A hybrid vehicle (HV) is based on a downsized internal The constant increase in power semiconductor module combustion engine (ICE) supported by an electric motor- heat dissipation has lead to the need to reliably estimate generator.The starter generator approach is a solution the junction temperatures and temperature profiles inside used in modern HVs to realize very compact construc- the unit. The emerging of a new generation of robust and tions, which enable to stop the ICE whenever the vehicle user-friendly Computational Fluid Dynamics (CFD) soft- is stationary and to provide additional boost, if full power ware solutions with the increase of computing power has is required. The existing converters for hybrid traction are made the thermal/fluid-flow simulation of a complete pow- still characterized by the use of standard packaged devic- er module and the attached cooling system feasible. The es cooled by dedicated water cooling circuits. A viable so- reasonable level of detail goes already down to the level lution for improving the efficiency and decreasing both of modeling solder layers, chips and bond wires, still weight and cost of the converters is system integration, in keeping solution times of a short-time transient problem in particular the design and the realization of highly-integrat- a range of hours instead of days or weeks. ed modules to share the cooling circuitry with the ICE. Since this strategy turns into higher junction temperatures The real power of the simulations lies in the extraction of of the devices and into more stringent thermo mechanical key parameters for faster temperature calculations using stresses, it has a great impact on the reliability of the con- very complicated heat dissipation profiles (mission pro- verter. In this framework, new methodologies have been files) over extended time-periods for studying the module developed for predicting the lifetime of IGBTdevices of temperatures during real-life operating conditions, such hybrid vehicles operated especially in an urban environ- as heavy use of a electric/hybrid car during a mixed drive. ment. These parameters can be extracted from the thermal step-response curves from the CFD-simulations, reducing the overall solution time dramatically. Once the parameters are extracted, different mission profiles can be investigated within minutes.

Measured junction temperature of an IGBTin a HV operated in urban environment (top). Stress-strain character- Layers in structure, definition of corresponding time-de- istic of a critical solder layer within an IGBTof a HV pendent parameters and a cross-section of a FEM simu- operated according to the mission profile above (bottom). lation model of a real structure.

74 Electrical Characterization of Extraction of Doping Proﬁles by Silicon at Very High Scanning-Capacitance Temperatures Microscopy

Personnel: M. Ciappa, F. Illien Personnel: Maria Stangoni, Lorenzo Ciampolini Toshiba: Hidehiko Yabuhara

Funding: BBW, EU-GROWTH-00275 HIMRATE Funding: BBW, EU-RTN-00031 HERCULAS, Toshiba

Partners: HIMRATE Consortium Partners: HERCULAS Consortium, Toshiba

The design of rugged IGBT and MOSFET devices operat- This project is focused on the results of Scanning Capac- ed at junction temperatures up to 200 C requires accurate itance Microscopy (SCM) Measurements referred to the device simulations. In the device simulatior DESSIS mod- use of diamond-coated cantilevers and on the performed els based on first-principle physics for the carrier mobility sample preparation. Diamond-coated cantilevers have and for the impact ionization are implemented and cali- been used for scanning capacitance microscopy as an al- brated up to 400 C. ternative for metal-coated ones in order to avoid the wear These measurements therefor have been carried out to out of the tip during the measure. confirm the validity of the implemented models in the case Two different low temperature oxidation techniques has of high-power devices working at very high current densi- been developed and performed, and successive mea- ties. The characterization up to 450 C of test structures surements on the same area at different working setpoint (e.g. Greek crosses, diodes and MOSFET) has proven have been made for the evaluation of the influence on the the consistency of the calibration. The output characteris- scanning capacitance image of charge trapping and inter- tics of power IGBTand MOSFETsup to 200 C have been face state formation. The use of diamond-coated probes predicted by simulation with an excellent accuracy, even in combination with the dry oxidation technique have been by using previous releases of the simulator. Further stud- showed to provide a good reproducibility of the results, ies are going on, which are intended to investigate the im- whereas due to a better homogeneity the wet oxidation is pact of the thermal generation of the carriers, since it has recommended in case of large area samples. a paramount importance in limiting the insulation behavior of devices operated at high temperature.

Top: DESSIS simulation of the tip-sample system in a SCM measure, on the left the holes concentration in de- pletion under the tip in a p-type silicon, on the right mesh- Micro-oven inserted within the poles of the Hall magnet ing at the interface. Bottom: A plot representing one (top). Measurement of the resistivity as function of the dimensional SCM doping profile showing a good agree- temperature in a highly doped sample (bottom). ment with the respective SIMS measure.

75 Characterization of the Offset Measurements and Device Sim- Matching for MOS Transistor ulations of Transient Substrate Structures Effect in Smart-Power ICs

Personnel: Fridolin Illien Personnel: Michael Schenkel Microdul: Werner Thommen

Funding: KTI-4295.1 CMOS Array Funding: BBW, ESPRIT-29647 SUBSAFE

Partners: Microdul, HMT Microelectronic, Partners: Bosch, ISE AG, FH Aargau ESD-MSD Cluster

With the new semi custom mixed signal gate array called During switching of inductive loads (e.g. motor) by a MD300 from Microdul AG it’s possible to realize analog as smart-power IC voltages at the power transistor outputs well as digital designs with low and medium number of dive below ground potential or exceed supply voltage. units. In the MD300 chip is implemented sets of resistors, These voltage conditions turn on parasitic bipolar transis- capacities, diodes and transistors. tor which inject minority (parasitic lateral NPN transistor) and majority (parasitic vertical PNP transistor) carriers The simulation of transistor circuits requires an answer into the substrate. Investigation of these substrate cur- about the offset matching for differential transistor pairs. rents are the focus of the SUBSAFE project (as men- The setup below consists of analog transistors composed tioned in the contribution on page 77 left). from 4 parallel unit devices in serial chains of lengths 1, 2, After calibration of important device and technology pa- 3 and 6. For the statistical evaluation the measurements rameters (see contribution to the left) measurements and are performed for all modules over the wafer area. The 3D full-chip device simulations of the collection of tran- figure shows the benefit of connecting transistors in series sient injected minority carriers have been compared for to improve the offset matching. validation. Minority carriers have been injected by applying a negative voltage pulse of -1.5 V to the drain n-regions (emitter of parasitic NPN transistor) of a low-side LDMOS power transistor resulting in a substrate current of 80 mA. Collection of the injected minority carriers by a n-well on +5 V (collector) located 600 mm away from the injecting power transistor’s edge has been measured. The substrate (base) has been connected to ground through a substrate contact in the middle between power transistor and n-well and at the Schottky-type backside contact which is similar to a typical low-side smart-power IC configuration. The collected n-well current is in the order of mA and harmful for sensitive analog or digital circuitries, therefore. Measurements and 3D full-chip device simulations agree well (within a factor of 2). Thus, with the validated simulation setup substrate current effects can be investigated by means of 3D full-chip device simulations.

Schematic circuit diagram of the measured analog Measurement and 3D device simulation of transient mi- NMOS transistors (top) and fitted Gaussian density func- nority carrier collection from the substrate of a smart- tion for the drain current deviation from 80 of 84 samples. power motor control IC.

76 Minimization of Transient Device Simulation of Transient Substrate Effects Latchup

Personnel: Markus Schaldach, Michael Schenkel Personnel: Markus Schaldach ISE AG: Paul Pfäffli

Funding: BBW, ESPRIT-29647 SUBSAFE Funding: Bosch, MEDEA+ ASDESE

Partners: Bosch, ISE AG, Partners: Bosch ESD-MSD Cluster

Numerous applications ranging from class-D amplifiers in Disturbances covering a wide frequency range occur dur- mobile phones to motor control systems in cars involve ing normal operation of motor vehicle equipment. These pulse-width-modulation of inductive loads. In such appli- disturbances can cause temporary malfunction or perma- cations minority carrier injection into the substrate is sub- nent damage to electronic equipment of the vehicle. To stantial because p-n junctions of the junction isolation assure immunity of electronic devices operated in cars become forward biased. The minority carriers diffuse with- against such disturbances on supply lines these devices in the substrate and are collected at reverse biased pn are tested according to the international standard ISO junctions leading to a diffusive parasitic substrate current. 7637. Devices under test have to withstand bursts of test pulses with amplitudes of up 150 V and rise times of 5 ns Substrate coupling in a Smart Power IC driving a motor for an entire hour. It is desirable to assure immunity to was studied by transient device simulation. Both capaci- electrical disturbances prior to manufacturing. This would tive and diffusive parasitic currents were studied. It be- lead to fewer redesigns and a faster time-to-market. To at- came evident that countermeasures normally taken to tain this goal devices are put under stress in the device reduce capacitive coupling can aggravate the diffusive simulator using different types of ISO test pulses. parasitic substrate currents. Capacitive coupling can be reduced by placing grounded substrate contacts next to Transient 2D device simulations of single ISO 7637 test devices that have to be protected. This works because pulses were conducted to provoke transient latchup in a voltage changes in the substrate are reduced. The figure Smart Power IC. Simulation results clearly showed that below shows the minority carrier current density distribu- protection structures effectively reduce electrical distur- tion in the vicinity of a sensitive device with and without an bances. The figure below depicts the displacement cur- adjacent grounded substrate contact. The source of the rent density distribution with and without a grounded minority carriers is located outside the depicted cross sec- guard ring. Areas of high current density are depicted in tion in about 2 mm distance from the depicted site. The red. The bottom cross section illustrates how leaving out top cross section shows that the grounded substrate con- the protection structure increases the parasitic current. Al- tact attracts the current, hereby increasing the parasitic though current densities were high they did not lead to coupling. The bottom cross section shows the same IC transient latchup in this particular structure because the without grounding the substrate contact. In this simulation gain of the parasitic transistors was too small. the current density is increased by a factor of 10,000 when grounding the contact. Simulations allowed to identify one particular kind of test In order to minimize substrate coupling substrate contact pulse as particularly harmful to the device. Measurements positioning recommendations and active barrier concepts qualitatively matched these findings and revealed that sin- were developed. gle test pulses do not lead to transient latchup in the circuit under investigation.

Displacement current density with (top) and without Parasitic substrate current density. guard ring (bottom).

77 Research Projects

Bio–Electromagnetics and Electromagnetic Compatibility

Coordinator:

Niels Kuster (adjunct Professor, Departement of Information Technology and Electrical Engineering)

79 RF Design of Mobile Phones by A Robust FDTD Subgrid Technology Computer Aided Scheme for General Application Design (TCAD) to Enhanced Antenna Analysis

Personnel: Nicolas Chavannes Personnel: Nicolas Chavannes IT’IS: Neviana Nikoloski, Niels Kuster IT’IS: Jürg Fröhlich, Niels Kuster Motorola: Roger Tay SPEAG: Hans-Ueli Gerber Funding: KTI-4789.1 SEMCAD++, Funding: KTI-4789.1 SEMCAD++, SPEAG, ISE AG SPEAG, ISE AG

Partners: IT’IS, SPEAG, ISE AG, IT’IS Partners Partners: IT’IS, SPEAG, ISE AG

Recent years have shown tremendous growth within the Within recent years, due to its simple, straightforward ap- mobile telecommunications equipment sector, placing proach, the FDTD method has become the preferred high demands on excellent product quality combined with technique for simulating a broad range of EM applications low pricing. The requested development of highly efficient such as antenna design. Nevertheless, restrictions in spa- devices forces RF engineers to clearly call for new analy- tial resolution due to computational limitations prevent sis and optimization tools. meeting real-world engineering needs which often include highly detailed sub-objects within a largely extended This project assessed the general suitability and possible space. limitations of an enhanced TCAD environment based on the Finite-Difference Time-Domain (FDTD)method for Within this project a novel FDTD subgrid scheme was de- straightforward and efficient RF design of complex trans- veloped and implemented into a state-of-the-art simula- mitters. The study was conducted using one of the latest tion platform (SEMCAD). Due to an improved updating commercially available multi-band mobile phones. In the procedure in time and space, the scheme has proven to simulation different parameters were evaluated such as be greatly robust and highly efficient, since it may be stag- impedance, efficiency, far-field, as well as EM near-field gered without loosing stability (tested up to 1:32). The distributions and Specific Absorption Rate (SAR). The re- novel techniques finally enabled the detailed modeling of sults are compared to measurements obtained with the various complex real-world antenna configurations. A latest tools available. In addition, mechanical design is- thorough benchmarking against other numerical methods sues which show a significant influence on the EM field and measurements demonstrated the enhanced model- behavior could be predicted by simulations and were ex- ing capabilities of the presented approach applied to gen- perimentally reproduced. The obtained accurate progno- eral antenna R&D purposes. sis of all essential performance parameters by straightforward simulations suggests that state-of-the-art software packages incorporating an excellent and flexible GUI as well as enhanced modeling capabilities are suitable for device design in industrial R&D environments.

FDTD simulation of a commercially available mobile Antenna R&D: subgridding scheme in SEMCAD plat- phone. form.

80 Hybridization of a Post-Pro- A Phase-Corrected FDTD Algo- cessing Environment for MTE rithm for the Simulation of Opti- Analysis and Optimization cal Structures

Personnel: Nicolas Chavannes, Emilio Cherubini Personnel: Andreas Christ, Andreas Witzig IT’IS: Neviana Nikoloski, Niels Kuster IT’IS: Niels Kuster

Funding: KTI-4789.1 SEMCAD++, Funding: KTI-4789.1 SEMCAD++, SPEAG, ISE AG SPEAG, ISE AG

Partners: IT’IS, SPEAG, ISE AG Partners: IT’IS, SPEAG, ISE AG

Due to the heavily growing market in the field of wireless The Finite-Difference Time-Domain (FDTD)method has applications, RF engineers must rely on experimental and successfully been applied on a large range of the most numerical high-performance tools for the evaluation of the complex applications of electrodynamics. Limited compu- close EM near-field. However, in order to perform a reli- tational resources and the inherent numerical errors of the able cross-validation of the tools and moreover incorpo- method, however, impose restrictions on the maximum rate each system’s individual advantages, a hybrid data size of the problem which can be treated. Electrically large extraction and post-processing (PP)environment would structures, which require the accurate reproduction of in- greatly enhance R&D capabilities. A reliable comparison terference effects, indicate the limitations of the method. requires a consistent PP system which is able to take data In order to overcome these restrictions, a phase velocity resulting from either system as its input. Moreover, for corrected non-uniform FDTD algorithm has been devel- comparative purposes, data transformations and conser- oped. The algorithm yields generally reduced phase er- vative interpolations are performed. rors and enables distortionless wave propagation for one frequency and direction. The phase velocity corrected al- The aim of this project was the implementation of a PP gorithm has been combined with a novel technique which system which acts as a common interface to the simula- rigorously enforces the boundary conditions for electric tion platform SEMCAD and the near-field scanner and magnetic fields on planar material interfaces. DASY4, which can be easily extended according to future requirements. The new PP environment must allow ma- These techniques allow the significant decrease of the nipulation and visualization of simulated and measured number of mesh cells required for the discretization of data in a common graphical user interface (GUI). The im- large structures without increasing the numerical errors of plemented hybrid platform provides a general EM related the method. The method is currently being benchmarked R&D tool set with outstanding uniqueness. by calculating resonance frequency and loss of cylindrical cavity resonators and Vertical Cavity Surface Emitting La- sers (VCSELs). Due to the reduced computational burden, the proposed modifications enable the three-dimensional full wave simulation of VCSELs on an average PC or workstation.

Hybrid post-processing environment (DASY4-SEMCAD) allowing direct comparison of measured and simulated results (SAR distribution in SAM phantom). Electrical field distribution in a VCSE-laser.

81 Novel High-Resolution Advanced Evaluation of Temperature Probe for Measurement Results Micro-Dosimetry

Personnel: Jürgen Schuderer Personnel: Emilio Cherubini, Andreas Christ SPEAG: Thomas Schmid SPEAG: Hans-Ulrich Gerber IMTEK: G. Urban; IT’IS: Niels Kuster IT’IS: Niels Kuster Funding: BBW, EU-QUAL-01574 REFLEX, SPEAG, Funding: IT’IS, SPEAG IT’IS Partners

Partners: IT’IS, SPEAG, IT’IS Partners Partners: IT’IS, SPEAG

Spatial gradients of absorbed microwave power in tissue Recent years have shown growth in the popularity of reli- structures can be several dB/mm. This might result in lo- able high-end measurement systems designed to support cal temperature hotspots that could trigger biological re- RF engineers in R&D. In addition to enabling flexible and sponses. The smallest E-field probes have a spatial reso- complicated measurement profiles, provision of a qualita- lution not better than 1 mm3. The goal of this study was to tively high-level post-processor facilitates result interpre- develop a dosimetric temperature probe with a resolution tation and therefore enhances the value of the usability of of less than 0.1 mm3 and a sensitivity < 10 mK, in order to such R&D tools. The objectives of this project are the de- detect hotspots in SAR as well as local temperature in- velopment and implementation of such a post-processing creases. engine. The developed prototypes, which were manufactured by The main effort of this project centers on the design as- IMTEK, Freiburg, were designed as four-wire thermistors, pects of the post-processor and the accuracy of the eval- based on a thin film of evaporated amorphous germanium uation of measured data, while keeping in mind a modular (0.1 mm x 0.05 mm)to yield a high temperature coeffi- approach encouraging future development. The post-pro- cient of resistance. RF-immunity is reached by using high- cessing system allows various types of evaluation, includ- ly resistive Ti-leads as the source and sense feeding (sen- ing data extrapolation to medium interfaces, assessment sor resistance: 5 MW). The sensor is insulated by a 3mm of the spatial peak as well as averaged SAR over arbitrary thick silicon nitride layer and placed on glass or silicon volumes, etc. The system supports visual representations substrates, which guarantee temperature conductivity of evaluated data sets using the high-end graphics inter- similar to aqueous media. The noise level of 4 mK, a re- face OpenGL. Multiple evaluated results can be directly sponse time < 10 ms and self heating < 0.1 mK ensure ef- overlaid on different CAD models, e.g., antennas, phones, ficiency for sensitive and fast SAR measurements. Solu- phantoms, etc. tions to achieve sufficient insulation, which becomes a . problem when the probes are kept for days in liquid media, are currently investigated.

Microscopic picture of the probe tip showing the four sensor leads and the temperature-sensitive germanium lay- DASY4 measurement system with results from a real er. mobile phone.

82 Pilot Study Time-Domain Field Improved Methodology for Sensors Base-Station Site Evaluations

Personnel: Sven Ebert, Jürgen Schuderer Personnel: IT’IS: Neviana Nikoloski, Niels Kuster IT’IS: Axel Kramer, Niels Kuster

Funding: IT’IS Funding: FNM

Partners: IT’IS, SPEAG Partners: IT’IS

There is a great demand for near-field sensors in various In recent years the increasing number of GSM mobile areas of research and industrial applications. Due to the phone base stations has drawn attention and public con- increased clock speed and miniaturization in wireless ap- cern toward the issue of potential health hazards resulting plication devices, EMI/EMC problems will significantly in- from exposure to radio-frequency electromagnetic fields. crease. With an analysis tool like the Time-Domain Sen- In this project, the recommended and new protocols for sor, problem zones can be localized and analyzed in early base-station emission measurements shall be evaluated. design phases. The evaluation shall be conducted within a room which is The realization of a TD-sensor is tracing a new approach well characterized in terms of EM-field distributions using based on optical remote sensing, aiming for an ultra- a robotized measurement system as well as using SEM- broad frequency range from DC up to 10 GHz. In contrast CAD. The room is designed to provide worst-case stand- to related methodologies, where the sensor is a large, ing-wave patterns. passive device, the target here is to exploit active signal The objectives of this study are: I)provision of the missing transduction. This allows a significant size reduction down scientific data, instrumentation and accurate measure- to submillimeter dimensions. ment protocols for evaluation of exposure from base-sta- The sensor consists of five main components: 1)the field tion antennas, II)development of scientifically sound and transducer, 2)the frequency transducer, 3)the transmis- reliable procedures for the assessment of the measure- sion system of the field information to an amplifier unit, 4) ment uncertainty when measuring in residential and office the transmission of the signal to the data analysis unit and locations with inhomogeneous field distributions, III) 5)the auxiliary power supply of the sensor head for the transfer of the results to the standardization bodies and active solution. regulation commissions. The key parameters for sensor realization are size, sensitivity, dynamic range and speed. In a pilot study, possible technologies with respect to advantages and limitations of the most promising methods are currently being investigated.

Classic E-field probe design (to be replaced by the TD- E-field distribution 4cm above a circularly polarized multi- sensor). patch antenna.

83 Risk Assessment: Exposure Risk Assessment: Exposure Systems for Combined Toxicity/ Systems for Combined Toxicity/ Carcinogenicity Studies in Mice Carcinogenicity Studies in Rats

Personnel: Sven Ebert, Walter Oesch, Rainer Mertens Personnel: Sven Ebert, Walter Oesch, Rainer Mertens IT’IS: Neviana Nikoloski, Jürg Fröhlich, IT’IS: N. Nikoloski, J. Fröhlich, W. Kainz, Niels Kuster N. Kuster Funding: BBW, IT’IS Partners Funding: BBW, IT’IS Partners

Partners: PERFORM A Consortium Partners: PERFORM A Consortium

In the context of health risk assessment of GSM expo- Two types of exposure setups for rats, one operating at sure, two “classical” combined chronic toxicity and carci- 902 MHz and the other at 1747 MHz, had to be developed nogenicity two-year bioassays with B6C3F1 mice are cur- for the European project PERFORM A: a large toxicolog- rently being conducted at Fraunhofer ITA, Germany at ical/carcinogenic setup as well as a simultaneous replica- both frequency bands (GSM900 and DCS1800). tion setup in the context of health risk assessment of low In addition a co-carcinogenicity study using E -Pim1 trans- level exposure to the RF of mobile phones. genic mice at GSM900 is currently taking place at RBM, The evaluation of various concepts for exposure setups Italy. with respect to efficiency, homogeneity of exposure, size, IT'IS/IIS developed and installed GLP compliant exposure GLP compliance and cost led to the conclusion that the setups for these studies. These setups were developed concept which best meets all constraints is a Ferris Wheel and optimized to enable the highest possible performance with H-polarization. The realized prototype-concept of the with respect to homogeneity, independence of weight dis- rat setup is a circular cascade of 17 sectorial wave-guides tribution and coupling between animals. A wheel-shaped all excited by a loop antenna placed in the center, which resonant structure enables the simultaneous radiation of has a homogeneous circular field distribution, low losses up to 65 mice. To minimize losses all openings are metal- and well-matched impedance. For the 1800 MHz wheel lically sealed, e.g., through integrated metal plates in the the concept had to be further enhanced by reducing the covers of the mouse tubes. The exposure is monitored distance of the plates for a certain diameter around the with two field sensors, and any drift is compensated. A exciting antenna in order to guarantee single mode exci- three-stub tuner enables high efficiency with the utmost tation. More sophisticated setup shielding also needed to flexibility to accommodate changing animal size and be developed. weight. Environment sensors for temperature, O2 and hu- midity are integrated in the airflow system. A control elec- The evaluation, optimization and fine-tuning of the setup tronic provides an interface to the monitoring and control were performed using the FDTD simulation platform software. SEMCAD including its thermal solver extension. The results were carefully verified using the near-field scanner DASY4 equipped with the latest probe technology.

PERFORM A mouse exposure setup at Fraunhofer ITA The final exposure setup based on the Ferris wheel con- in Hanover, Germany. cept with H-polarization

84 Risk Assessment: Preliminary Risk Assessment: Preliminary Dosimetry of the Mouse Setup Dosimetry of Rat Setup

Personnel: Sven Ebert, Walter Oesch, Rainer Mertens; Personnel: Walter Oesch, Rainer Mertens IT’IS: Neviana Nikoloski, Jürg Fröhlich, ARCS: M. Frauscher; IT’IS: N. Nikoloski, J. Wolfgang Kainz, Niels Kuster Fröhlich, W. Kainz, N. Kuster Funding: BBW, IT’IS Partners Funding: BBW, IT’IS Partners

Partners: PERFORM A Consortium Partners: PERFORM A Consortium

The preliminary dosimetry gives initial predictions of the Life-span exposure at uniform doses is one of the basic absorbed radiation in mice of the PERFORM A mouse ex- requirements in the PERFORM A project. The objective of posure system. this study was to assess the whole-body as well as organ- Complex field distributions occur in biological bodies specific SAR of rats from incident exposures at 902 MHz when they are exposed to electromagnetic radiation. In and 1747 MHz as a function of sex, age and weight. The order to assess the dosimetry it is crucial to know the dis- evaluation of the setup was performed using numerical tribution of the field in the biological body. Therefore, sev- dosimetry with the FDTD simulation platform SEMCAD. eral scalable numerical mouse models were developed Various animal phantoms were generated for the purpose from high-quality, high-resolution (<1 mm)microtom- of this study. More than 100 different regions were dis- scans. These models were used for assessing averaged cretized. SEMCAD was extended to automatically assess SAR for the whole body and certain organs through simu- the averaged, maximum, and minimum SAR values for lations with the FDTD-based simulation platform SEM- the whole-body as well as every organ and tissue. De- CAD. tailed numerical models of the two physical exposure setups were generated and optimized with respect to accu- Extensive experimental evaluation and determination of racy and numerical efficiency. These numerical setups the SAR were performed through measurements in dum- were extensively validated by comparing performance mies filled with a liquid which has the same dielectric pa- with detailed measurements of the two physical setups rameters as muscle tissue. The SAR distribution in the using differing dummy rats in two different setup configu- wheel was determined with the temperature method as rations: (A)synthetic, symmetrical phantoms and (B)rat- well as with E-field measurements using sophisticated like phantoms placed inside the tubes. The experimental near-field probes with a DASY3 scanning system. evaluations have been conducted using the near-field In the PERFORM A exposure system mice are exposed scanner DASY4 equipped with the latest probe technolo- to a SAR of about 5 W/kg using a standard GSM/DCS sig- gy (E- and H-field as well as temperature probes). The re- nal. quired incident field as a function of sex, age and weight for constant whole-body averaged SAR was assessed using detailed rat phantoms (male & female)of different body weights accordingly positioned inside the exposure setup.

High resolution numerical mouse model in the simulated E-field distribution in one of the sectorial waveguides of setup and DASY3 near-field scanning system. the Ferris wheel including the numerical rat phantom.

85 Risk Assessment: Risk Assessment: Characterization of a RF Setup Characterization of an ELF for In-Vitro Studies Setup for In-Vitro Studies

Personnel: Jürgen Schuderer, Walter Oesch, Rainer Personnel: Jürgen Schuderer, Walter Oesch, Rainer Mertens Mertens IT’IS: Niels Kuster IT’IS: Niels Kuster Funding: BBW, EU-QUAL-01574 REFLEX, Funding: BBW, EU-QUAL-01574 REFLEX, IT’IS Partners IT’IS Partners

Partners: REFLEX Consortium Partners: REFLEX Consortium

The objective of this study was to characterize the field The task of IIS/IT'IS was to develop a highly flexible GLP conditions and their uncertainties for the recently devel- compatible in-vitro setup for ELF (extremely low frequen- oped exposure setup, which was built to perform in-vitro cy)magnetic field exposures and to characterize the field risk assessment studies at GSM 1800 MHz. and environmental conditions inside the setup. The setup consists of two single-mode resonator cavities The setup consists of two four-coil systems, each of which that can be loaded with several Petri dishes containing is placed inside a m-metal box. The currents in the bifilar cell medium and the biological cells as a monolayer at the coils can be switched parallel for field exposure or non- dish bottom. The dishes were put in the H-field maxima of parallel for sham control. The cells are located inside Petri the standing waves in order to achieve the most homoge- dishes that can be placed in the center area of the coils. nous SAR distribution. The setup was numerically ana- Field characterization included numerical simulations and lyzed by the FDTD simulation platform SEMCAD and ex- experimental verification using a high-resolution Gauss- perimentally verified with the DASY3 near-field scanning meter probe. Additionally, an analysis of possible varia- system. tions during exposure as well as an uncertainty evaluation The field distribution inside the medium has been investi- of the applied methods has been performed. Unwanted gated for several medium volumes and also for variations electric fields have been analyzed with an E-field probe of the geometry. Sources for variations and uncertainties and compensated by a shielding box. No differences for were divided into three areas: (1)inhomogeneity of the the temperatures inside the cell media in the exposure SAR distribution (< 30%), which is dependent upon the and sham chambers could be measured, since both coils medium volume, (2)variation in SAR (5%)due to dish become heated by the same currents. The vibration load misplacement, frequency dependency of the waveguide for the Petri dish has been assessed with an accelerome- coupler and field sensor, noise and drift, (3)absolute un- ter probe for vertical and horizontal directions. certainty (12%)due to the numerical method, method for the determination of dielectric properties, calibration method and field measuring technique during exposure. Furthermore, the temperature response of the medium has been assessed in terms of the incident field strength, liquid height and airflow. This is an important analysis, since the exclusion of biological effects due to temperature changes was a strict requirement.

H-field distribution in the empty and loaded waveguide ELF coil system inside the m-metal shielding box. The resonator. The presence of dielectric material inside the holder for the Petri dishes has been removed from the resonator leads to a reduction of the wavelength. box.

86 Risk Assessment: Effect of EMF Exposure on Detailed Dosimetry of Human Cerebral Blood Flow and Sleep Exposure Setup EEG

Personnel: Jürgen Schuderer Personnel: Jürgen Schuderer UNIZH: Peter Achermann UNIZH: Peter Achermann IT’IS: Niels Kuster IT’IS: Niels Kuster Funding: NMF, IT’IS Partners Funding: FNM, IT’IS Partners

Partners: IT’IS, IT’IS Partners Partners: IT’IS, IT’IS Partners

The objective of this study was to develop an exposure There is limited data on the possible effects resulting from setup for human risk assessment studies at 900 MHz and electromagnetic field (EMF)exposure on brain function. to provide a detailed characterization of the field distribu- Since head and brain regions become directly exposed tion inside the brain and its functional regions. while using a mobile phone, effects on brain physiology The developed setup consists of two patch antennas are of special interest for health risk research. In this pro- mounted on both sides of the head of a sitting subject at ject the effect of EMF versus sham control exposure on a distance of 11 cm with neither or one of them activated. waking regional cerebral blood flow (rCBF)and on waking The simulation platform SEMCAD was used as the nu- and sleep EEG has been investigated in several studies. merical TCAD environment for the optimization and anal- After unilateral head exposure to 30 minute GSM-like ysis of the SAR distribution. The currently most detailed pulse modulated (pm)900 MHz EMF, positron emission and accurate human head model was the basis for this tomography (PET)demonstrated increased relative rCBF study. 23 different tissue types, including functional sub- in the dorsolateral prefrontal cortex. This data provides regions of the brain have been distinguished and tissue- the first demonstration of an immediate post-exposure ef- specific statistical data as mean values, standard devia- fect on rCBF. Nighttime sleep was polysomnographically tions, etc. for the SAR are provided. Additionally, the vari- recorded after and during EMF exposure. Following pm- ation of these values with respect to different head anato- EMF exposure, EEG power was enhanced in the alpha mies has been investigated and the uncertainties of the frequency range prior to sleep onset and in the spindle applied numerical and experimental methods have been frequency range during stage 2 sleep. Exposure to EMF assessed by simulations and measurements. The numer- without pm (CW)did not enhance power in the waking or ical results were validated by measuring the free fields as sleep EEG. The EEG effects have been confirmed by us- well as the induced fields, which were determined with the ing two different exposure setups (exposure unilateral and DASY3 near-field scanning system inside a head phan- from top)and two different study protocols (exposure prior tom. to and during sleep).

Simulated SAR distribution inside the numerical head phantom. Axial, coronal and sagittal sections are shown. The tissue model is shown in the top panels: thalamus (green), grey matter (dark grey), white matter (white), CSF (cyan), cerebellum (brown), middle brain (light Regions showing higher relative regional cerebral blood gray), muscle (dark orange), air (blue), skin (orange) and flow after pulse modulation (pm)EMF exposure com- bone (yellow). pared to sham exposure.

87 Controlling and Monitoring Data Processing and Analysis Software of Exposure Systems of Exposure and Environmental Parameters

Personnel: Walter Oesch, David Perels Personnel: Walter Oesch, David Perels IT’IS: Niels Kuster IT’IS: Niels Kuster

Funding: BBW, EU-QUAL-01574 REFLEX, Funding: BBW, EU-QUAL-01574 REFLEX, IT’IS Partners IT’IS Partners

Partners: PERFORM A Consortium, REFLEX Partners: PERFORM A Consortium, REFLEX Consortium Consortium

In order to conduct experiments in accordance with the Modern in-vitro and in-vivo electromagnetic exposure set- principles of GLP (Good Laboratory Practice), bio-experi- ups are software controlled. An important task of a con- ments addressing the possible hazardous effects of elec- trolling and monitoring software is to collect and store the tromagnetic exposures must be performed under highly entire sequence of hardware commands and sensor data controlled conditions with respect to the biological system to enable full reconstruction of the entire experiment for and environmental parameters. However, the application each individual run. Since most bio-experiments are con- of well defined and controlled EMF exposures to bio-sys- ducted in a blinded or double-blinded fashion, these data tems is a complex task, in particular for RF experiments. should be encoded. It requires customized equipment optimized for the partic- The aim of this project was to design and develop an en- ular experiment. Furthermore, the experiments often coded data format and an analysis software for exposure need to be conducted in a blinded or double-blinded fash- setup data. The implementation decodes the data, gener- ion. These tasks can only be satisfactorily met with elab- ates a detailed summary of all relevant parameters, cre- orate controlling and monitoring software. ates charts and saves the output in a pdf-formatted file. The objective of this study was to design and implement Furthermore, the results are automatically e-mailed to the a flexible and extensible software which can be used for a bio-laboratories conducting the experiments for their own wide range of exposure systems, including both in-vitro analysis. The analysis software greatly enhances the sig- and in-vivo systems. In particular, a special concurrency nificance of bio-experimental studies, since unstable elec- model consisting of a combination of multithreading and tromagnetic fields and abnormal environmental parame- message queuing has been developed, as well as a con- ters are reliably detected. sistent mechanism of passing data from a data acquisition class to a sensor class. The software has been written in Visual C++ under the viewpoint of maximum reuse of source code. This goal has been achieved by application of software design patterns wherever possible. Especially suited are the State, Observer, Decorator, Publisher, Sub- scriber and Template Patterns.

Two data plots of an experiment. Top: GSM signal statis- Front panel of controlling and monitoring software. tics. Bottom: Field deviation of target.

88 Risk Assessment: Standards: Scalability of Advanced Animal Models In-Vivo to Human Exposures

Personnel: IT’IS: Neviana Nikoloski, Jürg Fröhlich, Personnel: Nicolas Chavannes Eva Schumacher, Miriam Wanner, Niels IT’IS: Jürg Fröhlich, Niels Kuster Kuster Funding: BfS-SAR, BBW, PERFORM A Funding: KTI-4789.1 SEMCAD++, IT’IS Partners

Partners: IT’IS, IT’IS Partners Partners: IT’IS, SPEAG, ISE AG

Previous studies have revealed that the existing numeri- One issue of great concern within risk assessment of mo- cal animal models developed for dosimetric evaluations in bile telecommunication devices regarding compliance bio-experiments, including those derived from MRI and testing and design of bio-experiments is the ratio between CT, with resolutions larger than 1 mm are insufficient to the spatial peak SAR and the whole body SAR within ex- achieve reliable assessment of the organ-averaged SAR posed animals and humans. Since measurements within for certain organs, e.g., for the brain. Thus, generation of living bodies are not easily realizable, appropriate numer- high-resolution animal models with slice separation of ical and physical models have to be developed. Accurate less than 0.5 mm is necessary for enabling the provision and reliable numerical assessment of SAR distributions of accurate dosimetry, including a sound uncertainty anal- within animals and the human body require high-resolu- ysis, leading to significant increase of the quality of bio-ex- tion anatomical models. periments. The objective of this project was to develop Within this study the SAR distribution in a mouse, a rat models for rats and mice of varying weights and sexes, and a human model will be calculated at the technically which have the same postures used during exposure in a relevant frequencies of 450 MHz, 900 MHz, 1.8 GH, and performed in-vivo experiment and implement these mod- 5 GHz, and for different polarizations with respect to an in- els into the simulation platform SEMCAD. A novel method coming plane wave. High-resolution animal models have using the microtome slicing technique showed significant been generated. The SAR distribution within the animals advantages in the generation of high-resolution models at the different frequencies will be compared to the distri- for animals with different postures and weights, based on bution within the human body. Simulated SAR distribu- color pictures that are very well suited for further segmen- tions will be validated with appropriate measurements tation. With this method a resolution of up to within phantoms at all frequencies and within an animal 0.05x0.05x0.05 mm3 can be achieved. The novel com- cadaver at one frequency. In addition the averaged SAR pound format of SEMCAD allows an efficient 3D real-time values over 0.01, 0.1 and 1 g of tissue in animals and over modeling of such complex structures and in combination 1 and 10 g for the human model shall be evaluated. with the implemented new features enables not only the extraction of organ- and tissue-averaged specific SAR, but also (1)spatial peak SAR in all organs (0.1 g),(2)organ average SAR values, (3)whole body average SAR, (4)spatial peak SAR in the whole animal, (5)dependence of the dose on animal posture and size, (6)assessment of the variability and uncertainty of other exposure parameters as well as assessment of the thermal load.

Numerical mouse model enabling extraction of various SAR distribution in a human and a mouse (E,H,k-polar- organ and tissue specific averaged SAR values. ization) at 900 MHz (SEMCAD).

89 Standards: Evaluation of Standards: Implementation and Human-Head Phantoms for Application of Novel IEEE MTE Compliance Testing SCC34 SAR Extraction

Personnel: Andreas Christ, Nicolas Chavannes Personnel: Nicolas Chavannes, Andreas Christ IT’IS: Neviana Nikoloski, Niels Kuster, IT’IS: Jürg Fröhlich, Niels Kuster H.-U. Gerber; SPEAG: K. Pokovic Funding: IT’IS, SPEAG, IT’IS Partners Funding: KTI-4789.1 SEMCAD++, IT’IS Partners, SPEAG, ISE AG

Partners: IT’IS, SPEAG Partners: IT’IS, SPEAG, ISE AG

Human head phantoms are the cornerstone in compli- International standardization bodies have introduced ance testing of Mobile Telecommunications Equipment comprehensive mandatory safety guidelines governing (MTE)with radiation safety standards. In order to ensure exposure to RF energy. These include limits on the Spe- that a device does not expose its user to a radiation level cific Absorption Rate (SAR)which is the unit of measure- above the limits, the SAR assessment procedure has to ment for the amount of RF energy absorbed by the human represent a conservative approach. body. An IEEE standard was evaluated by the working Within this study, the Generic Twin Phantom and the SAM group SCC34 - subcommittee 2. This standard is meant phantom were compared to a high-resolution anatomical to take all situations into account arising from compliance head model. The Generic Twin Phantom has become a testing of mobile phones. Body tissue and tissue belong- quasi-standard as part of the DASY3 dosimetric assessing to extremities (ear, hand, etc.)are evaluated separate- ment system. The SAM phantom has recently been ly. The evaluation of the peak average SAR over 1 and agreed upon by several international regulatory bodies 10g is a demanding task. Therefore the implementation of (e.g., IEEE, CENELEC) to serve as the new standard. such a standard has to be very efficient in terms of the computational language used and in terms of algorithmic The Generic Twin Phantom and the SAM phantom were aspects. characterized numerically (FDTD)and experimentally. Comparison with numerical data from the anatomical In this project the novel routine has been implemented head model confirmed that both phantoms yield a conser- into the SEMCAD simulation environment. The algorithm vative estimation of the SAR. shall enable the evaluation of the peak average SAR within arbitrary highly inhomogeneous structures over any required cubical mass. The algorithm is optimized with respect to computational efficiency. The implementation was validated using different canonical examples that can be compared to measurements.

Dosimetry of mobile phones: SAR distribution on the sur- Human- head phantom exposed to MTE radiation. (Top: face of specific tissues of anatomical human head (SEM- numerical model, bottom: measurement setup) CAD).

90 Education Program

Student Projects

Coordinator:

Norbert Felber

91 Teaching microelectronics is one of the core activities of the Integrated Systems Laboratory. Shortly after the laboratory was founded in 1986, it started to offer graduate students term projects in IC design. Probably as the first European university ETH financed the fabrication of student chips. This gave students the opportunity to carry out a VLSI design project from the specification to the test of their own silicon chips. Still today, the majority of student term projects at IIS are in practical chip design and many diploma projects include the realization of integrated circuits or the development of components as contribution to research ASICs. The tools used by the student are the same as in research and by our main industry partners: Modelsim for VHDL simulation, Synopsys for synthesis, Cadence for the physical design, and Synopsys again for test generation. The overhead of three design environments requires a considerable effort by our students who do not just want to learn IC design per se, but realize an often challenging and complex project. Despite the hard work with many traps and complica- tions, almost all chips finally work as intended. During the 15 weeks of a semester thesis, groups of one to three students put 50% of their work load each into the realization of a chip (sometimes considerably more). First-time-right digital ICs of almost industrial complexity level often result. This is only possible due to the sound VLSI education and an excellent support for design and test offered by the PhD students of our Laboratory. The group of Qiuting Huang complements the field of IC design with projects for mixed-signal and analog chips. The yellow bars in the figure above illustrate the total number of student IC design theses (digital and analog) that have been realized as term projects and diploma theses during the last ten years. We would like to emphasize that, without the funding by the Board of the ETH Zürich in the project Lehre und Forschung in Mikroelektronik (Education and Research in Microelectronics), it never would have become possible to give more than 400 young engineers the experience of designing real silicon. Most of our former students are now working in the microelectronics research and development centers of Swiss industry, while others found the way to well-known international companies all over the world. Besides the VLSI projects our laboratory also offers student projects in all its other fields of research. Especially the simulation of optoelectronics devices and effects attracts an increasing number of students. But also hardware and combined software-hardware projects are popular. The total number of student projects at IIS is dis- played by the blue bars of the graph. The following pages give short descriptions of most student term and diploma theses executed during the winter term 2000/2001 and the summer term 2001. Some student projects which are strongly related to research projects can be found in the research chapter (page 66 right).

92 EDGE Equalizer Acceleration Tempo Rex – A GPS Reference Unit Time Controller for FireWireTM

Personnel: Felix Becheiraz; Personnel: Silvio Dragone; Hubert Kaeslin (assistant); Eric Roth, Thomas Boesch (assistants) Daniel Müller (Philips) Funding: Philips, ETHZ Funding: ETHZ

Partners: Philips Partners: BridgeCo

EDGE (Enhanced Data Rates for GSM Evolution) is an In professional audio studios all equipment is synchro- extension of the current GSM standard. Replacing the nized to a common clock. Today a dedicated coax cable original gaussian-filtered minimum shift keying modula- carries this house sync signal. In the future, FireWireTM tion by 8-PSK (Phase Shift Keying) makes it possible to could distribute audio data as well as the house sync. The triple the bit rate for the same symbol rate. However, a dif- goal of this semester thesis was the development of an in- ficulty is that channel equalization at the receiver end is terface that translates accurate reference time informa- highly critical due to strong intersymbol interference. The tion from a GPS receiver into reference time packets for a necessary computations are likely to burden the embed- FireWireTM bus. ded DSPs of cellular phones to their limit even if an RSSE (Reduced State Sequence Estimation) algorithm is being First, a reliable concept for timing distribution was investi- employed. gated. Depending on the bus configuration the chip called “Tempo Rex” generates timing packets itself or advises The goal of this project, therefore, was to develop a spe- another bus member to adjust its reference time to the cialized equalizer acceleration unit as a virtual component GPS time. In the latter case transfer delays between bus for integration into a GSM-EDGE baseband processor members are compensated using ping packets for round- chip. After the most onerous and repetitive tasks had trip delay measurements. This method aligns the phase been identified, a variety of alternative architectures with offsets between any two nodes with an accuracy of better different amounts of hardware resources have been stud- than 100 ns. ied in order to find an optimum trade-off between hardware costs and effectiveness. The final design occupies Tempo Rex was implemented on a CMOS 0.6 µm 3LM an area of approximately 107 F2 (where F stands for the process from AMS. It occupies a die area of 10.2 mm2.In minimum feature size) and unburdens the embedded addition to the ASIC a software interface was developed DSP by a computational load of 26MIPS. to directly configure Tempo Rex and the FireWireTM chip set via a serial interface.

GSM transmitter and receiver block diagrams with indi- cation of the newly developed equalizer acceleration unit in the receiver. In between is a symbolic representation Microphotograph of the Tempo Rex chip and an applica- of the modulation that enables enhanced throughput. tion example.

93 MP3 Player Chip: MP3 Player Chip: Decoder Part Digital Signal Processing Part

Personnel: Elmar Schmid, Tamas Weber; Personnel: Jonas Bandi, Marc Wegmüller; Thomas Boesch, Eric Roth (assistants) Thomas Boesch, Eric Roth (assistants)

Funding: ETHZ Funding: ETHZ

In this semester thesis the data decoding part of an MP3 The goal of this semester thesis was the signal process- player chip has been developed. The signal processing ing part of the M3 player project introduced on the left half was part of another semester project (see on the right). of this page (bottom block in the figure). This circuit re- The circuit reads MPEG1 audio layer III standard (ISO/ ceives the decoded spectral components and the side in- IEC11172-3) audio data form a SmartMediaTM storage formation from the decoder. device. The module re-quantizes the spectral data according to The compressed spectral audio data and control informa- the sideband information, reorders them, and performs tion (header data and scale-factors) are extracted. Subse- the joint stereo processing. After the alias reduction the quently, the audio data is Hoffman decoded. The decoded Inverse Modified Discrete Cosine Transform (IMDCT) re- data with all control information is buffered in an internal synthesizes the time-domain samples of the narrow fre- memory and read by the DSP part for audio signal pro- quency bands. Finally, these samples get re-combined to cessing. After signal processing the PCM audio data is re- the final PCM signal by the poly-phase filter bank. turned and transferred via an I2S interface to an external The Project was an experiment of realizing the MP3 de- A/D converter. The external A/D converter is controlled coder as dedicated hardware in silicon in order to explore and supplied with clocks to support three different sam- the potential of this solution in comparison to the com- pling frequencies. A controller manages and coordinates monly realized digital signal processor implementation. It all processing blocks of the decoding process. The com- has shown that the algorithm is not at all optimal for inte- plete MP3 decoder does not require any additional exter- gration as dedicated circuit. The large amount of required nal memories. buffer memories and the huge number of operation An external user interface provides the basic capabilities modes are the major drawback. The algorithm could be to control the MP3 player chip. It consists of five different considerably optimized in both silicon area and energy signals: Skip Backward, Skip Forward, Play, Break and dissipation, however at the cost of violating the standard. Stop. Since this was a VLSI education project, the signal processing chip has been designed to the end and sent for fabrication. After return it has been tested by the students. It showed full functionality.

Audio data flow through the MP3 decoder chip. All blocks except the DSP block are part of this design. The project Chip microphotograph of the MP3 decoder signal pro- led to verified VHDL code. cessing circuit.

94 Development of a Reusable 8-bit Microprocessor Core M68000 Microprocessor Core

Personnel: Chiara Martelli; Personnel: Michael Lerjen; Robert Reutemann, Stephan Oetiker (assistant) Thomas Villiger (assistants) Funding: ETHZ Funding: ETHZ

The goal of this diploma thesis was the development of a Most actual chip designs need large configuration inter- reusable M68000 compatible processor core. This Virtual faces or complex finite state machines with a large num- Component (VC) would allow the inclusion of a processor ber of state transitions. These cases are troublesome to with full development tool support in other projects. implement, and, due to the extreme number of possible state sequences they can not be verified satisfactorily. A First, a behavioral-level VHDL simulation model for the programmable on-chip micro-controller is the preferred processor core was developed. This model was used to solution to this problem. In the course of this project a pro- verify the correct interpretation of the 68000 code and to cessor which is compliant to the Motorola™ 68HC05 in- serve as reference for the implementation. In a second struction set was developed and can be used as a step, an architecture has been devised and the RTL level parametrizable virtual component (VC) in future projects. VHDL synthesis code has been developed. The requirements to such a microcontroller are compact- The architecture is a multi-cycle non-pipelined implemen- ness and easy programmability. Neither large word sizes tation of the 68000 instruction set. It splits the core into and complex instructions, nor huge computational re- three main units: a central controller responsible for in- sources are needed. The success of the VC depends on struction decoding and sequencing, an address calcula- the availability of software development tools, though. For tion unit, and the main execution unit. The execution unit the 68HC05 there exists a reasonable number of tools itself is split into five subunits for different types of com- and the designer can choose between high-level lan- mands. A separate bus interface unit is responsible for guage or assembler. Various memories can be connected communication with memory and I/O devices. This archi- to the core. If the program is small and fixed, its code can tecture decouples the interface from the core and allows even be synthesized as combinatorial logic. Other possi- the inclusion of dedicated I/O units for specific applica- bilities include synchronous and asynchronous RAM, tions. ROM, or latch banks (Designware™ RAMs). Only the address decoder needs to be adapted. Currently, the RTL code is being completed and is optimized for synthesis. A first test implementation of the The instruction set was tested using a C language model. core, possibly on an FPGA, will be used for functional ver- To further guarantee its correctness, the VC was imple- ification of the virtual component. mented in a VIRTEX™ XCV400 FPGA. As program and data memory one of the on-chip Block RAMs of the FPGA was used and the program code has directly been synthesized into the configuration bitstream. LEDs were used to demonstrate memory-mapped ports. The FPGA implementation achieved a frequency of 28 MHz and used 376 slices corresponding to 5396gate equivalents of the FP- GA. This equals to 8% of the XCV400 resources which confirms the compactness of the design.

Architecture overview of M68000 core. Processor core test implementation in a FPGA.

95 Performance Analysis of AMD Low-Voltage, Low-Power Southbridge “Zorak” DDA-based Frontend with Improved Dynamic Range

Personnel: Peter Lüthi; Personnel: Yue Li; Frank Dresig (AMD), Michael Oberle (assistant) Norbert Felber (assistants) Funding: AMD, ETHZ Funding: ETHZ

Partners: AMD (Dresden)

Optimization of highly integrated System-on-Chip (SoC) Recent trends in medical technology demand miniatur- designs assumes a thorough knowledge of the internal ized and portable devices for continuous sensing of vital structures. This includes all circuit blocks and bus proto- parameters. Since these devices will operate with a single cols, as well as their modes of operation. Performance battery, power consumption becomes tight. Especially, a analysis further requires knowledge of the traffic occurring lower supply voltage impacts the design of the analog on internal and external bus systems. sensor readout circuitry. The low input dynamic range The thesis analyzed the performance of an early proto- makes the system more sensitive to in-band noise. type (code name: “Zorak”) of the next-generation AMD Southbridge and investigated possible performance Rail-to-rail input circuits represent one possibility to im- shortcomings. A theoretical analysis of bandwidth and prove the dynamic range of the frontend even at very low data rate of various blocks, measurements, and thorough supply voltages. Already proposed solutions for medical discussions led to the implementation of a performance applications use input buffers with rail-to-rail input and analysis environment. output stages. These circuits are usually feeding a 2- or 3- opamp topology to amplify the sensor signals. However, The implementation of this analysis tool was based on a this approach to improve the dynamic input range increas- bottom-up approach by taking an existing RTL description es the current consumption of the overall frontend unnec- and building the necessary blocks on top of it. This ap- essarily. proach ensures that the results of the performance analysis are highly correlated to the underlying hardware. The solution developed within this thesis applies the con- The aim of this performance analysis environment is not cept of a rail-to-rail input stage to a differential-difference only performance optimization. An additional feature is to amplifier (DDA) with resistive feedback. Challenges due highlight the utilization of several busses and to extract to the closed-loop operation, and due to the common- important information for the integration of new circuit mode feedback required for fully-differential operation, blocks. With this insight, the chip architect gets valuable have been investigated. Simulations of the DDA circuit in information to choose the most efficient bus attachment of a 0.6 µm CMOS technology at 2.2 V supply voltage re- a new circuit block. vealed that the signal resolution is limited to 9 bit. This is due to the imperfect control loop of the rail-to-rail input stages for DDAs.

Schematic diagram of the performance analysis environ- Schematic view of a differential difference instrumenta- ment (partial view). tion amplifier.

96 Design and Implementation of a Arithmetic Coding and its Fast Sample-and-Hold Circuit Efﬁcient Implementation

Personnel: Yingyun Zha; Personnel: Giuseppe Acunto; Miquel Sans; Jürgen Hertle, Pio Balmelli (assistants) Andy Burg (assistant)

Funding: ETHZ Funding: ETHZ

One of the most crucial building blocks in modern analog- Arithmetic coding is a lossless data compression (or en- to-digital converters is the sample-and-hold stage. Its re- tropy coding) scheme. Compared to the more popular quirements are very demanding because the signal must prefix-coding schemes (such as Huffman coding) it allows be sampled at full bandwidth with an accuracy higher than to encode symbols with fractions of a bit and consequent- the converter’s specifications. Further, the nonlinear ON ly exhibits a much higher compression efficiency. In appli- resistance of the sampling switch - usually a transmission cations, where the probability distribution of the data gate - must be taken into account, because the amplitude source is not a-priori known, or changes over time, an of the input signal must be as high as possible to alleviate adaptive coding scheme is required. The arithmetic cod- the requirements on the following ADC. ing algorithm is based directly on the symbol probabilities The aim of this diploma thesis was the design of a 10 bit and does not require an intermediate codebook that 100 MS/s sample-and-hold circuit, with special emphasis needs to be recomputed whenever the distribution chang- on the optimization of the sampling switch, especially in es. It is therefore very well suited for adaptive implemen- terms of harmonic distortion. An interleaved architecture tations. has been chosen in order to reduce the bandwidth and Despite these advantages hardware implementations of settling requirements of the amplifiers. the algorithm are rare. The main reasons for this are the The investigation of the switches revealed that an opti- facts that an arithmetic coder has a much higher complex- mum exists for the ratio between the width of the NMOS- ity than a prefix en-/decoder and that the original arith- and the PMOS-transistor in a transmission gate. The fig- metic coding algorithm uses infinite precision arithmetic. ure shows that a ratio of approximately 2.6(technology In order to efficiently implement the algorithm with finite dependent) leads to a substantial reduction of total har- precision arithmetic, some minor modifications to the al- monic distortion. gorithm need to be made. In this project the core of a configurable arithmetic coder was developed and realized as Virtual Component (VC) in VHDL. It implements the complete en-/decoding algorithm for finite precision arithmetic. Various parameters of the design, such as the number of symbols in the alphabet, the precision of the probabilities, and the resolution of the encoding procedure can be configured. An analysis of the design’s complexity depending on the configuration was performed. For the probability modeler a non-adaptive behavioral model was used. It will be replaced with a real implementation of an adaptive source model in a fol- low-up project.

The sample-and-hold circuit and a transmission gate to realize the switches. Graph of total harmonic distortion caused by the switch. Test image (Barbara) and entropy of a binary alphabet.

97 Real-Time Video Compression JPEG-3D Video CoDec System and Error Resilience Software Methods

Personnel: Alp Bozaci, Daniel Otti; Personnel: Alex Burri, Daniel Hirt; Andy Burg (assistant) Andy Burg (assistant); Johan Garcia (Karlstad University) Funding: ETHZ Funding: ETHZ

Partners: Karlstad University (Sweden)

In previous projects a low-complexity video compression 3D-DCT video compression is a scheme to efficiently algorithm based on a 3D-Discrete Cosine Transform compress video in real-time. Efficiency is achieved by (DCT) has been developed and implemented in software avoiding the complex motion estimation algorithms which and as an ASIC at the IIS. The scheme avoids the com- are used in MPEG-2/4. Instead, an extension of the 2D- putationally complex motion estimation algorithm which is DCT, which is used in the JPEG still image compression used in most other video compression systems such as standard, is used to remove inter-frame correlation in vid- MPEG-2/4. eo sequences. However, up to this point, no elaborate In the first part of this diploma thesis a hardware concept storage format for the 3D-DCT scheme has been devel- and two PCBs were developed that should allow to con- oped. nect the ASIC to two standard PAL video codecs on one In this project the basic concept of the 3D-DCT video side and to the PCI-bus of a PC on the other side through compression was integrated with the JPEG still image for- a Lucent ORCA-FPGA. The necessary Windows drivers mat and a software implementation was developed. The for the communication and the configuration were also de- basis for this was the publicly available IJG JPEG imple- velopped. mentation. From this starting point a complete JPEG-3D In the second part of the project, various methods to add based video compression system was realized. It sup- error resilience to the existing 3D-DCT compression ports most of JPEGs error resilience capabilities and adds scheme were investigated. The goal hereby was to find only minor modifications to the original still image JPEG methods that would allow the system to recover quickly format to make it suitable for video. In a subsequent stu- from errors in the transmitted data stream. In the original dent project, camera and network interfaces will be add- implementation such errors led to a complete failure of the ed. decoder. A simple but effective method which inserts synchronization points and parity-bits in regular intervals into the compressed data stream was chosen and added to the original software implementation. The introduced additional overhead for this technique was analyzed and the effectiveness of the approach was demonstrated through simulations.

Frames from a compressed video sequence (carphone) Comparison between the still image JPEG algorithm and with transmission errors (marked with yellow circles). the JPEG-3D video format.

98 Digital Precision Altimeter Battery Charge Controller for a Diving Lamp

Personnel: Marc Secall Wimmel; Personnel: David Satz; Norbert Felber (assistant) Frank Gürkaynak, Norbert Felber (assistants) Funding: ETHZ Funding: ETHZ

Partners: Keldan AG (Switzerland)

Global Positioning Systems (GPS) are no reason for Modern rechargeable Nickel-Metal-Hybrid (NiMH) batter- mountaineers and other sports men not to use old-fash- ies offer long battery life and high operation currents, but ioned pressure-based altimeters. These work also in the are extremely costly. Preserving battery life is therefore a shadow of rocks, need no (or in case of the electronic ver- key issue of recharging circuits for NiMH batteries. sion much less) batteries, and are much faster to give a In this project, a battery charge controller for a diving lamp new reading. The goal of this student project was to ex- was developed. For a diving lamp it is important to offer plore the maximal sensitivity and precision that can be the operator the precise amount of charge left in the de- reached by today’s available electronic pressure sensors vice and to clearly warn the user before the battery is no with subsequent digital correction of non-idealities. Low longer able to support the lamp. Furthermore, the com- energy dissipation was an additional requirement. plexity of the controller is limited by physical dimensions The work included the evaluation of the best suited sen- and power consumption requirements. sors, A/D converters, and other components. It was decid- The battery charge controller continuously monitors the ed to concentrate on the signal conditioning and its current, voltage and the temperature of the battery to de- optimization. Therefore a PC was used to play the role of termine the amount of battery charge during operation. the microprocessor and display during this evaluation The controller automatically detects when it is attached to phase. A printed circuit board for the two most promising a charging unit and regulates the amount of charging cur- sensors, amplifier, filter and converter has been devel- rent to obtain the fastest possible charging time without oped. Characterizations in pressure chambers have been endangering the battery itself. The controller is imple- performed until it became clear that the realized system mented using a XILINX Coolrunner CPLD and has been had much higher resolution than the available equipment. verified to function under different operational situations. Correction of non-linearities, temperature, calibration support and numerical as well as graphical display have been realized in C++ on the personal computer. The figure illustrates the sensitivity of the instrument. The steps in the pressure-versus-time curve are due to repeat- ed up-down movement of 50 cm and the envelope dem- onstrates the short-time pressure change.

Typical charging curve for a NiMH battery (above) and Graphical display of the altimeter prototype system (dig- the block diagram of the battery charge controller (be- ital correction and display on PC). low).

99 High-Precision Audio Signal DDS-based High-Frequency Generator based on Direct Function Generator on a PCI Digital Synthesis (DDS) Board

Personnel: Michael Gerber, Philipp Inderbizin; Personnel: Simone Buzzi, Davide Cescato, Norbert Felber (assistant) Simon Häne; Matthias Brändli, Norbert Felber (assistants) Funding: ETHZ Funding: ETHZ

In an earlier term project an integrated circuit has been re- This semester thesis makes use of the same DDS signal alized which performs signal generation on the basis of generator ASIC as in the project to the left. The goal was Direct Digital Synthesis (DDS). The chip delivers wave- a PCI card for a personal computer working as PC-based forms with 24-bit resolution and precision. It features 2-channel function generator. In contrast to the other pro- many different modes with serial or parallel control and ject, emphasis was put on the higher frequency range the signal interfaces, sine, triangle, rectangle and different chip is able to cover. noise waveforms on separate or mixed two channels. The PCI board has been equipped with a Lucent FPGA The goal of this semester thesis was a stand-alone func- OR3TP12 with built-in PCI interface, the DDS ASIC, and tion generator instrument with best possible audio quality. two 14-bit 100Ms/s Intersil HI5741 D/A converters. Inter- A microcontroller with keys and LCD interface has been face and glue functions have been implemented in the programmed to act as user interface and to control the se- FPGA. A Linux device driver has been developed. The rial command interface of the DDS ASIC. All available graphical user interface running on X11 allows to select all functions relevant for audio measurements are supported functionality of the DDS ASIC which is available in the by the controller. The two-channel serial signal interface chosen hardware configuration. The maximal signal fre- is fed to an oversampling filter (Burr-Brown DF1704) quency is 24 MHz. The outputs drive single-ended or dif- which drives two 24-bit digital-to-analog converters ferential 50Ω loads. (PCM1704). These 8-fold oversampled signals are recon- structed by two active third-order filters. The images show the developed instrument and the signal quality that has been achieved by the realized system.

PCI function generator, user interface, and measured twin-tone spectrum (12 MHz sampling frequency, DDS audio function generator and spectrum of a 10 kHz 350 kHz and 450 kHz signals with (full-scale - 6dB) am- sine wave measured by an Audio Precision System One. plitude.

100 Audio Transmission over Compact Model Parameter FireWireTM Extraction for Semiconductor Laser Simulation

Personnel: Claudio Ghislini, Marcel Grob; Personnel: Pamela Lässer; Eric Roth, Matthias Streiff, Thomas Boesch (assistants) Andreas Witzig (assistants) Funding: ETHZ Funding: ETHZ

Partners: BridgeCo

In this semester thesis a system for audio transmission Physics-based simulations of semiconductor lasers in two over FireWireTM has been developed. The goal was to im- and three dimensions produce highly accurate spatially plement a complete system that includes A/D and D/A resolved results. However, these simulations are rather conversion of audio signals on the transmitter and on the time consuming. In system simulations of entire fibre-optic receiver. The final system can input a stereo signal from transmission links, it is necessary to drastically reduce the an analog source and send the converted audio data to amount of CPU time needed to simulate the behavior of a two receiving nodes that can output the analog signal. single component, as in this case, for a laser diode. In order to achieve this, a simple concentrated (zero dimen- As a starting point an existing evaluation platform with sional) rate equation model with unknown fit parameters TM FireWire chip set, microcontroller, and FPGA was is employed. used. A daughter-board with a PLL and audio CoDecs was designed in the project. Most of the effort was made This project aimed at obtaining the parameters for this on the dataflow management in the FPGA and the control rate equation model from the results of a physics-based software on the microcontroller. simulation. The parameters were extracted such that the optical output power relates to the laser current equally in In order to synchronize the audio sampling rates between the physics-based model and in the rate equations. A lo- the receiving and the sending node a PLL was implement- cal sensitivity analysis of the parameters in the rate-equa- ed. The analog parts of the PLL (VCXO, low-pass filter) tion model was performed. The parameters were are located on the audio board while the digital parts extracted using a least-square fitting procedure based on (phase detector, dividers) are implemented in the FPGA. the interior reflected Newton method.

Parameters are extracted by minimizing the difference Picture of the evaluation board with audio daughter between terminal quantities of the physics-based model board and system diagram. and the rate equation model.

101 Spontaneous Emission in Calculation of Electronic Surface-Emitting Lasers Band Structures for Laser Simulations

Personnel: Thomas Eberle; Personnel: Kersten Schmidt; Andreas Witzig, Michael Pfeiffer, Matthias Streiff (assistants) Andreas Witzig (assistants) Funding: ETHZ Funding: ETHZ

Spontaneous emission is a remarkable manifestation of TCAD tools are becoming increasingly important instru- the interaction between an atom and the electromagnetic ments in the design and optimization of optoelectronic de- fields. Spontaneous emission is sometimes erroneously vices like e.g. diode lasers and photodetectors. While regarded as being an inherent feature in the behavior of device geometries in optoelectronics are usually more atoms. However, it has been demonstrated theoretically simple than in classical silicon TCAD, the wide variety of and experimentally that the radiative properties of an different optoelectronic materials and the complex phys- atom can be altered by modifying the cavity around it. ics of the light-matter interaction make the task of optoelectronics device simulation a real challenge. The rate of spontaneous emission depends on the density This diploma thesis was concerned with one of the key of electromagnetic modes. Spontaneous emission is in- factors of optoelectronic device simulation: the knowledge hibited if the cavity is off resonance and/or if the atom is of electronic band structures. While in silicon TCAD it is located at a node of a mode function, and is enhanced if usually sufficient to assume a parabolic energy dispersion the cavity is resonant and/or the atom is located at an anti- E(k) between the energy E and the wave vector k of a node of a mode function charge carrier, optoelectronic materials exhibit strong The capability of modifying spontaneous emission by an non-parabolicities for the relevant values of k. This is the optical cavity holds technological promise for realizing an case in particular for materials in wurtzite crystal configu- efficient laser. The spontaneous emission can not be ne- ration, namely the GaN material group. The calculation of glected in the rigorous simulation of vertical cavity surface band structures can be carried out by costly ab-initio emitting lasers (VCSEL). The inhibition and the enhance- methods like the Empirical Pseudopotential method or by ment of the spontaneous emission has been investigated more approximative methods like thekp⋅ method. This using the finite-difference time-domain (FDTD) method. method is based on a perturbative approach, making it The simulation has been validated by comparison with the computationally more efficient. analytic solution that is available for very simple struc- In this thesis, a library of Matlab routines has been imple- tures. mented for performing band structure calculations using a 4-bandkp⋅ approach. For given material parameters the band structure E(k), the effective carrier masses, and the densities of state for electrons and holes (all as functions of E) are returned. The implementation is modular and allows for future extensions to cover higher-orderkp⋅ or other calculation methods. The library will also be converted to C++ and coupled to the device simulator DESSIS.

Normalized spontaneous emission rate versus frequen- Valence band structure near the center of the Brillouin cy for a atomic dipole in a planar mirror microcavity. The zone in AlGaAs (large picture) and resulting density of dipole is indicated by the arrows, and sits exactly halfway hole states (small picture). The black curves are calculat- between the mirrors. The perpendicular case is shown in ed assuming parabolic bands. The red curves result from (a), and the parallel case is shown in (b). a 4-bandkp⋅ calculation.

102 Simulation of Twin-Guide Device Simulator Calibration for Tunable Lasers Substrate Effect Investigations in Smart-Power ICs

Personnel: Adrian Bregy; Personnel: Thomas Frei; Andreas Witzig, Michael Schenkel (assistant) Michael Pfeiffer (assistants) Funding: ETHZ Funding: ETHZ

Partners: Nortel Networks Partners: Bosch, ISE AG

Tunable lasers are promising devices for communication Cause and effects of parasitic substrate currents in smart- applications. For wavelength-division multiplexing (WDM) power motor control ICs as well as protection measures different channels can be addressed by the same device, are investigated in the European SUBSAFE project. Goal and the wavelength can be selected by external circuitry. is a TCAD-based (Technology Computer-Aided Design) substrate current control design methodology. But, before In this undergraduate thesis, a twin-guide tunable laser meaningful device simulations can be performed, device has been investigated. The device structure consists of an and technology parameters have to be calibrated. active region, where the photons are generated by injec- Minority carrier lifetime τ in the substrate directly influ- tion luminescence. Furthermore, there is a tuning region n ences the substrate current. On the other hand, τ is not in which the refractive index can be changed by the injec- n well known and needs calibration. Because standard life- tion of charge carriers. The current confinement is time test structures do not measure τ in the substrate, a achieved by a n-doped barrier region in the p-substrate. n new approach had to be chosen. IV-measurements of the parasitic NPN transistor have been compared to 3D de- The thickness of the barrier region is a typical parameter vice simulations with different minority carrier lifetimes un- that has to be optimized in the device design. til best agreement has been found, whereas good agreement at VBE = 1 V is important. Other important parameters which need to be calibrated are substrate dop- Φ ing NA and backside contact Schottky barrier height Bp.

Device simulation of a twin-guide tunable laser. Top: device structure. Bottom left: simulation result at operating 3D device simulation structure of parasitic NPN transistor condition. Bottom right: simulation result at high current used for minority carrier lifetime calibration (top) and injection, where a breakdown can be observed and the comparison of measured and simulated Gummel plot af- barrier region fails to confine the current. ter lifetime calibration (bottom).

103 PhD Theses – Abstracts

On Boundary Conforming Anisotropic Delaunay Meshes Jens Krause Automatic mesh generation has become an integral part This work presents a novel method, normal offsetting, to in solving partial differential equations numerically by the generate the discretization points in such a way that the Finite Element Method or the Box Method as a variant of induced Delaunay triangulation is anisotropic. The the Finite Element Method. Many engineering disciplines method uses a modified Advancing Front approach; in employ these methods to analyze new design concepts. 2D layers of stretched quadrilaterals are added to the The framework of this work is the design of new semi- boundary and in 3D layers of flat prismatic elements are conductor technologies. Generally, this is done in two inserted into a surface mesh. Subsequently, a final steps: the modelling of the fabrication (process simula- triangular mesh is constructed. tion) and of the electrical behaviour of the device (device This work focuses on a practical implementation of simulation). these ideas. In this respect, robustness of the genera- The discretization method of choice for the partial differ- tor to handle arbitrary geometries is very important. ential equations in this field is the Box Method, which Especially in 3D, this stability is hard to achieve and a calls for Delaunay meshes as a minimum requirement. constitutes major road block for a successful process On the other side, the boundary layer behavior of the simulation, which needs multiple re-meshing steps. solution has to be modeled. A fine mesh with isotropic With the continuing miniaturization of modern semi- elements at material interfaces would contain too many conductor devices 3D effects become more and more points to be useful in practical applications. In order to pronounced in the device characteristics. Also, the save points, anisotropic elements are desired at these simulation of 3D effects becomes more important. This interfaces. In addition, the solution characteristics favors work, however, deals with 2D and 3D design and mesh lines interface parallel. implementation of these new ideas.

Prof. Dr. W. Fichtner, ETH Zürich, examiner Diss ETH-Nr. 14219 Prof. Dr. S. Selberherr, TU Wien, co-examiner ISBN 3-89649-696-4

Scanning Capacitance Microscope Imaging and Modeling Lorenzo Ciampolini Actual electron devices are fabricated on the scale of sulting 2D SCM image is thus dependent on the cross- hundreds or even tens of nanometers (nm). At this sectional, 2D dopant distribution of the sample. scale, the device electrical behavior and its reliability The thesis describes accurately the experimental SCM are strongly dependent on the shape of the two- technique and proposes an highly efficient technique for dimensional (2D) distribution of impurity atoms its modeling, which is based on device simulation with (dopants) across the semiconductor. However, it is not the commercial software DESSIS-ISE. Device simula- possible to experimentally observe the different levels of tions are performed systematically on a wide set of concentration of dopants across the various regions of tip/sample geometries and the calculated Capacitance- a device. Furthermore, it is difficult to predict the 2D Voltage (C-V) characteristics are gathered in a data- dopant distribution with the aid of process simulators, base. The SCaMsim software has been developed in due to the complexity of the different physical effects order to manage the simulations and the C-V database. that may take place during the device fabrication. The software has been used to theoretically investigate The Scanning Capacitance Microscope (SCM) is a the SCM technique and to obtain 2D SCM images, re- promising candidate for the quantitative analysis of 2D constructed from the database results. dopant distributions. With SCM, which is a technique Simulation results have been compared with one- based on an Atomic Force Microscope (AFM), it is pos- dimensional SCM measurements performed at the Insti- sible to acquire 2D images with deep sub-micron reso- tute of Integrated System and at the IMETEM laboratory lution along a device cross section. The SCM signal is in Catania. Finally, the simulation results have been related to the local free carrier concentration in the de- successfully compared with capacitance spectroscopy vice region immediately beneath the AFM tip. The re- measurements performed at the Solid State Electronics Institute of the Technische Universität, in Wien.

Prof. Dr. W. Fichtner, ETH Zürich, examiner Diss ETH-Nr. 14304 Prof. Dr. E. Gornik, TU Wien, co-examiner ISBN 3-89649-788-X

104 Globally-Asynchronous Locally-Synchronous Architectures for VLSI Systems Jens Muttersbach This thesis describes the specification and implementa- Data channels between LS modules, which are estab- tion of a design methodology for globally asynchronous lished with the mentioned basic elements, are able to locally-synchronous (GALS) architectures. Such archi- safely transfer over 300·106 data words of arbitrary tectures are a novel approach to the design of complex width per second (All measured numbers refer to a VLSI systems which are suffering from clocking prob- 0.25µm CMOS technology). The channels have a la- lems and high power consumption. tency of far less than one clock period and transmis- In a GALS architecture the system gets partitioned into sions in subsequent local clock cycles are possible. several independently clocked modules which are These two features and the prevention of metastability communicating in a self-timed manner. Thus the func- distinguish the proposed method from all previous con- tionality of each locally-synchronous (LS) module can cepts. be described and synthesized along well established By realizing a crypto system in GALS architecture the synchronous design flows and clocking problems are methodology is validated on silicon. The ASIC encrypts eased by confining them to a moderately sized subsys- and decrypts data with the Safer SK-128 algorithm in all tem. The circuitry necessary to coordinate clock-driven standardized block cipher modes. The system contains with self-timed operation is contained in an asynchro- 58.000 gate equivalents and scan-testability of syn- nous wrapper that surrounds each LS module. chronous circuitry is fully sustained. This work is the first These wrappers have a modular internal structure that to demonstrate GALS operation for a system of sub- can be assembled from a library of six basic elements: stantial complexity. four different port controllers for input and output ports A second ASIC implements the same crypto system in respectively, a memory access controller, and a clock a conventional globally-synchronous architecture and generation unit. To prevent metastability while transfer- serves as a reference for comparisons. Both chips have ring data across clock boundaries, the concept employs been manufactured on the same wafer. The measured a pausible clocking scheme, i.e. whenever data maximum data throughput of the synchronous design is changes and sampling clock edge occur dangerously about 30% higher than that of the GALS counterpart. close to another, either the clock or the data get de- On the other hand the synchronous chip, which already layed. The pausible clock is provided by an on-chip employs clock gating to save power, dissipates 30% clock generator, which does properly arbitrate between more energy per Mbit of data than the GALS implemen- numerous concurrent requests for pausing and active tation. clock edges. The frequency of the clock is programmable for a large range of values. Prof. Dr. W. Fichtner, ETH Zürich, examiner Diss ETH-Nr. 14155 Prof. Dr. G. Tröster, ETH Zürich, co-examiner ISBN 3-89649-724-3

Data Statistics and Low-Power Digital VLSI Jürgen Wassner Ongoing advances of semiconductor technology enable technique for the efficient control of the estimation accu- the integration of more and more complex circuits, thus racy is proposed. making feasible devices of ever increasing functionality for ever new applications. Naturally, power dissipation 2. The question of fundamental lower bounds on power has evolved into a key constraint for the design of VLSI dissipation in consideration of data statistics is pursued. circuits, particularly for battery-powered applications. A systematic view of minimum power dissipation is developed, which leads to a classification of the lower This thesis deals specifically with power dissipation of bound problem. The resulting sub-problems are set in digital VLSI circuits subject to the statistical properties context to known information-theoretic bounds on data of the data being processed. The dependence of power coding and transmission. consumption on data statistics is explored with regard to three major aspects: power estimation, power minimiza- 3. By means of speech filtering it is exemplified how tion, and practical low-power design. designers of application-specific circuits may avail themselves of data statistics to cut down the energy 1. In the context of gate-level power estimation, a prob- use. Various number representations and data encod- abilistic approach to determine the switching activity in ings are examined, and potential power savings are logic circuits from the given input statistics is presented. quantified subject to statistical signal properties and This approach can take into account any kind of signal operating conditions. This permits the derivation of gen- correlation and calculates the correct switching activity eral coding guide-lines for application-specific process- for every node in the circuit. A novel approximation ing of speech data. Prof. Dr. W. Fichtner, ETH Zürich, examiner Diss ETH-Nr. 14395 Prof. Dr. L. Thiele, ETH Zürich, co-examiner ISBN 3-89649-741-3

105 On-Chip ESD Protection in Integrated Circuits: Device Physics, Modeling, Circuit Simula- tion Markus Mergens This thesis investigates Electro Static Discharge (ESD) applying these models on ESD-level circuit simulation, phenomena in microelectronics Integrated Circuits (ICs) the complex high current behavior of various ESD pro- including simulation of integrated ESD (on-chip) protec- tection configurations including relevant core partitions tion structures. A special emphasis is put on the ESD could be analyzed regarding ESD discharge paths and relevant high current physics of bipolar and MOS tran- critical node voltages. From the simulation results, ESD sistors in Smart-Power as well as CMOS technologies design rules and improved protection schemes for dif- employing 2-D device simulation. Analytical compact ferent Input, Output, and supply protection configura- models for the reproduction of (parasitic) bipolar snap- tions could be derived and verified. back behavior were developed in conjunction with the corresponding parameter extraction procedures. By Prof. Dr. W. Fichtner, ETH Zürich, examiner Diss ETH-Nr. 14185 Prof. Dr. H. Jäckel, ETH Zürich, co-examiner ISBN 3-89649-701-4

Stress-Related Problems in Process Simulation Stefan Zelenka This thesis deals with mechanical stress which can de- entation-dependent oxidation and the related »out- velop during the manufacturing process of semiconduc- growth« of crystal planes, known as faceting, can be tor devices in highly integrated circuits. The commercial included. Besides thermal oxidation, as a related proc- simulation software DIOS-ISE was extended by a consti- ess, silicidation can be simulated. As already mentioned tutive equation which allows the treatment from purely the constitutive equation is capable of accounting for viscous via viscoelastic to purely elastic materials. Addi- purely elastic materials. Since most of the materials tionally, the temperature-dependent viscosity can de- used in semiconductor technology show elastic behav- pend on the local shear stress in the material. This ior at moderate temperatures the complete manufactur- leads to a non-linear constitutive equation. To obtain ing process of a device can be simulated additionally accurate results for the thermal oxidation of silicon the with respect to mechanical properties. Thereby the final diffusivity and reaction rate of the oxidants can depend result of a simulation contains the complete history of on the local stress in the material and at the oxidation mechanical stress. The underlying mechanics equa- front. Mechanical stress can be calculated within the tions and the corresponding implementation will be dis- whole device, i.e. also in the substrate. Deposited mate- cussed in detail. In addition the functionality of the simu- rials such as Si3N4 show initial stress directly after lator will be demonstrated and validated by numerous deposition. During simulation this phenomenon can also examples taken out of literature. be taken into account. Additionally, effects such as ori-

Prof. Dr. W. Fichtner, ETH Zürich, examiner Diss ETH-Nr. 14220 Prof. Dr. S. Selberherr, TU Wien, co-examiner ISBN 3-89649-704-9

Device Simulation of ESD Protection Elements Kai Esmark “First time right” is the guiding principle for every semi- tools have been used a long time in the ordinary proc- conductor company with respect to the introduction of a ess development, simulators have had a minimal role in new process technology. Beside the development of the ESD engineering. The reason is the operational regime single process steps, a whole new and complex infra- of an ESD protection element is far outside the range structure has to be set up, which reaches from the de- the physical models have been tested and verified. velopment of single cells of a specific I/O library to the These models serve as the basis for such kinds of cal- realization of a complete product, an integrated circuit. culations. A further question is, if the conventional 2-D simulation approach of today’s TCAD tools is able to The problem regarding electrostatic discharge (ESD) is describe ESD protection elements under ESD condi- present at every stage of the development level, as tions or in how far 3-D effects need to be considered considerations concerning the protection against elec- too. To sum up: to use TCAD software for typical prob- trostatic discharge are encountered in the definition of a lems in the field of ESD it needs a verification, if the new process as well as in the product. simulation approach is correct and if the physical mod- Strategies and solutions for ESD protection concepts els are valid under ESD like conditions. and suggestions for the optimization of the process Before this thesis, there was a great lack of information concerning its intrinsic ESD characteristics have to be concerning internal device processes under high cur- found by the engineer in a very early stage of the proc- rent injection and high temperature conditions that are ess development. To achieve very short time to market characteristics of ESD events. Recently available new and reduce the development effort, one tries to make experimental techniques, like IV-tracing at elevated use of the benefit of simulation tools. Whereas TCAD

106 temperatures and thermal mapping of ESD protection sents a milestone in the field of ESD, since this comes structures under ESD stress conditions, make an at- very close to the target of “first time right”. tempt to compare measured and calculated results under ESD conditions. Based on the experimental results, The rules for the prediction of failure thresholds derived in this thesis are based upon the evaluation of tempera- the single physical models were calibrated and partly nd improved, so they fit quite well in the high temperature ture profiles and the detection of 2 breakdown; here regime and provide reasonable results. again, an excellent agreement to experimental results were achieved. The failure criteria are applicable inde- The ggNMOS2 transistor is a widespread ESD protec- pendent of the stress type, whether the device is tested tion element and serves in this thesis as the test case to according to the Human Body model (HBM) or with discuss the necessary steps to gain reliable and usable Transmission Line (TL) pulses. In addition the very information from a commercial device simulator under good reproduction of measured temperature distribu- high current operation. The goal is to make device tions allows optimization of the process technology and simulation a predictive tool for ESD designers. This is the particular protection element with respect to thermal achieved through a greater understanding of device stress under ESD stress conditions. specific behavior under ESD stress conditions, for example 2nd breakdown. Unfortunately, devices pushed into snap back like the ggNMOS transistor do not always necessarily operate From the viewpoint of an ESD engineer and designing homogeneously along the device width, even though an appropriate ESD protection concept, two issues are the current regime that the device operates non- of particular interest. They are the determination of elec- uniformly can be restricted to a very small current re- trical parameters in the high current regime and the gion. In some cases, the device behavior is affected by prediction of failure thresholds. As shown in this thesis, 3-D device effects in the whole operating regime, many questions can be answered by means of a well including the device failure under ESD condition. It is calibrated 2-D device simulator, but some of them can- obvious in this case that these issues cannot be han- not. dled in a 2-D device simulator. The use of 3-D device simulation is very valuable to gain background informa- Under the condition that the protection device is trig- tion about layout and technology issues that accelerate gered homogeneously meaning it is operating uniformly the process of current filamentation and limit the ESD along the device width, the calculated current density robustness of the device. and temperature distribution are in very good agreement to the measured values. The correspondence is 1 Technology Computer Aided Design so good, that area optimized pre-Si ESD protection 2 grounded gate NMOS concepts can be derived very early. This itself repre- Prof. Dr. W. Fichtner, ETH Zürich, examiner Diss ETH-Nr. 14466 Prof. Dr. Melchior, ETH Zürich, co-examiner ISBN 3-89649-781-2

Grid Adaptation for the Stationary Two-Dimensional Drift-Diffusion Model in Semicon- ductor Device Simulation Bernhard Schmithüsen In this work a novel anisotropic grid adaptation proce- method discretization. The iterative re-computation of dure for the stationary 2D drift-diffusion model of semi- solutions on new simulation grids utilizes local and conductor device simulation is developed. The adapta- global characterizations of dominating nonlinearities, tion approach is based on the principle of 'equidistribut- employing solves of local Dirichlet Problems and global ing local dissipation rate errors' and aims at accurate homotopy techniques for strong avalanche generation. computations of device terminal currents. The appropri- The approach is analyzed for simple model device ate adaptation criteria, derived in analogy to standard a structures and demonstrated along realistic simulation posteriori error estimation methods, are based on solu- cases. tions of local Dirichlet problems on locally refined meshes, measure jumps of the dissipation rate density Keywords: grid adaptation, semiconductor device simu- across element edges, and include natural anisotropic lation, a posteriori error estimation, drift-diffusion model, refinement information. A quad-tree mesh structure is Scharfetter-Gummel box method, boundary Delaunay utilized to enable anisotropic local grid adaptations on mesh, quad-tree mesh, dissipation rate, anisotropic boundary Delaunay meshes, required by the stability refinement, avalanche homotopy. properties of the underlying Scharfetter-Gummel box Prof. Dr. W. Fichtner, ETH Zürich, examiner Diss ETH-Nr. 14449 Prof. Dr. G. Baccarani, Uni Bologna, co-examiner ISBN 3-89649-773-1

PhD theses can be ordered from:

Hartung-Gorre Verlag Phone: +49 7533 97227 Säntisblick 26 Fax: +49 7533 97228 D-78465 Konstanz E-mail: [email protected] Germany Web: http://home.t-online.de/home/hartung.gorre

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Diploma Theses – Overview

Summer Semester 2001

Yue Li Low-Voltage, Low-Power DDA-based Frontend with Improved Dynamic Range Yingyun Zha Design und Implementation of a Fast 10-bit Sample-and-Hold Circuit Kersten Schmidt Quantum Wells in the Simulation of Semiconductor Lasers

Winter Semester 2001/2002

Giuseppe Acunto Adaptive Arithmetic Coding and its Efficient Implementation Miguel Sans Simone Buzzi 3D-DCT Video Compression System on a PCI Board Simon Häne Giuseppe Schiavello Beni Ingold SAFER SK128 Encryption/Decryption for Digital Audio Links Jonas Bandi Digital Communications System for "BodyCom" Marc Wegmüller Silvio Dragone OIF-SPI-5 Receiver Peter Oertig Evaluation and Design of Fast Comparators for Analog-to-Digital Converters David Satz LED-Lamp with Electronically Controllable Color Characteristics Elmar Schmid Low-Power GPS RF Front End in 0.18µm CMOS Thomas Weber Marco Chiavarini Thermal Simulation of Power Semiconductor Devices

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Student Theses – Overview

Summer Semester 2001

Giuseppe Acunto Arithmetic Coding and its Efficient Implementation Miguel Sans Adrian Bregy Simulation of a Tunable Laser Claudio Ghislini Digital Audio Transmission over FireWire Marcel Grob Michael Lerjen Compact Microcontroller Core as Virtual Component David Satz Battery Charge Controller for Diving Lamps Marc Secall-Wimmel Precise Digital Altimeter Axel Burri Real-Time Error-Resilient 3D-DCT Video Compression System

Winter Semester 2001/2002

Thomas Dellsperger MIMO UMTS Baseband Integrated Circuit Michael Geissmann Gérard Basler SERPENT Encryption ASIC Jürg Treichler Pieter Rommens Andres Erni RIJNDAEL Encryption ASIC Adrian Lutz Stefan Reichmuth Marc Robert FFT based Audio Equalizer Roman Leuzinger PIC Microcontroller Virtual Component Urs Frey Simon Müller LIN Automotive Network Interface Chip for Smart Sensor Marcel Plüss Andreas Dick Adrian Trüllinger Real-Time Image Filter Processor ASIC Silvan Wegmann JAVA Virtual Machine Co-Processor Andreas Ochsner GSM Speech Synthesizer Sidcley Nascimento da Silva Felix Bürgin Source Coder for Bio-Medical Data Tranfer Franziska Pfisterer Thomas Christen 200 MHz Frequenzy Synthesizer Stefan Odermatt Devid Destefanis FPGA Board for ∑∆ D/A Converter Patrick Torta Iwan Schenker Pseudo-Random Number Generation Eyjolfur Snjolfsson ∑∆ Audio Digital-to-Analog Converter Martin Polasek FireWire Audio System Carlos Velasquez Santi

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Microelectronics Design Center (DZ)

Personnel

Dr. H. Kaeslin (head, VLSI CAE), C. Balmer (VLSI technology), M. Brändli (software operation, VLSI CAE/CAD), R. Haldemann (external consultant, VLSI CAD), R. Köppel (PCB CAD),

Security improvements

IT security was subject to thorough rethinking and improvement to better protect the industrial software products installed in view of the many users affiliated with ETH in one way or another. Export of EDA software and of design kits is strictly confined to trusted hosts located at ETH Zurich itself. License check- out is restricted in a similar way. In addition, all log files are being archived and get inspected on a regular basis. UNIX groups and HTTP user authentication are being put to service to limit access to specific design kits and other company-confidential data to authorized project teams and individuals. Subscription to mailing lists and access to newsgroup archives is restricted to persons from within ETH. Last but not least, a summary on the regulations that apply to university licenses is made available in both English and German at the website http://dz.ee.ethz.ch/misc/regulations/index.en.html.

Cockpit

Any of today's digital design flows makes use of a multitude of EDA tools from different vendors. This typically includes Emacs for the entry of HDL source code, ModelSim by Mentor Graphics for simulation, Design Analyzer by Synopsys for synthesis, Silicon Ensemble by Cadence for physical design, and either of Calibre by Mentor Graphics or Assura by Cadence for physical verification. Making such a heterogene- ous collection of tools cooperate requires an elaborate data organization which DZ has learned to optimize over the years. In order to enforce a consistent directory structure and to facilitate the process of setting up of the EDA environment for a given target technology, we have developed a Perl script that handles all this mostly automatically. This cockpit tool has been made available to students for their exercises and design projects in the winter term 2001/02.

Fabrication processes

The table below lists all CMOS processes currently supported for digital and/or analog design, that is fabrication processes for which a design kit for either design flow, a standard cell library, and MPW services are available.

Vendor Process Drawn Metal Digital Supported min. channel interconnect length [µm] layers libraries devices AMS CMOS 0.35 3 yes 1) CMOS 0.6 3 yes 1) BiCMOS 0.8 2 yes 1), 2) STM CMOS 0.18 6 yes 1) CMOS 0.25 6 no 1) TSMC CMOS 0.18 6 yes 1), 3) UMC CMOS 0.18 6 yes 1), 3)

1) capacitor, resistor 2) bipolar transistor 3) MIM, spiral inductor, varactor DZ has redesigned its on-line directory of the supported fabrication processes. The new website lists key technology characteristics, gives important data on the available foundry kits and cell libraries, and sketches the design flow by naming the necessary CAE/CAD tools. Please refer to http://dz.ee.ethz.ch/support/IC/technologies/index.en.html

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Design activities

A statistical overview of all IC and PCB design activities conducted in 2001 with the EDA installations operated by DZ is given in the tables below along with the laboratory involved and other technical information.

IC design Teaching Research Total Process family Foundry IIS ISI IfH IfE IQE 0.35 µm CMOS AMS - - - - 1 - 1 0.6 µm CMOS AMS 2 1 - - 2 2 7 0.8 µm CMOS AMS - 1 - - - 4 5 0.15 µm PHEMT IAF - - - 1 - - 1 InP-HBT IfE - - - 3 - - 3 0.13 µm CMOS Infineon - 4 - - - - 4 0.25 µm CMOS Infineon - 4 - - - - 4 1.0 µm CMOS Philips - - 2 - 2 - 4 0.18 µm CMOS STM - 2 - - - - 2 0.25 µm CMOS STM - 3 - - - - 3 0.6 µm GaAs MESFET Triquint - - - 1 - - 1 0.18 µm CMOS TSMC - 1 - 1 - - 2 0.8 µm CMOS X-FAB - - - - - 1 1

Total 2 16 2 6 5 7 38

Board design IIS IfE ISI IQE TIK Total with individual support 9 1 2 2 1 15 freelance projects 13 1 4 24 - 42 Total 22 2 6 26 1 57

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Joint Research Cooperation with Foundation for Research on Information Technologies in Society IT'IS

Profile try research partners in Europe, the USA and The Foundation for Research on Information Asia. Technologies in Society (IT'IS) was founded Current Research Focus and Projects on November 15th, 1999 through the initiative IT'IS is currently involved in over twenty na- and support of the Swiss Federal Institute of tional, European and international research Technology in Zurich (ETHZ), the global wire- projects addressing the question of risk less communications industry, and several evaluation in wireless communications, as governmental agencies. The aim was to cre- well as five projects related to sensing and ate a flexible and dynamic research institution computational techniques for electromagnetic capable of addressing the research needs of analysis. In addition to providing research re- society in the explosively expanding field of sults for governmental agencies through par- information technologies. Some of the areas ticipation in standardization bodies and pro- encompassed are: viding consultation to governments, IT'IS also • evaluation of the safety and risks related to provides courses to members of the public, current and emerging information tech- industry, and universities. nologies Current research projects are being sup- • exploration of information technologies for ported by public funds such as those of the medical, diagnostic and life support sys- Quality of Life Programme of the European tems Union, health agencies and other governmen- • improvement of the accessibility of infor- tal institutions. Funding from industry comes mation technologies for all members of so- from major mobile communications manufac- ciety including disabled persons. turers and service providers as well as from IT'IS is committed to the advancement of sci- smaller companies (see page 80ff). ence for the benefit of society at large and to maintaining strict independence from any particular interest groups. These principles are reflected in the foundation's charter as well as the balance of the composition of its board with distinguished personalities from science, the public sector, and the global wireless communications industry. IT'IS is a non-profit tax-exempt research organization.

Infrastructure and Cooperation The main research unit of IT'IS is located in the VAW Building at ETH Zurich. In April Foundation for Research on Information Tech- 2000, IT'IS opened jointly with Schmid & nologies in Society IT'IS Partner Engineering AG the world's most ad- Prof. Dr. Niels Kuster vanced near-field laboratory in downtown Zu- rich. Director IT'IS & Associate Member of the Electrical Engineering Department of the Swiss Federal Insti- The closest and most important cooperative tute of Technology ETH Zürich ties that IT'IS has are with ETH Zurich. An excellent relationship has been established ETH VAW Building, Gloriastrasse 37/39 with the Integrated Systems Laboratory. In ETH Zentrum, CH-8092 Zürich, Switzerland addition, the IT'IS team has great experience Phone: +41 1 245 9696, Fax: +41 1 245 9699 in multi-disciplinary cooperation through a www: http://www.itis.ethz.ch multitude of projects, resulting in an interna- IT'IS Laboratories, Zeughausstrasse 43 tional network of over 50 academic and indus- CH-8004 Zürich, Switzerland

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Workshops and Courses

A/D Converters for Telecommunication Trainer: Dr. Clemens Hammerschmied, Integrated Systems Laboratory Dates: Monday, 22 October 2001 Participants: Staff and students ETH Zürich

Physical Design Verification with Calibre Trainer: M. Kneip, Mentor Graphics Dates: 3 days from December 11 to 13, 2001 Participants: 6

Schematic Entry and Physical Layout for PCBs Trainer: R. Köppel, Microelectronics Design Center Dates: 4 days from April 12 to May 31, 2001 Participants: 4

Schematic Entry and Physical Layout for PCBs Trainer: R. Köppel, Microelectronics Design Center Dates: 4 days from April 23 to May 21, 2001 Participants: 5

Schematic Entry and Physical Layout for PCBs Trainer: R. Köppel, Microelectronics Design Center Dates: 4 days from November 1 to 29, 2001 Participants: 11

Schematic Entry and Physical Layout for PCBs Trainer: R. Köppel, Microelectronics Design Center Dates: 3 days from December 3 to 10, 2001 Participants: 9

Workshop Simulation of Semiconductor Laser Devices Organized by Optoelectronics Modeling Group, Integrated Systems Laboratory Dates: 2 days from October 22 to 23, 2001 Presentations: 3 invited talks, 65 talks, 1 tutorial, demonstrations of laser simulations, computer lab with hands-on-experience Participants: 25 from optoelectronics industry and academia Publication: Workshop proceedings including contributions of all presentations and computer demonstrations.

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Lectures

Halbleiterbauelemente 4th Semester Semiconductor Devices EE

This lecture gives an introduction to the basics of modern semiconductor devices for micro-, opto-, and power-electronics. It bases on semiconductor physics and covers band structures, band models, dispersion relations, statistics, transport equations, macroscopic models, and the characteristics of Silicon and other semiconductors. An overview on device families is presented. The part on technologies covers the properties of materials, and introduces the steps of modern process technologies as well as packaging. To understand the basic principles of devices ohmic and rectifying contacts, physical and electrical characteristics of pn junctions, and types of diodes are explained. The lecture continues with the bipolar transistor's function, working regions, characteristic diagrams, and its simulation. MOS devices are treated based on band diagrams. and the MOSFET behaviour is deduced. Power devices, their working regions and static and dynamic behaviour are followed by examples of optoelectronic devices as photo conductor, photodiode, LED, and fiber. Semiconductor measurement and characterization methods conclude the course.

Kommunikationselektronik 5th Semester Communications Electronics EE

This course provides basic design and circuit techniques for communications electronics. As a starting point, bipolar and MOS transistors are reviewed. The discussion of circuit design begins with basic amplifier topologies, impedance matching concepts and a bit of two-port theory. Important non-ideal aspects such as non-linearity and noise are discussed. This sets the ground for more involved topics. Important building blocks of communications equipment, such as mixers and oscillators, are examined in detail. The discussions include the basic topologies, mathematical descriptions and a thorough analysis of non-ideal behavior, from which finally guidelines for the design can be derived. The exercises form an integral part of this course. The definitions and concepts presented in the lecture will be reinforced by small design examples, therefore providing a link between the theoretical description and real-world problems.

VLSI I: Architektur von hochintegrierten Schaltungen 6th Semester VLSI I: Architectures of Highly Integrated Circuits EE/CS/Phys/CSE

As becomes clear from the subsequent list of topics, the first course in this series of three is mainly concerned with system-level issues of VLSI. Terminology, overview on design methodologies and fabrication avenues, levels of abstraction used for circuit description and simulation, VLSI design flow, dedicated VLSI architectures, how to obtain an architecture for a given processing algorithm, architectural transformations for meeting throughput, area, and power requirements. Hardware Description Languages (HDL) and their underlying concepts, VHDL for simulation and synthesis, the IEEE-1164 logic system, Register Transfer Level (RTL) synthesis. Timing models, Anceau diagrams, functional verification of digital circuits and systems, building blocks of digital VLSI circuits, case studies of actual circuits, comparison with microprocessors and DSPs. During the exercises students learn how to model digital ICs with VHDL. They write testbenches for simulation purposes and synthesize gate-level netlists for ASICs and FPGAs.

VLSI II: Entwurf von hochintegrierten Schaltungen 7th Semester VLSI II: Design of Highly Integrated Circuits EE/CS/Phys/CSE

The second course begins with a thorough discussion of various technical aspects at the circuit and layout level. It then moves on to economic issues of VLSI. Topics include: limitations of functional design verification, techniques for improving controllability and observability, design for test, block isolation,

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scan-path techniques, partial scan and its caveats. Evaluation of various synchronous clocking disciplines, skew margins, clock distribution techniques. Asynchronous inputs, data inconsistency and metastability problems, synchronization. Cell libraries, Process-Temperature-Voltage (PTV) variations, transistor models, characteristics of CMOS inverters, complex gates. Power estimation and low-power design. Layout parasitics, transport delay, switching currents, ground bounce, controlling noise problems, power distribution, floorplanning, chip assembly. Layout design at the mask level, symbolic layout. Timing verification, physical design verification. Cost structures of microelectronics design and fabrication, avenues to low-volume fabrication, management of VLSI projects. Exercises are concerned with physical design and sound engineering practices for avoiding timing, testability, and layout parasitics problems. Industrial CAD tools are being used for place and route, clock tree generation, chip assembly, and physical design verification. Students that elect to carry through a term project at the laboratory are offered the opportunity to complete a full IC design cycle on a circuit of their own which gets actually fabricated.

VLSI III: Fabrikation und Verifikation von hochintegrierten Schaltungen 8th Sem. VLSI III: Fabrication and Verification of Highly Integrated Circuits EE/CS/Phys/CSE

Whereas the preceding courses deal with design aspects of VLSI circuits, this one addresses manufacturing, testing, physical analysis, and packaging issues, such as: Effects of fabrication defects, abstraction from physical to transistor- and gate-level fault models, fault grading of large ASICs. Generation of efficient test vector sets, enhancement of testability by built-in self-test techniques. Modern IC testers: Architectures and application. Deep-submicron CMOS fabrication processes with multi metal levels and the physical analysis of their devices. Packaging problems and solutions. Technology outlook. Exercises teach students how to use CAE/CAD software and automatic test equipment for verifying ASICs after fabrication. Students that submitted a design for manufacturing at the end of the 7th semester do so on their own circuits. Physical analysis methods with professional equipment (AFM, DLTS) complement this training.

Analoge integrierte Schaltungen 6th Semester Analog Integrated Circuits EE

This course provides a foundation in analog integrated circuit design: After a review of bipolar and MOS devices and their small-signal equivalent circuit models, building blocks in analog circuits such as current sources, active load, current mirrors, supply independent biasing are presented. Other topics are differential amplifiers, cascode amplifiers, high gain structures, and output stages, and comparators, gain bandwidth product and stability of op-amps. Second-order effects in analog circuits such as mismatch, noise and offset are investigated. More complex circuits as A/D and D/A converters, analog multipliers and oscillators are analyzed. An introduction to switched-capacitor circuits from an IC designer’s point of view is given. The exercise sessions aim to reinforce the lecture material by well-guided step-by-step design tasks. Cadence design tools are used to facilitate the tasks. There is also an experimental session on op-amp measurements.

Grundlagen der Optoelektronik I 7th Sem. Physics of Optoelectronic Devices I EE

This lecture gives an introduction to the physical principles of optoelectronic devices and circuits. An overview of modern semiconductor devices and circuits, and important physical effects is presented. The physical background on quantum mechanics, quantum electronics and solid-state physics leads to the physics of heterostructures. This first course on optoelectronic devices concludes with the interaction of light and matter, the generation and detection of photons, and the modulation of light in semiconductors.

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Halbleiter-Bauelemente: Physikalische Grundlagen und Simulation 7th Sem. Semiconductor Devices: Physical Principles and Simulation EE/Phys

This course aims at understanding the principles behind the physics of modern electronic silicon semiconductor devices and the foundations of physical modeling of transport and its numerical simulation. During the course basic knowledge on quantum mechanics, semiconductor physics and device physics is also provided. The main topics are: Transport models for semiconductor devices (quantum transport, Boltzmann equation, drift-diffusion model, hydrodynamic model), physical characterization of silicon (intrinsic properties, band gap narrowing, scattering processes), mobility of cold and hot carriers, recombination (SRH statistics, lifetimes for tunnel-assisted transitions), interband tunneling (Zener diode), impact ionization, metal-semiconductor contact, MIS structure, and heterojunctions. The exercises focus on the theory and the basic understanding of special devices, such as pn-diodes, bipolar transistors, MOSFETs, and thyristors. Numerical simulations of these devices with an advanced simulation package are compared with corresponding measurements, which are also part of the exercises.

Halbleitertransporttheorie und Monte-Carlo Bauelementsimulation 8th Sem. Semiconductor Transport Theory and Monte-Carlo Device Simulation EE/CSE

The aim of the course is, on the one hand, to establish the link between microscopic physics and its concrete application in device simulation and, on the other hand, to introduce the numerical techniques involved. The scope encompasses therefore the basics of quantum mechanics, transport theory and the Monte-Carlo method for the solution of the Boltzmann transport equation. The topics include second quantization, crystal symmetries, band structure calculation, phonons, Boltzmann equation, probability calculus, Monte-Carlo techniques and device simulation. The exercises comprise problems to illustrate the contents of the lecture, simple Monte-Carlo related programming tasks as well as the application of various professional tools for device simulation.

Elektrotechnik I 3rd Semester Electrical Engineering I MPE

This course provides the basic foundation in the specific field of electric engineering. Starting from the basic concepts of voltage and currents, it covers the basic analyses of dc and ac networks. This includes series and parallel circuits, resistive circuits, circuits including capacitors and inductors, as well as the Kirchhoff's laws governing such circuits, and other network theorems. Transient response of RC-circuits, analysis of resonant circuits, concept of filtering, and simple filter circuits are all among the subjects covered in this course. The understanding of the basic concepts of electric engineering, particularly of circuit theory, shall be advanced. At the end of the course, the successful student knows the basic elements of electric circuits and the basic laws and theorems for determining voltages and currents in circuits with such elements. He/she is also familiar with basic circuit calculations.

Abbreviations:

CS Computer Science CSE Computational Science and Engineering EE Electrical Engineering MPE Mechanical and Process Engineering Phys Physics1

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IC Design Projects – Overview

2001: Project: Status: SERPENT Encryption ASIC student project / RIJNDAEL Encryption ASIC student project / FFT-based Audio Equalizer student project / PIC Microcontroller Virtual Component student project / LIN Automotive Network Interface Chip for Smart Sensor student project / Real-Time Image Filter Processor ASIC student project / JAVA Virtual Machine Co-Processor Chip student project / Source Coder for Bio-Medical Data Tranfer student project / MIMO UMTS Baseband Integrated Circuit student project c Compact Microcontroller Core as Virtual Component student project c GSM Speech Synthesizer student project n Fast 10-bit Sample-and-Hold Circuit student project n Low-Voltage, Low-Power DDA-based Front End student project n Efficient Arithmetic Coder for Video Compression diploma project / Digital Communications System for BodyCom diploma project / OIF SPI-5 Receiver diploma project c Fast Comparator for Analog-Digital Converters diploma project c Low-Power GPS RF Front End in 0.18µm CMOS diploma project n 14-bit 50Msample/s D/A Converter with Background Calibration research project + 2GHz, 0.12µm CMOS Transmit I/Q Modulator for UMTS research project + 2GHz, 0.25µm CMOS Transmit I/Q Modulator for UMTS research project / Broadband Sigma-Delta D/A Converter research project / 8-bit Folding and Interpolating AD Converter research project + Baseband Circuits for a UMTS Zero-IF Mobile Receiver in 0.25µm CMOS research project ~ Baseband Circuits for a UMTS Zero-IF Mobile Receiver in 0.12µm CMOS research project / Delay-Line based Digital Controlled Oscillator research project / Test Integration for GALS Pausable Oscillators research project / Electro Cardiogram ASIC research project /

2000: Project: Status: GPS Reference-Time Generator for FireWire student project + MP3 Player Signal Processor student project + MP3 Player Data Management Processor student project n ASIC for ECG Sensor Interface student project + Virtual Component for I2C Bus diploma project n Viterbi Decoder for Applications in Telecommunications diploma project c SAFER SK128 Cipher ASIC in Globally Asynchronous Locally Synchronous Design Methodology research project + STM-1/STS-3 Programmable Virtual Component research project + Integrated Dynamic Gate Controller research project t Eddy Current Position Sensor ASIC research project +

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2-Channel Frontend IC for Eddy Current Sensors research project + 13.5 mW 185 Ms/s ∆∑ Modulator for IF Radio Signal Reception research project + SISYPHOS I: 13-bit Pipelined A/D Converter with MOSFET-Only D/A research project + SISYPHOS II: 13-bit Pipelined A/D Converter with MOSFET-Only D/A research project + SISYTEST: Building Blocks for Pipelined A/D Converter research project + MADBRIC D/A Delta-Sigma Converter research project / DAC14: 14-bit D/A converter research project + 14-bit 2.5 Ms/s Sigma-Delta Modulator with Tri-Level Quantizer research project + 8-Bit Folding and Interpolating AD Converter research project + 0.5 W 1.9 GHz Class-E Power Amplifier research project + 2 GHz Oscillator with Quadrature Output research project p

Status Marks: + successfully tested design / chip in fabrication ~ functioning, but with minor bugs • design project in progress - severe design errors t chip under test n not submitted to integration (not implemented) T design of test structures c contribution to research or industrial chip p process errors

118

Research Projects – Overview

IC and System Design and Test

Subject: Lehre und Forschung in Mikroelektronik 1999 – 2002 (Education and Research in Microelectronics) Period: April 99 - March 02 Funding: ETH Zürich, Zürich (Switzerland)

Subject: Synchrone intelligente Gate Unit zur Ansteuerung von parallel- und seriegeschalteten IGBTs (Synchronous Intelligent Gate Unit for Controlling IGBTs in Parallel and Serial Connection) Partner: CT-Concept Technology AG, Biel (Switzerland) Period: October 96 – September 01 Funding: KTI*

Subject: GALS (Globally Asynchronous Locally Synchronous) for Reuse Partner: Infineon Technologies AG, München (Germany) Period: Oktober 98 – Juni 01 Funding: Infineon Technologies AG, München (Germany)

Subject: Testable Low-Power Architectures for Multistandard Radio Systems Partner: Philips Zürich AG Semiconductors, Zürich (Switzerland) Period: August 00 - July 02 Funding: KTI* Philips Zürich AG Semiconductors, Zürich (Switzerland)

Subject: Energy-Efficient Processing of Speech Data Partner: Bernafon AG, Bern (Switzerland) Period: August 00 - July 02 Funding: KTI* Bernafon AG, Bern (Switzerland)

Subject: Netzwerkprozessor für LAN/WAN Bridging im Umfeld professioneller Multimedia Content Produktionen (Network Processor forLAN/WAN Bridging in the Environment of Professional Multimedia Content Productions) Partner: BridgeCo AG, Dübendorf (Switzerland) Computer Engineering and Networks Laboratory ETH Zürich, Zürich (Switzerland) Period: August 00 - January 02 Funding: KTI* BridgeCo AG, Dübendorf (Switzerland)

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Subject: GALS 2 Towards Practical GALS Circuits Partner: Infineon Technologies AG, München (Germany) Period: April 01 – September 03 Funding: Infineon Technologies AG, München (Germany)

Subject: An Integrated Wideband-MIMO Receiver for Wireless Multimedia Communication Partner: Lucent Technologies, Holmdel (USA) Period: March 01 – February 02 Funding: Lucent Technologies, Holmdel (USA)

Analog and Mixed-Signal Design

Subject: Mixed Analog Digital Broadband Integrated Circuits (MADBRIC) (ESPRIT IV Project) Partner: Diseno de Sistemas de Silicio SL, Castellon (Spain) Cisco Systems International B.V., Amsterdam (The Netherlands) Electricite de France, Paris (France) Period: September 98 – August 01 Funding: BBW*, European Union

Subject: Analoge Mikroelektronik in der Medizintechnik II (Analog Microelectronics in Medical Technologies, Phase II) Partner: Bernafon AG, Bern (Switzerland) Elektrobit AG, Bubikon (Switzerland) Period: April 99 – Februar 01 Funding: KTI* Bernafon AG, Bern (Switzerland)

Subject: CMOS Semicustom Array for Mixed-Signal ASIC Partner: Fachhochschule Aargau, Windisch (Switzerland) Microdul AG, Zürich (Switzerland) HMT Microelectronic AG, Biel (Switzerland) Period: April 99 – June 01 Funding: KTI

Subject Design Methodology and Implementation of a 3rd Generation W-CDMA Transceiver Using Deep Submicron CMOS Technologies (LEMON) Partner: Infineon Technologies AG, München (Germany) Institute for Communications and Information Engineering, Johannes Kepler Universität Linz, Linz (Austria) Period: January 00 – June 02 Funding: BBW*, European Union

120

Technology CAD

Subject: MAGIC FEAT – Meshes and Global Integration for Semiconductor Front-End Simulation (European IST Project) Partner: Fraunhofer-Institut für Integrierte Schaltungen, Bauelementetechnologie, Erlangen (Germany) Institut National de Recherche en Informatique et Automatique (INRIA) ST Microelectronics (ST), Gentilly, (France) Technical University of Vienna, Wien (Austria) ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: January 00 – December 02 Funding: BBW*, European Union

Subject: Hybrid-Simulatoren für sub-0.1µ-Halbleiter-Bauelemente (Hybrid Simulators for sub-0.1µ-Semiconductor Devices) Partner: ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: April 99 – March 02 Funding: KTI* ISE Integrated Systems Engineering AG, Zürich (Switzerland)

Subject: Entwicklung eines Programmes zur Simulation von Quantenwell- Lasern (Development of a Simulation Program for Quantum Well Lasers) Partner: ISE Integrated Systems Engineering AG, Zürich (Switzerland) Nortel Networks Optical Components (Switzerland) AG, Zürich (Switzerland) Period: April 99 – March 02 Funding: KTI* ISE Integrated Systems Engineering AG, Zürich (Switzerland) Nortel Networks Optical Components (Switzerland) AG, Zürich (Switzerland)

Subject: Modeling and Simulation of Correlated Carrier Transport in Semiconductor Devices Period: April 00 – March 02 Funding: SNF*

Subject: Iterative Methoden zur parallelen Lösung grosser linearer Gleichungssysteme aus der Halbleiter-Simulation (Iterative Methods for Parallel Solving of Large Linear Systems from Semiconductor Simulation) Partner: ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: July 00 – June 02 Funding: KTI* ISE Integrated Systems Engineering AG, Zürich (Switzerland)

121

Subject: VCSELs - Numerical Simulation of Vertical-Cavity Surface-Emiting Laser Diodes Partner: ISE Integrated Systems Engineering AG, Zürich (Switzerland) Pilot User: Institute for Micro- and Nanoelectronics, EPF Lausanne (Switzerland) Avalon Photonics AG, Zürich (Switzerland) Laboratory for Electromagnetic Fields and Waves, ETH Zürich (Switzerland) Walter Schottky Institut, TU München, Garching (Germany) Period: Oktober 00 – September 02 Funding: TOP NANO 21 ISE Integrated Systems Engineering AG, Zürich (Switzerland)

Subject NANOTCAD - Nanotechnology Computer Aided Design (European IST Project) Partner: Universita degli studi di Pisa (DII-EIT), Pisa (Italy) National Microelectronics Research Centre (NMRC-UCC), Cork (Ireland) Max-Planck-Institut für Festkörperforschung (MPG), München (Germany) TU Vienna, Institute for Mikroelectronics (TUV), Vienna (Austria) Bayerische Julius-Maximilians Universität Würzburg, Würzburg (Germany) Period: April 00 – March 03 Funding: BBW*, European Union

Subject Meshes and Global Integration for Semiconductor Front-End Simulation Partner: ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: January 00 – December 02 Funding: ISE Integrated Systems Engineering AG, Zürich (Switzerland)

Subject Noise Calibration in Advanced Bipolar Semiconductor Technologies Partner: ISE Integrated Systems Engineering AG, Zürich (Switzerland) Toshiba Corporation, Yokohama (Japan) Period: April 00 – September 01 Funding: ISE Integrated Systems Engineering AG, Zürich (Switzerland)

Subject Intraband Photon Absorption in Multi-Quantum-Well (MQW) Structures Partner: Fujitsu Laboratories Ltd., Atsugi (Japan) Period: April 01 – March 02 Funding: ISE Integrated Systems Engineering AG, Zürich (Switzerland)

Subject: Improvement of Semiconductor Process Simulator by Atomistic Simulation Techniques (MOLDYN) Partner: ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: January 02 – December 03 Funding: TOP NANO 21 ISE Integrated Systems Engineering AG, Zürich (Switzerland)

Subject: High Speed and Quantum-Well Photodetectors Partner: Opto Speed AG, Rüschlikon (Switzerland) ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: January 02 – December 03 Funding: TOP NANO 21 ISE Integrated Systems Engineering AG, Zürich (Switzerland)

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Subject: Modeling of General Multi-Quantum-Well Structures Including Self- Consistent Coupling to a Laser Simulator (MQW) Partner: Nortel Networks Optical Components (Schweiz) AG, Zürich (Switzerland) ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: January 02 – December 03 Funding: TOP NANO 21 ISE Integrated Systems Engineering AG, Zürich (Switzerland)

123

Physical Characterization and Technology Development

Subject: SUBSAFE – Substrate-Current Safe Smart-Power IC Design Methodology (European ESPRIT IV Project) Partner: Robert Bosch GmbH, Reutlingen (Germany) ISE Integrated Systems Engineering AG, Zürich (Switzerland) Information Capturing and Dissemination: ESD-MSD Cluster, Centro Nacional de Microelectrónica IMSE, Sevilla (Spain) Period: January 99 - October 01 Funding: BBW*, European Union

Subject HIMRATE - High-temperature IGBT- and MOSFET-modules for Railway Traction and automotive Electronic application (European GROWTH Project) Partner: Siemens AG, München (Germany) Regienov – Renault Recherche et Innovation, Guyancourt (France) Institut National de Recherche sur les Transport et leur Sécuruité (INRETS), Arcueil (France) Centro Ricerche Fiat ScpA (CRF), Orbassano (Italy) EUPEC GmbH & Co. KG, Warstein (Germany) Ferraz Date Industries S.A., La Mure (France) Electrovac Fabrikation Elektrotechnischer Spezialartikel GmbH, Klosterneuburg (Germany) Infineon Technologies AG, München (Germany) Ansaldo Transporti SpA, Napoli (Italy) Technical University Vienna, Wien (Austria) Technische Universität München, München (Germany) Period: November 00 – Oktober 03 Funding: BBW*, European Union

Subject Modelierung und Charakterisierung von IGBT-Modulen (Modeling and Characterization of IGBT-Modules) Partner: ABB Corporate Research Ltd., Dättwil (Switzerland) ABB Semiconductors AG, Lenzburg (Switzerland) ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: January 01 – December 03 Funding: KTI* ABB Corporate Research Ltd., Dättwil (Switzerland) ABB Semiconductors AG, Lenzburg (Switzerland)

Subject Modelling of the High-Frequency SOI Power MOSFET Partner: Nippon Telegraph and Telephone Corporation, Tokyo (Japan) ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: April 00 – March 01 Funding: Nippon Telegraph and Telephone Corporation, Tokyo (Japan)

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Subject HERCULAS - High resolution electrical characterisation of ULSI and advanced semiconductor devices (European IHP – RTN Project) Partner: Interuniversity Microelectronics Centre (IMEC), Leuven (Belgium) Hahn-Meitner-Institut Berlin GmbH (HMI), Berlin (Germany) ST Microelectronics SA (ST Crolles), Crolles (France) Philips Electronics Nederland B.V., Eindhoven (The Netherlands) Universität Hamburg, Hamburg (Germany) Infineon Technologies AG, München (Germany) Consiglio Nationale di Metodolgie e Tecnologie per la Microelettronica (CNR- IMETEM), Catania (Italy) Kungl Tekniska Högskolan (KTH), Kista (Sweden) Institute for Semiconductor Physics (IHP), Frankfurt (Germany) Tel-Aviv University (TAU), Tel-Aviv (Israel) Period: Oktober 00 – September 03 Funding: BBW*, European Union

Subject: DEMAND – Integrated Design Methodology for enhANced Device Robustness (European IST Project) Partner: Infineon Technologies AG, München (Germany) Technical University of Vienna, Wien (Austria) Uni Bologna, Universita degli Studi di Bologna, Dipartimento di Elettronica Informatica e Sistemistica, Bologna (Italy) ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: September 01 – August 04 Funding: BBW*, European Union

Subject Total Simulation between electrical and thermal effect for automobile IGBT module Partner: Toyota Central Laboratories Inc., Aichi (Japan) Period: February 01 – January 02 Funding: Toyota Central Laboratories Inc., Aichi (Japan)

Subject: SP3M - Scanning Probe Microscopy assisted Modeling in Microelectronics (Part 2) Period: July 01 – June 03 Funding: SNF*

Subject: ASDESE - Application Specific Design for ESD and Substrate Effects Partner: Robert Bosch GmbH, Reutlingen (Germany) Period: September 01 - February 03 Funding: Robert Bosch GmbH, Reutlingen (Germany) German Government

125

Bio Electromagnetics and Electromagnetic Compatibility

Subject Untersuchung der SAR-Verteilung in elektromagnetisch exponierten Versuchstieren (Investigation of the SAR-Distribution in Electromagnetic Exposed Experimental Animals) Partner: Bundesamt für Strahlenschutz, Salzgitter (Germany) Period: January 00 – June 01 Funding: BfS, Salzgitter (Germany)

Subject Definieren der Messmethodik und Verkleinern der Messunsicherheit bei Immissionsmessungen in Wohn- und Geschäftshäusern (Definition of Measurement Methodology and Reduction of Measurement Uncertainty of Electromagnetic Field Measurements in Living and Business Rooms) Partner: Foundation for Research on Information Technologies in Society (IT'IS), Zürich (Switzerland) Period: August 00 – July 02 Funding: FNM, Zürich (Switzerland)

Subject REFLEX - Risk Evaluation of Potential Environmental Hazards from Low Energy Electromagnetic Field Exposure using Sensitive InVitro Methods (European IST-Project) Partner: Stiftung für Verhalten und Umwelt (VERUM), München (Germany) Universitätsklinikum Benjamin Franklin der freien Universität Berlin (UKBF Berlin), Berlin (Germany) Universitätsklinik für Innere Medizin IV Klinische Abteilung Arbeitsmedizin (AMUW Wien), Wien (Austria) Institut für Pflanzengenetik und Kulturpflanzenforschung Gatersleben (IPK Gatersleben), Gatersleben (Germany) Investigacion Bioelectromagnetismo Hospital Ramon y Cajal (VERYC Madrid) Madrid (Spain) (STUK Helsinki) – Radiation and Nuclear Safety Authority, Helsinki (Finland) Institut für Biophysik Universität Hannover (IFBH), Hannover (Germany) Universita degli Studi di Bologna Dipartimento di Fisica, Bologna (Italy) Ecole Nationale Supérieure de Chimie et de Physique de Bordeaux (ENSCPB Talence), Talence (France) Universita degli Studi di Milano (UMIL, Milano (Italy) Period: February 00 – August 03 Funding: BBW*, European Union

Subject SEMCAD++: Extension/Improvement of the TCAD Engine SEMCAD for Antenna/EMC Partner: Foundation for Research on Information Technologies in Society (IT'IS), Zürich (Switzerland) Schmid & Partner Engineering AG, Zürich (Switzerland) ISE Integrated Systems Engineering AG, Zürich (Switzerland) Period: April 00 – March 03 Funding: KTI* IT'IS, Zürich (Switzerland) SPEAG, Zürich (Switzerland)

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Subject Forschungskooperation IT’IS – ETH Zürich (Research Cooperation IT’IS – ETH Zürich) Partner: Foundation for Research on Information Technologies in Society (IT'IS), Zürich (Switzerland) Period: since January 00 Funding: IT'IS, Zürich (Switzerland)

Abbreviations

BBT Federal Office for Professional Education and Technology (a Swiss Government Agency) BBW Federal Office for Education and Science (a Swiss Government Agency) KTI Commission for Technology and Innovation (a Swiss Government Agency) SNF Swiss National Science Foundation TOP NANO 21 Technology Oriented Program for Nano Sciences (Research and Technical Development Cooperations between Swiss Universities, Institutes, and Swiss Enterprises, funded by the Swiss Government)

127

Presentations

2001

E. Alonso, Ch. Müller, A. Mari, C. Perez-Martin, J. Dominguez-Vazquez, J.J. Jimenez-Rodriguez, M. J. Caturla, W. Fichtner "Low Energy Boron Implants: a Molecular Dynamics Kinetic Monte Carlo Approach", International Workshop on Computational Electronics (IWCE-8) 2001, Champaign IL, USA, October 14- 17, 2001. P. Balmelli "High-Bandwidth Lowpass Sigma-Delta A/D Converters", Workshop on A/D Converters for Telecommunication, Pfäffikon, Switzerland, October 22, 2001. F. M. Bufler, A. Schenk, W. Fichtner "Simplified Inelastic Acoustic-Phonon Hole Scattering Model for Silicon", SISPAD’01, Athens, Greece, September 5, 2001. F. M. Bufler, A. Schenk, W. Fichtner "Proof of a Simple Time-Step Propagation Scheme for Monte Carlo Simulation", MCM2001, Salzburg, Austria, September 12, 2001. F. M. Bufler, W. Fichtner "Hole Transport in Orthorhombically Strained Silicon", IWCE-8, No. 33, Urbana, IL, October 17, 2001. A. Burg, B. Haller, E. Beck, M. Guillaud, M. Rupp, L. Mailaender "A Rapid Prototyping Methodology for Algorithm Development in Wireless Communications”, DATE'01, Munich, Germany March 13-16, 2001. T. Burger, Q. Huang "A 13.5mW, 185Msample/s Delta-Sigma Modulator for UMTS/GSM Dual-Standard IF Reception", ISSCC’2001, San Francisco, USA, February 5-7, 2001. T. Burger "Bandpass Sigma-Delta Converters for Communications", Workshop on A/D Converters for Telecommunication, Pfäffikon, Switzerland, October 22, 2001. N. Chavannes "Next Generation FDTD Modeling Capabilities for Enhanced Analysis of Bioelectromagnetic Interaction Phenomena", 2001 The Bioelectromagnetics Society, St. Paul, MI, USA, June 10-14, 2001. N. Chavannes "Advances Towards Next Generation FDTD Modeling Capabilities", AP-S International Symposium and USNC/URSI National Radio Science Meeting, Boston, MA, USA, July 8-13, 2001. N. Chavannes "Recent Progress in FDTD Modeling Capabilities for Analysis of Transmitters Operating in the Vicinity of Biological Bodies", 2001 International Congress of the European Bio Electromagnetics Association, Helsinki, Finland, September 6-8, 2001. N. Chavannes "Advances in FDTD Modeling Capabilities for Enhanced Analysis of Antennas Embedded in Complex Environments", 2001 International Conference on Electromagnetics in Advanced Applications, Torino, Italy, September 10-14, 2001. N. Chavannes "Advantages and Limitations of FDTD Subgrid Schemes for EM Transmitters Embedded within Highly Complex Non-homogeneous Environments", 2001 International Conference on Applied Electromagnetics and Communications, Dubrovnik, Croatia, October 1-3, 2001.

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A. Christ "Comparison of Human Head Models for the Compliance Testing of Mobile Telephone Equipment", 2001 The Bioelectromagnetics Society, St. Paul, MN, USA, June 10-14, 2001. A. Christ "Experimental and Numerical Comparison of Human Head Phantoms for SAR Assessment at 900 and 1800MHz", AP-S International Symposium and USNC/URSI National Radio Science Meeting, Boston, MA, USA, July 8-13, 2001. M. Ciappa, M. Stangoni, L. Ciampolini, P. Malberti, W. Fichtner "Modeling the Transfer Characteristics and Harmonic Distortion Effects in Scanning Capacitance Microscopy", IEEE Instrumentation and Measurements Technology Conference (IMTC), Budapest, Hungary, May 21- 23, 2001. M. Ciappa "On the Use of Compact Models for Thermal Simulation of Power Devices", Power Semiconductor Workshop, at European Symposium on Reliability of Electron Devices, Arcachon, France, October 1-5, 2001. S. Ebert "Optimized In Vivo Exposure Setups for Risk Assessment Studies at the Mobile Communication Frequencies 902MHz and 1747MHz", 2001 The Bioelectromagnetics Society, St. Paul, MN, USA, June 10-14, 2001. K. Esmark, W. Stadler, H. Gossner, M. Wendel, M. Streibl, W. Fichtner "ESD Protection Concept Development by Means of 2D and 3D Device Simulation -- Do We Still Need Silicon Evaluation?", ESD Forum 2001, Berlin, Germany, December 11-12, 2001. W. Fichtner "Towards Predictable TCAD", MSM 2001, Hilton Head, SC, USA, March 19-20 2001. W. Fichtner "From Microelectronics TCAD Towards Computational Optoelectronics", ETH Workshop "Simulation of Semiconductor Laser Devices", Zurich, Switzerland, October 22-24, 2001. W. Fichtner, K. Esmark, W. Stadler "TCAD Software for ESD ON-Chip Protection Design", IEDM 2001, Washington, DC, USA, December 2-5, 2001. P. A. Francese "High-Speed Sigma-Delta D/A Converters", Workshop on A/D Converters for Telecommunication, Pfäffikon, Switzerland, October 22, 2001. B. Glass, B. Haller, N. Felber, W. Fichtner "High-Performance QR-RLS Filtering ASIC for Wireless LAN Diversity Combining", IASTED International Conference Wireless and Optical Communications, Banff, Alberta, Canada, pp. 192-196, June 27-29, 2001. M. Guillaud, A. Burg, M. Rupp, E. Beck, S. Das "Rapid Prototyping Design of a 4x4 BLAST-over-UMTS System", 35th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, November 4-7, 2001. C. Hammerschmied "Nyquist A/D Converters - A General Overview", Workshop on A/D Converters for Telecommunication, Pfäffikon, Switzerland, October 22, 2001. C. Hammerschmied "Pipelined A/D Converters for Telecommunication Applications", Workshop on A/D Converters for Telecommunication, Pfäffikon, Switzerland, October 22, 2001.

128

J. Hertle "High-Speed Folding and Interpolation A/D Converters", Workshop on A/D Converters for Telecommunication, Pfäffikon, Switzerland, October 22, 2001. F. Heinz, A. Schenk, A. Scholze, W. Fichtner "Full Quantum Simulation of Silicon-on-Insulator Single-Electron Devices", IWCE-8, No. 30, Urbana, IL, USA, October 17, 2001. N. Hitschfeld, L. Villablanca, J. Krause, M.C. Rivara "Improving the Quality of Meshes for the Simulation of Semiconductor Devices using LEPP-Based Algorithms", 3rd Symposium on Trends in Unstructured Mesh Generation, 6 U. S. National Congress of Computational Mechanics, Dearborn, MI, USA, August 1-4, 2001. Q. Huang "Introduction to Sigma-Delta Converters", Workshop on A/D Converters for Telecommunication, Pfäffikon, Switzerland, October 22, 2001. H. Kaeslin "Wie funktionieren Mikrochips und wie werden sie entwickelt?", Naturforschende Gesellschaft Oberwallis, Brig, Switzerland, November 22, 2001. M. G. Khazhinsky, A. Höfler, M. Stockinger, D. J. Collins, L. Clejan, K. Wimmer, W. Taylor, M. Foisy, J.M.Higman (Motorola, Inc., 6501 William Cannon Drive, Austin, TX 78735, U.S.A.) L. Bomholt, Ch. Clémonçon, O. Zuyakova, W. Fichtner (ISE Integrated Systems Engineering AG, Zurich, Switzerland) "A Shared Architecture for a Dynamic Technology Simulation Repository", SISPAD’01, Athens, Greece, September 5, 2001. N. Kuster "Conducting Research & Exposure Assessments & Setups (invited)'', Mobile Telecommunications and Health Research Program, Department of Health, London, Great Britain, February 9, 2001. N. Kuster "Criteria for Selecting Specific EMF Exposure Conditions for Bioexperiments in the Context of Health Risk Assessment (invited)", EMC Zurich, Switzerland, February 22, 2001. N. Kuster "Conducting Research & Exposure Assessments & Setups (invited)", R&TTE and EMC in Telecom, London, Great Britain, March 8, 2001. N. Kuster "Selection and Implementation of Specific EMF Exposure Conditions for Bioexperiments in the Context of Health Risk Assessment (invited)", 2001 International Symposium on Electromagnetics in Biology and Medicine, University of Tokyo, Japan, April 4, 2001. N. Kuster, K. Pokovic "Technical Trend on SAR Measurements (invited)", ARIB Headquarter, Tokyo, Japan, April 5, 2001. N. Kuster "Advances in Antenna Design (invited)", Toshiba Corporation, Tokyo, Japan, April 6, 2001. N. Kuster "Criteria for Selecting Specific EMF Exposure Conditions for Bioexperiments in the Context of Health Risk Assessment", The Bioelectromagnetics Society, St. Paul, MN, USA, June 10-14, 2001. N. Kuster "Exposure Setups for Large Scale NTP Studies", NIEHS-Workshop, St. Paul, MN, USA, June 13, 2001.

129

N. Kuster "International Activities - Risk Assessment of Mobile Communications ", NIS Workshop - BUWAL, Bern, Switzerland, November 7, 2001. G. Meneghesso, A. Chini, A. Maschietto, E. Zanoni, P. Malberti, M. Ciappa "Electrostatic Discharge and Electrical Overstress on GaN/InGaN Light Emitting Diodes", ESD/EOS Symposium, Portland, OR, USA, September 9-13, 2001. D. H. Neuhaus, P. P. Altermatt, A. B. Sproul, R. A. Sinton, A. Schenk, A. Wang, and A. G. Aberle "Method for Measuring Minority and Majority Carrier Mobilities in Solar Cells", 17th European Photovoltaic Solar Energy Conference and Exhibition, Munich, Germany, October 22-26, 2001. M. Oberle, R. Reutemann, J. Hertle, Q. Huang "A 10mW 2-Channel Fully Integrated System-on-Chip for Eddy-Current Position Sensing", ESSCIRC’2001, Villach, Austria, September 18-20, 2001. D. Pfaff, J. Rogin, Q. Huang "A 14mA 2GHz 0.25µm CMOS Quadrature Demodulator Including a Low Phase Noise Local Oscillator", IEEE European Solid State Circuits Conference, Villach, Austria, September 18-20, 2001. M. Pfeiffer, A. Witzig, W. Fichtner "Coupled Electro-Thermo-Optical 3D Simulation of Edge-Emitting Lasers", NUSOD'01, Santa Barbara, CA, USA, March 25-27, 2001. M. Pfeiffer, B. Witzigmann, A. Witzig, W. Fichtner "Laser- DESSIS: A Comprehensive Multidimensional Microscopic Simulation Tool for Quantum Well Lasers", First SIAM/EMS Conference, Berlin, Germany, September 2-6, 2001. M. Pfeiffer, B. Witzigmann, A. Witzig, M. Streiff, W. Fichtner "Laser-DESSIS: Comprehensive and Multidimensional Laser Simulation", ETH Workshop "Simulation of Semiconductor Laser Devices", Zurich, Switzerland, October 22-24, 2001. M. Schaldach "Transient Simulation", Workshop on Substrate Effects in Smart-Power ICs at ESSDERC’2001, Nuremberg, Germany, September 14, 2001. A. Schenk "Physical Modeling of Deep-Submicron Devices", ESSDERC’01, Nuremberg, Germany, September 11-13, 2001. O. Schenk, K. Gärtner "Sparse Factorization with Two-Level Scheduling in PARDISO", SIAM’2001, Portsmouth, VI, USA, March 12-14, 2001. M. Schenkel, P. Pfäffli, W. Wilkening, D. Aemmer, W. Fichtner "Transient Minority Carrier Collection from the Substrate in Smart Power Design", ESSDERC'2001, Nuremberg, Germany, September, 11-13, 2001. M. Schenkel "Measurements and Calibration", Workshop on Substrate Effects in Smart-Power ICs at ESSDERC'2001, Nuremberg, Germany, September 14, 2001. B. Schmithüsen "Grid Adaptation in Semiconductor Device Simulation for the Stationary Drift-Diffusion Model in 2 Dimensions", Weierstrass Institut für Angewandte Analysis und Stochastik (WIAS), Berlin, Germany, January 29 - February 02, 2001. L. Schneider, A Witzig, M. Pfeiffer, M. Streiff, W. Fichtner "Simulation of a Tunable Twin-Guide (TTG) DFB Laser", ETH Workshop "Simulation of Semiconductor Laser Devices", Zurich, Switzerland, October 22-24, 2001.

130

J. Schuderer, R. Mertens, W. Oesch, U. Frauenknecht, N. Kuster "Flexible and Efficient In Vitro Exposure Setup for Risk Assessment Studies at 1800MHz Enabling any Modulation Scheme from Sub-Hz up to 15MHz and Double Blind Protocols", BEMS’01 Twenty-Third Annual Meeting, St. Paul, MI, USA, June 10-14, 2001. M. Stangoni "Phase-Resolved SCM Measurements", 2nd Herculas Workshop, Zurich, Switzerland, February 19, 2001. M. Stangoni "Identification of Artifacts Arising during SCM Measurements", 3rd Herculas Workshop, Grenoble, France, October 21-22, 2001. M. Streiff, A. Witzig, M. Pfeiffer, W. Fichtner "Numerical Simulation of Vertical-Cavity Surface-Emitting Laser Diodes", Top Nano 21 Annual Meeting, Berne, Switzerland, October 16, 2001. M. Streiff, A. Witzig, W. Fichtner "Optical Mode Solver for VCSEL Devices", Workshop "Simulation of Semiconductor Laser Devices", ETH Zurich, Switzerland, October 22-24, 2001. J. Thalheim, N. Felber, W. Fichtner "A New Approach for Controlling Series-Connected IGBT Modules", ISCAS’2001, Sydney, NSW, Australia, May 6-9, 2001. T. Villiger, J. Muttersbach, H. Kaeslin, N. Felber, W. Fichtner "A Globally-Asynchronous Locally-Synchronous VLSI Circuit for the SAFER Crypto Algorithm" First ACiD-WG Workshop, Neuchatel, Switzerland, February 12-13, 2001. A. Witzig, M. Streiff, W. Fichtner "Time-Tomain Green's Functions of Realistic VCSEL Cavities", Photonics West, San Jose, CA, USA, January 2001. A. Witzig, M. Streiff, W. Fichtner "Calculating the Optical Modes of Realistic VCSEL Devices", NUSOD-01, Santa Barbara, CA, USA, March 25-27, 2001. A Witzig, M. Pfeiffer, M. Streiff, L. Schneider, W. Fichtner "Pilot User Workshop Tutorial", Workshop "Simulation of Semiconductor Laser Devices", ETH Zurich, Switzerland, October 22-24, 2001. A Witzig, M. Streiff, W. Fichtner "Rigorous Calculation of the Spontaneous Emission in Edge-Emitting Lasers", Workshop "Simulation of Semiconductor Laser Devices", ETH Zurich, Switzerland, October 22-24, 2001. H. Yabuhara, M.Ciappa, W.Fichtner "Diamond-Coated Cantilevers for Scanning Capacitance Microscopy Applications", European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Arcachon, France, October 1-5, 2001. H. Yabuhara "SCM Response of Ultrathin Oxides Grown at Low Temperatures", 2nd Herculas Workshop, Zurich, Switzerland, February 19, 2001. H. Yabuhara "Characteristics of Diamond-Coated Cantilevers for SCM Applications", 3rd Herculas Workshop, Grenoble, France October 21-22, 2001.

131

Publications

2001

F. M. Bufler, A. Schenk, W. Fichtner "Simplified Model for Inelastic Acoustic Phonon Scattering of Holes in Si and Ge", Journal of Applied Physics, Vol. 90, No. 5, pp. 2626-28, 2001. F. M. Bufler, A. Schenk, W. Fichtner "Simplified Inelastic Acoustic-Phonon Hole Scattering Model for Silicon", Proceedings of SISPAD’01, Athens, Greece, pp. 42-45, September 5, 2001. F. M. Bufler, P. D. Yoder, W. Fichtner "Strain-Dependence of Electron Transport in Bulk Si and Deep-Submicron MOSFETS", VLSI Design, Vol. 13, pp. 163-167, 2001. A. Burg, B. Haller, E. Beck, M. Guillaud, M. Rupp, L. Mailaender "A Rapid Prototyping Methodology for Algorithm Development in Wireless Communications", Proceedings of DATE'01, Munich, Germany, pp. 133-137, March 13-16, 2001. T. Burger, Q. Huang "A 13.5mW, 185Msample/s Delta-Sigma Modulator for UMTS/GSM Dual-Standard IF Reception", ISSCC’01 Digest of Technical Papers, San Francisco, CA, USA, pp. 44-45, February 5-7, 2001. T. Burger, Q. Huang "A 13.5mW, 185Msample/s Delta-Sigma Modulator for UMTS/GSM Dual-Standard IF Reception", IEEE Journal of Solid-State Circuits, vol. 36, pp. 1868-1878, Dec. 2001. N. Chavannes, H.-U. Gerber, A. Christ, J. Fröhlich, H. Songoro, N. Kuster "Next Generation FDTD Modeling Capabilities for Enhanced Analysis of Bioelectromagnetic Interaction Phenomena", Proceedings of 2001 The Bioelectromagnetics Society, St. Paul, MN, USA, pp. 66, June 10-14, 2001. N. Chavannes, H.-U. Gerber, A. Christ, J. Fröhlich, H. Songoro, N. Kuster "Advances Towards Next Generation FDTD Modeling Capabilities", Proceedings of the AP-S International Symposium and USNC/URSI National Radio Science Meeting, Boston, MA, USA, pp. 257, July 8-13, 2001. N. Chavannes, H.-U. Gerber, A. Christ, J. Fröhlich, H. Songoro, N. Kuster "Recent Progress in FDTD Modeling Capabilities for Analysis of Transmitters Operating in the Vicinity of Biological Bodies", Proceedings of 2001 International Congress of the European Bio Electromagnetics Association, Helsinki, Finland, pp. 73-74, September 6-8, 2001. N. Chavannes, H.-U. Gerber, A. Christ, J. Fröhlich, H. Songoro, N. Kuster "Advances in FDTD Modeling Capabilities for Enhanced Analysis of Antennas Embedded in Complex Environments", Proceedings of the 2001 International Conference on Electromagnetics in Advanced Applications, Torino, Italy, pp. 353-356, September 10-14, 2001. N. Chavannes, H.-U. Gerber, A. Christ, N. Kuster "Advantages and Limitations of FDTD Subgrid Schemes for EM Transmitters Embedded within highly Complex Non-Homogeneous Environment", Proceedings of the 16th International Conference on Applied Electromagnetics and Communications, Dubrovnik, Croatia, pp. 85-89, October 1-3, 2001. A. Christ, N. Nikoloski, N. Chavannes, N. Kuster "Comparison of Human Head Models for the Compliance Testing of Mobile Telephone Equipment", Proceedings of 2001 The Bioelectromagnetics Society, St. Paul, MN, USA, pp. 66-67, June10-14, 2001. A. Christ, K. Pokovic, H.-U. Gerber, N. Chavannes, N. Kuster "Experimental and Numerical Comparison of Human Head Phantoms for SAR Assessment at 900 and 1800MHz", Proceedings of the AP-S International Symposium and USNC/URSI National Radio Science Meeting, Boston, MA, USA, pp. 418, July 8-13, 2001.

133

L. Ciampolini, F. Giannazzo, M. Ciappa, W. Fichtner, V. Raineri "Simulation of Scanning Capacitance Microscopy Measurements on Micro-Sectioned and Bevelled n+-p Samples", Material Science in Semiconductor Processing Journal, Vol. 4, pp. 85-88, 2001. L. Ciampolini "Scanning Capacitance Microscope Imaging and Modelling", PhD Thesis ETH-Nr. 14304, Hartung-Gorre Verlag, Konstanz, Germany, 2001. M. Ciappa, M. Stangoni, L. Ciampolini, P. Malberti, W. Fichtner "Modeling the Transfer Characteristics and Harmonic Distortion Effects in Scanning Capacitance Microscopy", Proceedings of IEEE Instrumentation and Measurement Technology Conference, Budapest, Hungary, Vol. 18, pp. 804-809, May 21-23, 2001. S. Ebert, R. Mertens, N. Kuster "Criteria for selecting Specific EMF Exposure Conditions for Bioexperiments in the Context of Health Risk Assessment", Proceedings of EMC Zurich, ETH, Zurich, February 2001. S. Ebert, J. Fröhlich, W. Oesch, U. Frauenknecht, N. Kuster "Optimized In Vivo Exposure Setups for Risk Assessment Studies at the Mobile Communication Frequencies 902MHz and 1747MHz", Proceedings of 2001 The Bioelectromagnetics Society, St. Paul, MN, USA, pp. 27, June 10-14, 2001. K. Esmark, W. Stadler, H. Gossner, M. Wendel, M. Streibl, W. Fichtner "ESD Protection Concept Development by Means of 2D and 3D Device Simulation – Do We Still Need Silicon Evaluation?", Proceedings of ESD Forum 2001, Berlin, Germany, pp. 95-104, December 11-12, 2001. W. Fichtner "Towards Predictable TCAD", MSM 2001, Hilton Head, SC, USA, pp. 1-4, March 19-20 2001. W. Fichtner, K. Esmark, W. Stadler "TCAD Software for ESD On-Chip Protection Design", Proceedings of IEDM’01, Washington, DC, USA, pp. 14.1.1-14.1.4, December 2-5, 2001. J. Fröhlich, W. Kainz, S. Ebert, T. Samaras, G. Neubauer, N. Kuster "Exposure Setups for Simultaneous Exposure of a Large Number of Rats for Risk Assesment Studies at the Mobile Communication Frequencies 902MHz and 1747MHz", Proceedings of 2001 International Congress of the European Bio Electromagnetics Association, Helsinki, Finland, September 6-8, 2001. F. Giannazzo, L. Calcagno, V. Raineri, L. Ciampolini, M. Ciappa, E. Napolitani "Quantitative Carrier Profiling in Ion-Implanted 6H-SiC", Applied Physics Letters, Vol. 79, 1211-1213, 2001. B. Glass, B. Haller, N. Felber, W. Fichtner "High-Performance QR-RLS Filtering ASIC for Wireless LAN Diversity Combining", Proceedings of the IASTED International Conference Wireless and Optical Communications, Banff, Alberta, Canada, pp. 192-196, June 27-29, 2001. M. Guillaud, A. Burg, M. Rupp, E. Beck, S. Das "Rapid Prototyping Design of a 4x4 BLAST-Over-UMTS System", Proceedings of the 35th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, November 4-7, 2001. C. Hammerschmied "CMOS A/D Converters using MOSFET-Only R-2R Ladders", PhD Thesis ETH-Nr. 13921, Hartung-Gorre Verlag, Konstanz, Germany, 2001. N. Hitschfeld, L. Villablanca, J. Krause, M.C. Rivara "Improving the Quality of Meshes for the Simulation of Semiconductor Devices using LEPP-based Algorithms", Proceedings of 3rd Symposium on Trends in Unstructured Mesh Generation, 6th U. S. National Congress of Computational Mechanics, Dearborn, MN, USA, pp. 319, August 1-4, 2001.

134

W. Kainz, N. Nikoloski, E. Schuhmacher, R. Überbacher, N. Chavannes, J. Fröhlich, G. Neubauer, N. Kuster "High Resolution Animal Models for Numerical Dosimetry", Proceedings of 2001 International Congress of the European BioElectromagnetics Association, Helsinki, Finland, pp. 57-58, September 6-8, 2001. M. G. Khazhinsky, A. Hoefler, M. Stockinger, D. J. Collins, L. Clejan, K. Wimmer, W. Taylor, M. Foisy, J.M.Higman (Motorola, Inc., 6501 William Cannon Drive, Austin, TX 78735, U.S.A.) L. Bomholt, Ch. Clémonçon, O. Zuyakova, W. Fichtner (ISE Integrated Systems Engineering AG, Zurich, Switzerland) "A Shared Architectue for a Dynamic Technology Simulation Repository", Proceedings of SISPAD’01, Athens, Greece, pp. 348-351, September 5, 2001. J. Krause "On Bonndary Conforming Anisotropic Delaunay Meshes", PhD Thesis ETH-Nr. 14219, Hartung-Gorre Verlag, Konstanz, Germany, 2001. N. Kuster, W. Ross Adey, S. Ebert, W. Oesch "Selection and Implementation of Specific EMF Exposure Conditions for Bioexperiments in the Context of Health Risk Assessment", Proceedings of 2001 International Symposium on Electromagnetics in Biology and Medicine, University of Tokyo, Japan, pp. 67, April 4, 2001. N. Kuster, J. Fröhlich, S. Ebert "Exposure Setup Design for Large Scale NTP-Like Bioassays", Proceedings of 2001 Asia-Pacific Radio Science Conference, University of Tokyo, Tokyo, Japan, pp. 245-246, August 1-4, 2001. N. Kuster, W. R. Adey "Criteria for Selecting Specific EMF Exposure Conditions for Bioexperiments in the Context of Health Risk Assessment", Proceedings of 2001 The Bioelectromagnetics Society, St. Paul, MN, USA, pp. 28, June 10-14, 2001. N. Kuster, "Latest Progress in Experimental Dosimetry for Human Exposure Evaluations and for Characterization and Optimization of Exposure Setups used in Biological Experiments ", Proceedings of 2001 in Mobile Phones Biological Effects, CADAS, Academie des Sciences, pp. 43-69, Paris, France, 2001. M. Macucci, G. Iannaccone, J. Greer, J. Martorell, D. W. L. Sprung, A. Schenk, I. I. Yakimenko, K.-F. Berggren, K. Stokbro, N. Gippius "Status and Perspectives of Nanoscale Device Modelling", Nanotechnology, Vol. 12, pp. 136-142, 2001. G. Meneghesso, A. Chini, A. Maschietto, E. Zanoni, P. Malberti, M. Ciappa "Electrostatic Discharge and Electrical Overstress on GaN/InGaN Light Emitting Diodes", Proceedings of ESD/EOS Symposium, Portland, OR, USA, pp. 23, September 9-13, 2001. M. Mergens "On-Chip ESD Protection in Integrated Circuits: Device Physics, Modeling, Circuit Simulation", PhD Thesis ETH-Nr. 14185, Hartung-Gorre Verlag, Konstanz, Germany, 2001. J. Muttersbach "Globally-Asynchhronous Locally-Synchronous Architectures for VLSI Systems", PhD Thesis ETH-Nr. 14155, Hartung-Gorre Verlag, Konstanz, Germany, 2001. M. Oberle, R. Reutemann, J. Hertle, Q. Huang "A 10mW 2-Channel Fully Integrated System-on-Chip for Eddy-Current Position Sensing", Proceedings of ESSCIRC’2001, Villach, Austria, pp. 152-155, September 18-20, 2001. I. Omura "High Voltage MOS Device Design: Injection Enhancement and Negative Gate Capacitance", PhD Thesis ETH-Nr. 14049, 2001. D. Pfaff, J. Rogin, Q. Huang "A 14mA 2GHz 0.25µm CMOS Quadrature Demodulator Including a Low Phase Noise Local Oscillator", Proceedings of ESSCIRC’2001, Villach, Austria, pp. 56-59, September 18-20, 2001.

135

M. Pfeiffer, A. Witzig, W. Fichtner "Coupled Electro-Thermo-Optical 3D Simulation of Edge-Emitting Lasers", Proceedings of NUSOD'01, Santa Barbara, CA, USA, pp. 20-21, March 25-27, 2001. K. Pokovic, T. Schmid, N. Kuster, "Evaluation of Ten Commercially Available Dosimetric E-Field Probes", Proceedings of 2001 The Bioelectromagnetics Society, St. Paul, MN, USA, pp. 82, June 10-14, 2001. S. Reggiani, M. Valdinoci, L. Colalongo, M. Rudan, G. Baccarani, A. Stricker, F. Illien, N. Felber, W. Fichtner, L. Zullino "Electron and Hole Mobility in Silicon at Large Operating Temperatures. Part I – Bulk Mobility", IEEE Transactions on Electron Devices, vol.49, No. 3, march 2002. A. Schenk "Physical Modeling of Deep-Submicron Devices", Proceedings of ESSDERC’01, Nuremberg, Germany, pp. 9-16, September 11-13, 2001. O. Schenk, K. Gärtner "Sparse Factorization with Two-Level Scheduling in PARADISO", SIAM’2001, Portsmouth, VA, USA, pp. 427-436, March 12-14, 2001. M. Schenkel, P. Pfäffli, W. Wilkening, D. Aemmer, W. Fichtner "Substrate Potential Shift due to Parasitic Minority Carrier Injection in Smart-Power ICs: Measurements and Full-Chip 3D Device Simulation", Microelectronics Reliability, Vol. 41, No. 6, pp. 815-822, June 2001. M. Schenkel, P. Pfäffli, W. Wilkening, D. Aemmer, W. Fichtner "Transient Minority Carrier Collection from the Substrate in Smart Power Design", Proceedings of ESSDERC'2001, Nuremberg, Germany, pp. 411-414, September 11-13, 2001. F. Schönborn, K. Pokovic, M. Burkhardt, N. Kuster "Basis for Optimization of In Vitro Exposure Setups for Health Hazard Evaluation of Mobile Communications", Bioelectromagnetics, Vol. 22, No.8, pp. 547-559, December 2001. J. Schuderer, R. Mertens, W. Oesch, U. Frauenknecht, N. Kuster "Flexible and Efficient In Vitro Exposure Setup for Risk Assessment Studies at 1800MHz enabling any Modulation Scheme from Sub-Hz up to 15MHz and Double Blind Protocols", Proceedings of 2001 The Bioelectromagnetics Society, St. Paul, MN, USA, pp. 26, June 10-14, 2001. Ch. Schuster, W. Fichtner "Parasitic Modes on Printed Circuit Boards and their Effects on EMC and Signal Integrity", IEEE Transactions on Electromagnetic Compatibility, Vol. 43, No. 4, pp. 416-425, 2001. M. Stadler, T. Röwer, H. Kaeslin, N. Felber, W. Fichtner "Design and Verification of a Stack Processor Virtual Component", IEEE Micro, Vol. 21, No. 2, pp. 69-80, March/April 2001. M. Streiff, A. Witzig, M. Pfeiffer, W. Fichtner "Numerical Simulation of Vertical-Cavity Surface-Emitting Laser Diodes" TOP NANO 21 Second Annual Report, Bern, Switzerland, pp. 74-75, October 16, 2001. J. Thalheim, N. Felber, W. Fichtner "A New Approach for Controlling Series-Connected IGBT Modules", Proceedings of ISCAS 2001, Sydney, NSW, Australia, pp. 69-72 Vol. 2, May 6-9, 2001. T. Villiger, J. Muttersbach, H. Kaeslin, N. Felber, W. Fichtner "A Globally-Asynchronous Locally-Synchronous VLSI Circuit for the SAFER Crypto Algorithm", First ACiD-WG Workshop, Neuchâtel, Switzerland, February 12-13, 2001. J. Wassner "Data Statistics and Low-Power Digital VLSI", PhD Thesis ETH-Nr. 14395, Hartung-Gorre Verlag, Konstanz, Germany, 2001. A. Wettstein, A. Schenk, W. Fichtner "Quantum Device-Simulation with the Density-Gradient Model on Unstructured Grids", IEEE Transactions on Electron Devices, Vol. 48, No. 2, February 2001.

136

A. Witzig, M. Streiff, W. Fichtner "Time-Domain Green's Functions of Realistic VCSEL Cavities", Proceedings of SPIE, Photonics West, San Jose, CA, USA, Vol. 4283, No. 13, pp. 19-20, January 2001. A. Witzig, M. Streiff, W. Fichtner "Calculating the Optical Modes of Realistic VCSEL Devices", Proceedings of NUSOD-01, Santa Barbara, CA, USA, March 25-27, 2001. A. Witzig, M. Streiff, W. Fichtner "Time-Domain Green's Functions of Realistic VCSEL Cavities", Proceedings of SPIE, Vol. 4283, No. 13, January 2001. H. Yabuhara, M.Ciappa, W.Fichtner "Diamond-Coated Cantilevers for Scanning Capacitance Microscopy Applications", Microelectronic Reliability, Vol. 41, pp. 1459-1463, 2001. C.-S. Yun, P. Malberti, M. Ciappa, W. Fichtner "Thermal Component Model for Electro-Thermal Analysis of IGBT Module Systems", IEEE Transactions on Advanced Packaging, Vol. 24, pp. 401-406, 2001. S. Zelenka "Stress-Related Problems in Process", PhD Thesis ETH-Nr. 14220, Hartung-Gorre Verlag, Konstanz, Germany, 2001.

137

Technical Reports

A. Witzig, M. Streiff, W. Fichtner Time-domain Green‘s functions of realistic VCSEL cavities Technical Report 2001/1

B. Schmithüsen, K. Gärtner, W. Fichtner A Grid Adaptation Procedure for the Stationary 2D Drift-Diffusion Model Based on Local Dissipation Rate Error Estimation: Part I – Background Technical Report 2001/2

B. Schmithüsen A Grid Adaptation Procedure for the Stationary 2D Drift-Diffusion Model Based on Local Dissipation Rate Error Estimation: Part II – Background Technical Report 2001/3

M P. J. Mergens, W. Wilkening, G. Kiesewetter, St. Mettler, H. Wolf, J. Hieber, W. Fichtner ESD-level Circuit Simulation - Impact of Gate RC-Delay on HBM and CDM Behavior Technical Report 2001/4

W. Fichtner Towards Predictable TCAD Technical Report 2001/5

O. Schenk, K. Gärtner Sparse Factorization with Two-Level Scheduling in PARADISO Technical Report 2001/6

F. M. Bufler, A. Schenk, W. Fichtner Simplified Inelastic Acoustic-Phonon Hole Scattering Model for Silicon Technical Report 2001/10

F. M. Bufler, A. Schenk, W. Fichtner Simplified model for inelastic acoustic phonon scattering of holes in Si and Ge Technical Report 2001/11

A. Schenk Physical Modeling of Deep-Submicron Devices Technical Report 2001/12

M. Schenkel, P. Pfäffli, W. Wilkening, D. Aemmer, W. Fichtner Substrate Potential Shift due to Parasitic Minority Carrier Injection in Smart- Power ICs: Measurements and Full-Chip 3D Device Simulation Technical Report 2001/13

M. Schenkel, P. Pfäffli, W. Wilkening, D. Aemmer, W. Fichtner Transient Minority Carrier Collection from the Substrate in Smart Power Design Technical Report 2001/14

T. Villiger, J. Muttersbach, H. Kaeslin, N. Felber, W. Fichtner A Globally-Asynchronous Locally-Synchronous VLSI Circuit for the SAGFER Cryptoalgorithm Technical Report 2001/15

H. Yabuhara, M. Ciappa, W. Fichtner Diamond-Coated Cantilevers for Scanning Capacitance Micorscopy Applications Technical Report 2001/16

J. Thalheim, N. Felber, W. Fichtner A new approach for controlling series-connected IGBT modules Technical Report 2001/18

B. Glass, B. Haller, N. Felber. W. Fichtner High-Performance QR-RLS Filtering ASIC for Wireless LAN Diversity Combining Technical Report 2001/19

137

M. Pfeiffer, A. Witzig, B Witzigmann, W. Fichtner Coupled Electro-Thermo-Optical 3D Simulation of Edge-Emitting Lasers and Laser-Dessis: A Comprehensive Multidimensional Mocroscopic Simulati. Tool for Quantum Well Lasers Technical Report 2001/20

F. M. Bufler, P. D. Yoder, W. Fichtner Strain-Dependence of Electron Transport in Bulk Si and Deep-Submicron MOSFTs Technical Report 2001/21

W. Fichtner, K. Esmark, W. Stadler TCAD Software for ESD ON-Chip Protection Design Technical Report 2001/22

A. Burg, B. Haller, E. Beck, M. Guillaud, M. Rupp, L. Mailaender A Rapid Prototyping Methodology for Algorithm Development in Wireless Communications Technical Report 2001/23

Technical Reports can be ordered from: Mrs. Verena Roffler Integrated Systems Laboratory ETH Zentrum CH-8092 Zürich/Switzerland Fax: +41 1 632 11 94 e-mail: [email protected]

138

Design, Electronic Test and Physical Characterization Equipment

ECAD and TCAD Software

MODEL TECHNOLOGY INC. HDL Simulation Package SYNOPSYS Simulation and Synthesis and Test Tools CADENCE DF II and Silicon Ensemble DSM Suite CADENCE Digital and Analog IC Design Tools HEWLETT PACKARD IC-CAP Measurement Control and Parameter Extraction Tools MENTOR GRAPHICS Calibre Physical Design Verification XILINX FGPA Tools ISE-TCAD Software for Process and Device Development

Equipment for Electronic Test

Verification Systems and Logic Analyzers Quantity HP83000, ASIC Verification System, 660MHz 1 IMS XL60, Mixed Signal ASIC Verification System, 60MHz 1 HP16702A, Logic Analysis System, IEEE 2 Tektronix 1240, Logic Analyzer 1

Spectrum and Network Analyzers Quantity Audio Precision System S1, Audio Analyzer 1 Rhode & Schwarz FSIQ3 Signal Analyzer, 20Hz-3.5GHz 1 Rhode & Schwarz FSP7 Spectrum Analyzer, 9Hz-7GHz 1 Agilent 8591E, RF Spectrum Analyzer, 9kHz-1.8GHz 1 HP35670A, Dynamic Signal Analyzer, DC-100kHz 1 HP89441A, Vector Signal Analyzer, DC-2650MHz 1 HP8563E, Spectrum Analyzer, 27GHz 1 Digital Signal Analyzer IIS, 100MS/s, 24bit, 128K Samples 1 Digital Signal Analyzer IIS, 1MS/s, 24bit, 96M Samples 1 Stanford SR785, 2-Channel Dynamic Signal Analyzer 1 HP5501B, Phase Noise Measurement System 1.6GHz 1 HP8720D, Network Analyzer, 50MHz-20GHz 1 HP8751A, Network Analyzer, 5Hz-500MHz, with HP87511A S-Parameter Set 1 HP8753E, Network Analyzer, 30kHz - 6GHz 1 Rhode & Schwarz FSEB30, Spectrum Analyzer, 20Hz-7GHz 1 Tektronix TLS216, 16-Channel Logic Scope, 500MHz 2GS/s, IEEE 1

Oscilloscopes Quantity HP54601A, 4-Channel Digitizing Scope, 100MHz 1 HP5460A, 2-Channel Digitizing Scope 1 Tektronix 2440, 2-Channel Digitizing Scope, 300MHz 500MS/s, IEEE 1 HP54510B, 2-Channel Digitizing Scope, 250MHz 1GS/s, IEEE 1 HP54512B, 4-Channel Digitizing Scope, 300MHz 1GS/s, IEEE 2 HP54542A, 4-Channel Digitizing Scope, 500MHz 2GS/s, IEEE 1 HP54750A, 2-Channel Digitizing Scope, 50GHz, IEEE 1 HP54754A, 2-Channel Differential TDR Module for HP54750A 1 Tektronix TDS684A, 4-Channel Digitizing Scope, 1GHz 5GS/s, IEEE 1 Tektronix TDS784, 4-Channel Digitizing Scope, 1GHz 4GS/s, IEEE 2 Tektronix TDS794D, 4-Channel Digitizing Scope, 2GHz 8GS/s, IEEE 1

139

Kikusui 5041, Scope, 40MHz 3 Iwatsu 6611, Scope, 60MHz 5 Iwatsu 5711, Scope, 100MHz 1 Tektronix 2235, Scope, 100MHz 2 Tektronix 2467B, Scope, 400MHz, Microchannel 1 Tektronix TDS820, 2-Channel Sampling Scope, 6GHz, IEEE 1

Signal Sources, Function Generators Quantity Rhode & Schwarz SML01, RF Signalgenerator, 1GHz 3 Rhode & Schwarz SML03, RF Signalgenerator, 3.3GHz 3 Tektronix SG505, Low-Distortion Oscillator, 10-100kHz, TM502A Power Rack 1 Stanford Research DS360, Low-Noise and -Distortion Function Generator, 200kHz 1 Rhode & Schwarz SMHU 58, Signal Generator, 100kHz-4.320GHz 1 Rhode & Schwarz SMIQ6 RF Vector Signal Generator, 300kHz-6.4GHz 1 Marconi 2042, Low-Noise Signal Generator, 10kHz-5.4GHz 1 Rhode & Schwarz AMIQ, 2 Channel Arbitrary Waveform Generator, 100MS/s 1 HP33120A, Function and Arbitrary Waveform Generator, 15MHz 4 Wavetek 145, Pulse/Function Generator, 20MHz 5 HP8116A, Pulse/Function Generator, 50MHz, 1 HP8110A, Pulse Generator, 150MHz 1 MiniZap ESD-Simulator and HBM-Network 1

Meters Quantity HP8970B, Noise Figure Meter, 2GHz 1 HP3478A, Multimeter, IEEE 1 Keithley 197, Autoranging Microvolt DMM 5 Keithley 197, Autoranging Microvolt DMM, IEEE 1 HP4140B DCV SRC, Picoampere Meter 1 Keithley 485, Autoranging Picoammeter, IEEE 1 Keithley 485, Autoranging Picoammeter 5 Keithley 2002, 9.5-Digit Multimeter 5 Metex M3650, 3.5-Digit Multimeter 8 Metex M4650, 3.5-Digit Multimeter 4 Roline 3660D, 3.5-Digit Multimeter 10 Escort ELC131D, Digital LCR-Meter 1 HP4284A, LCR Meter, 20Hz-1MHz, IEEE 1 Rhode & Schwarz NRV D, RF Power Meter 1 Rhode & Schwarz NRV Z5, Diode Power Sensor 1 Rhode & Schwarz NRV Z5J, Thermal Power Sensor 1 Magnetic Field Meter IIS, 50mT 1 UDT S380, 2-Channel Optometer, IEEE 1

Laboratory Systems Quantity HPE1401A, High-Power Mainframe for VXI-Bus 1 HPE1328A, VXI 4-Channel D/A Converter 1 HPE1406A, VXI Command Module 1 HPE1458A, VXI 96-Channel Digital I/O 1 HPE1490A, VXI Register Based Breadboard 2 HPZ2417A, VXI 32-Channel C Switch 1 Roline MS9150, Universal Power Supply, Wave Generator and Multimeter System 1

Counters Quantity Iwatsu SC7203, Universal Counter, DC-150MHz, 50MHz-1.3GHz 5

Power Supplies Quantity

140

Kikusui PAK6-60A, Power Supply, 6V/60A 1 Kikusui PAK20-18A, Power Supply, 20V/18A 2 HP6626A, System DC Power Supply, 4x 0-16/50V, 2/0.5A, IEEE 2 Thurlby PL310, Power Supply, 30V/1A 10 Thurlby PL320 TGP, Power Supply, 2x 30V/1A, IEEE 2 Thurlby PL330, Power Supply, 30V/3A 10 Topward TPS4000, Power Supply, 2x 30V/2,5A 1 Farnell PDD3010A, Power Supply, 2x 0-30V/10A 1 Heinzinger LNG100-2, Power Supply, 100V/2A 1 Heinzinger LNC3000-20, Power Supply, 3kV/20mA 1 FUG HCN 700-12500, Power Supply, 12,5kV/50mA, IEEE 1

Active Probes, Amplifiers and Attenuators Quantity Agilent 87405A, Preamplifier 22dB, 10MHz-3GHz 1 HP41802A, Input Adapter, 5Hz-100MHz, 1MOhm 4 HP54701A, Active Probes, DC-2.5GHz, 100kOhm 2 Tektronix P6015, High-Voltage Probe, 20kV 1 Tektronix P6206, FET Probe, DC-1GHz 1MOhm 4 Tektronix P6217, FET Probe, DC-4GHz, 100kOhm 2 Tektronix P627, FET Probe, DC-1GHz, diffential, 100kOhm 1 SI 9000, Differential Probe 2 Tektronix AM503, A6302 Current Probe, TM502A Power Rack 1 Tektronix AM503A, A6303 Current Probe, TM502A Power Rack 1 Tektronix CT1 5mV/mA Current Transformer 2 Tektronix CT2 1mV/mA Current Transformer 2 Chase CPA 9231 Preamplifier, 9kHz-1GHz 1 MITEQ AMF-20-001080-20-10P RF Amplifier, 100MHz-8GHz 1 Stanford Research SR560, Low-Noise Preamplifier 1 Stanford Research SR570, Low-Noise Current Preamplifier 1 Rhode & Schwarz, RF Step Attenuator RSH, DC-5.2GHz 1

Equipment for Physical Characterization

Physical Analysis Quantity Balzers SCD 40, Sputter System 1 Cambridge Stereoscan 360, Electron Microscope 1 Ebic Amplifier 1 Electron Microscope 1 Froilabo A, Thermo System 1 FT1020 DLTS 1 Mazali A510Q1, Thermo Test Module 1 Nanoscope Dimension 3100, Atomic Force Microscope System 1 RH2010 Hall Effect Measurement System 1 Schlieter 125l, Thermo Chamber 1 Weiss 305 SB/10Ju40DU, Environmental Testing Chamber 1

Parameter Analyzers Quantity HP4145B, Semiconductor Parameter Analyzer 1 HP4156A, Precision Semiconductor Parameter Analyzer 1 Tektronix Curve Tracer 370 1 HP4142B, Modular DC Source/Monitor 1 HP41420A, Source/Monitor Unit, 4µV-200V/20fA-1A 2 HP41421B, Source/Monitor Unit, 40µV-100V/20fA-100mA 4 HP41422A, High-Current Source/Monitor Unit, 40µV-10V/20nA-10A 2

141

HP41423A, High-Voltage Source/Monitor Unit, 2mV-1000V/2pA-10mA 2 HP41424A, Voltage Source/Voltage Monitor Unit 1 HP4085/4084, Switching Matrix/Control 1

Probers and Utilities Quantity Hamamatsu, Emission Microscope System 1 Wentworth AVT-703, Antivibration Table 1 Cascade Summit 9600, Thermal Probe Station 1 PWS Probe II, Automatic Wafer Prober 1 Suss PA150, Semi Automatic Prober 1 Suss PSM6, Submicron Prober 1 Suss PH100, Micropositioner 12 Suss PH150, Micropositioner 9 Alessi MH4, Micropositioner 2 Temptronic Thermo Chuck, 0 to 200C 1 Temptronic TPO3010B, Thermo Chuck System, 0 to 200C 1 Temptronic TPO4000, Thermo Stream, -60 to 140C 1 Temptronic TPO700A Thermo Chuck System 1 Alessi LG2, Green Laser Cutting System 1 Picoprobe, Active Probe 1

Optical Microscopes Quantity Nikon Optiphot 66, Stereo Microscope 1 Olympus SZ3060, Microscope 1 Zeiss Axiophot, Microscope 1 Zeiss Stemi SV8, Stereo Microscope 1

Photo, Video and Audio Equipment Quantity COHU 8390, CCD RGB Video Camera 1 HITACHI VK-C2000E, Color Video Camera 1 Hughes TVS200, Thermal Video System 1 NIKON Coolpix 950, Digital Camera 1 SONY DXC930, 3-CCD Color Video Camera 1 SONY VTX-100EC, TV Tuner 1 HITACHI VT-168EM, Multi System Video Recorder 1 PANASONIC AG5700, S-VHS NTSC Video Recorder 2 PANASONIC AG5700, S-VHS PAL Video Recorder 2 PANASONIC NV-H1000, S-VHS PAL Video Recorder 1 PANASONIC FT2900, Color Video Monitor 1 PANASONIC WV-CM100, Color Video Monitor 1 SONY KX20-PS1, Color Video Monitor 1 SONY KX27-PS1, Color Video Monitor 1 HITACHI VY300E, Color Video Printer 1 Marantz PM7000 Audio Amplifier, 100W 1 DENON DCD2560, CD-Player 1 Infinity Reference 40 Loudspeaker 2

142 Computer Equipment

Computers are most relevant tools in teaching and re- variants thereof. The file systems of all computers are as- search at IIS. Examples are design of integrated circuits, sembled via NFS into what appears to the user as a single simulation of circuits, devices and technologies for micro- file system. The networking of IIS computers and external electronics and microsystems, development of applica- computers is based on switched 100 Mbit and Gigabit tion software, and information transfer. Ethernet, and on the TCP/IP protocol. Important applications in the technical area are ECAD (Modelsim, Synop- Besides optimal reliability and uncompromising perfor- sys, Cadence, Mentor Graphics), TCAD (ISE AG), as well mance, homogeneity of the computing environment and as publishing and office applications on Macintosh com- user-friendliness are also important. To meet these goals, puters. the computing environment uses the operating system Unix, networking with TCP/IP and NFS, the X-Window System, and the programming languages C, C++, and Fortran 90. Besides the Unix machines in the scientific and technical area, Macintosh computers are widely applied for administration and presentation tasks. A Windows2000 terminal server for mainly office applications is also provided. Several PCs are installed for controlling measurement equipment, for lab classes, and for other special applications.

Memory usage of a 4-CPU Compaq Alpha Server: physical memory allocation of CPU-intensive processes (total size of process). 'max' indicates peak value of all data points collected within 14 hours. All other values are average values of all data points collected within 14 hours. Data points were sampled every five minutes.

Load of a 4-CPU Compaq Alpha Server: ‘Load’ = number of processes in running queue The computing equipment of IIS counts one Unix file serv- ‘Processes’ = number of CPU-intensive processes er, 121 Unix workstations, 25 Macintosh computers, 16 (>15% of CPU capacity) PCs and 15 powerful shared-memory compute servers for physical simulations. The detailed configuration of com- Since the teaching and research activities span many ar- puters at the Integrated Systems Laboratory, the Depart- eas, computer systems of various vendors are utilized. ment of Information Technology and Electrical Engineer- They range from file servers to standard workstations, ing (ITET), and the high-power and parallel computing fa- compute servers, and workstations with specialized dedi- cilities of CSCS (The Swiss Center for Scientific Comput- cated hardware. All Unix computers run SVR4 or BSD, or ing in Manno/Ticino) is shown on the following page.

Representative figures of performance of computers at the Integrated Systems Laboratory: Floating-point performance per CPU (SPECfp2000 benchmark) and memory size (MBytes) of compute servers and Unix workstation

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