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Vlsi in Computers & Processors Proceedings International Conference on Computer Design: VLSl IN COMPUTERS & PROCESSORS October 2 - 4,1995 Austin, Texas Sponsored by IEEE Computer Society Technical Committee on Design Automation IEEE Circuits and Systems Society In cooperation with IEEE Electron Devices Society IEEE Computer Society Press Los Alamitos, California Washington 0 Brussels 0 Tokyo Contents International Conference on Computer-Aided Design - ICCD’95 Welcome to ICCD’95 ............................................................................................................................................ xiv ICCD‘95 Conference Committee ......................................................................................................................... xv ICCD’95 Track Chairs and Committee Members ............................................................................................. xvi Hardware Support for Emerging Software Technologies L. Loucks Session 1.2.1 : VLSl & Technology Plenary Chair: Larry Pileggi, University of Texas at Austin Advances in Semiconductor Packaging and their Impact on System Design N.Naclerio Session 1.2.2: ArchitecturelAlgorithms Plenary Chair: Bing Sheu, University of Southern California, Los Angeles Statistical Generalization: Theory and Applications .......................................................................................... 4 B. Wah, A. leumwananonthachai,S. Yao, and T. Yu Session 1.3.2: System Level Interconnect Chair: Larry Pileggi, University Texas at Austin \ Signal Propagation In High-speed MCM Circuits............................................................................................ 12 C. Truzzi, E. Beyne, E. Ringoot, and I. Peeters Transient Analysis of Coupled Transmission Lines Characterized with the Frequency-Dependent Losses Using Scattering-Parameter Based Macromodel .......................................... 18 ‘ J.S.-H. Wang and W. W.-M. Dai A CMOS Gate Array with Dynamic-Termination GTL 1/0 Circuits ............................................................. 25 . J. Kudoh, T. Takahashi, Y. Umada,M. Kimura, S. Yamamoto,and Y. It0 Session 1.3.3: Asynchronous Systems Chair: Steve Nowick, Columbia University Precise Exception Handling for a Self-Timed Processor .................................................................................. 32 W.F. Richardson and E. Brunvand Implementing a STAN Chip ................................................................................................................................ 38 M.R. Greenstreet A High-PerformanceAsynchronous SCSI Controller ...................................................................................... 44 K.Y. Yun and D.L. Dill V Session 1.3.4: Embedded System Analysis Chair: Sharon Hu, Western Michigan University Performance Assessment of Embedded Hw/Sw Systems .............................................................................. 52 J.-P. Calvez and 0.Pasquier A Simulation Environment for Hardware-Software Codesign ....................................................................... 58 S.L. Coumeri and D.E. Thomas Performance Estimation for Real-Time Distributed Embedded Systems ...................................................... 64 T.-Y. Yen and W. Wolf Session 1.4.1: Formal Verification Meets the Real World Chair: Mirian Leeser, Cornel1 University and P.A. Subrahmayam, AT&T Bell Laboratories Verifying the Performance of the PCI Local Bus using Symbolic Techniques .............................................. 72 S. Campos, E.M. Clarke, W. Marrero, and M. Minea Formal Verification of a PowerPCm Microprocessor....................................................................................... 79 D.P. Appenzeller and A. Kuehlmann Extending VLSI Design with Higher-Order Logic ............................................................................................ 85 A. Chavan, S.-K. Chin, S. lkram, J. D. Kim, and 1.-Y. Lu Session 1.4.2: Issues in Superscalar Processors Chair: Bob Colwell, Intel Corp. Design and Implementation of a 100 MHz Centralized Instruction Window for a Superscalar Microprocessor ................................................................................................................................. 96 S. Wallace, N. Dagli, and N. Bagherzadeh A Superscalar RISC Processor with Pseudo Vector Processing Feature ...................................................... 102 K. Shimamura, S. Tanaka, T. Shimomura, T. Hotta, E. Kamada, H. Sawamoto, T. Shimizu, and K. Nakazawa The Resource Conflict Methodology for Early-Stage Design Space Exploration of Superscalar RISC Processors.............................................................................................................................. 110 J.-D. Wellman and E.S. Davidson Session I.4.3: SPARC Design Methodologies Chair: Chin-Long Wey, Michigan State University Design of an Efficient Power Distribution Network for the UltraSPARC-IrMMircoprocessor ....................................................................................................................... 118 A. Dalal, L. Lev, and S. Mitra Clock Controller Design in SuperSPARC IITMMicroprocessor ..................................................................... 124 H. Ha0 and K. Bhabufhmal Incas: A Cycle Accurate Model of UltraSPARCTM.......................................................................................... 130 G. Maturana, J.L. Ball, J. Gee, A. lyer, and J.M. O’Connor vi Session 1.4.4: Simulation Chair: Derek Beatty, Motorola Accurate Device Modeling Techniques for Efficient Timing Simulation of Integrated Circuits ............................................................................................................................................... 138 A. Devgan Execution-Time Profiling for Multiple-Process Behavioral Synthesis.......................................................... 144 J. K. Adams, J.A.Miller, and D.E. Thomas Emulation Verification of the Motorola 68060................................................................................................. 150 J. Kumar, N.Strader, J. Freeman, and M. Miller Session 2.1 .I: Embedded Systems Plenary Chair: Rolf Emst, University of Braunschweig Technical Challenges of PDA Design B. Mangione-Smith Session 2.2.1: Design for Testability Chair: Sumit Dasgupta, Sematech/IBM Corp. Testability Analysis and Insertion for RTL Circits Based on Pseudorandom BIST .................................... 162 J.E. Carletta and C.A. Papachristou Efficient Testability Enhancement for Combinational Circuit ....................................................................... 168 Y. Fang and A. Albicki Design for Hierarchical Testability of RTL Circuits Obtained by Behavioral Synthesis ............................ 173 1. Ghosh, A. Raghunathan, and N.K. ]ha Synthesis for Testability of Large Complexity Controllers. ........................................................................... 180 F. Fummi, D.Sciuto, and M. Serra Session 2.2.2: PowerPCTM Chairs: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola Multiprocessor Design Verification for the PowerPC 620TMMicroprocessor .............................................. 188 C. Montemayor, J.-T. Yen, M. Sullivan, P. Wilson, and R. Evers The PowerPC 603e’rMMicroprocessor: An Enhanced, Low-Power, Superscalar Microprocessor ............................................................................................................................... 196 J. Slaton, S.P. Licht, M. Alexander, K.R. Kishore, R. Jessani, and S. Reeve A High Performance Bus and Cache Controller for PowerPCTMMultiprocessing Systems.. ................... .204 M.S. Allen, W.K. Lewchuk, and J.D. Coddington Performance Monitoring on the PowerPCTM604 Microprocessor ................................................................ 212 F.E. Levine, C.P. Roth, and E.H. Welbon vii Session 2.2.3: Floor Planning & Placement Chair: Carl Sechen, University of Washington Thermal Placement for High-Performance Multichip Modules ................................................................... 218 K.-Y. Chao and D.F. Wong EPNR An Energy-Efficient Automated Layout Synthesis Package ............................................................. 224 G. Holt and A. Tyagi PEPPER - A Timing Driven Early Floorplanner ............................................................................................. 230 G. Vijayan, V.Narayananan, D. LaPotin, and R. Gupta Connection-Oriented Net Model and Fuzzy Clustering Techniques for K-Way Circuit Partitioning ................................................................................................................................ 236 1.-T. Yan Session 2.2.4: Combinational and Sequential Logic Optimization Chair: Masahiro Fujita, Fujitsu Labs of America An Enhanced Algorithm for the Minimization of Exclusive-OR Sum-of-Products for Incompletely Specified Functions ..................................................................................................................... 244 T. Kozlowski, E.L. Dagless, and J.M. Saul Implicit State Minimization of Non-Deterministic FSMs ............................................................................... 250 T. Kam, T. Villa, R.K. Brayton, and A.L. Sangiovanni-Vincentelli Extending Equivalence Class Computation to Large FSMs .......................................................................... 258 G. Cabodi, S. Quer, and P. Camurati Efficient State Assignment Framework for Asynchronous State Graphs ...................................................................................................
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