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SYS68K/CPU-60 Technical Reference Manual

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SYS68K/CPU-60 Technical Reference Manual SYS68K/CPU-60 Technical Reference Manual P/N 204077 Edition 2.3 June 1999 FORCE COMPUTERS Inc./GmbH All Rights Reserved This document shall not be duplicated, nor its contents used for any purpose, unless express permission has been granted. Copyright by FORCE COMPUTERS World Wide Web: www.forcecomputers.com 24-hour access to on-line manuals, driver updates, and application notes is provided via SMART, our SolutionsPLUS customer support program that provides current technical and services information. Headquarters The Americas Europe Asia FORCE COMPUTERS Inc. FORCE COMPUTERS GmbH FORCE COMPUTERS Japan KK 5799 Fontanoso Way Prof.-Messerschmitt-Str. 1 Miyakeya Building 4F San Jose, CA 95138-1015 D-85579 Neubiberg/München 1-9-12 Hamamatsucho U.S.A. Germany Minato-ku, Tokyo 105 Japan Tel.: +1 (408) 369-6000 Tel.: +49 (89) 608 14-0 Tel.: +81 (03) 3437 3948 Fax: +1 (408) 371-3382 Fax: +49 (89) 609 77 93 Fax: +81 (03) 3437 3968 Email [email protected] Email [email protected] Email [email protected] NOTE The information in this document has been carefully checked and is believed to be entirely reliable. FORCE COMPUTERS makes no warranty of any kind with regard to the material in this document, and assumes no responsibility for any errors which may appear in this document. FORCE COMPUTERS reserves the right to make changes without notice to this, or any of its products, to improve reliability, performance, or design. FORCE COMPUTERS assumes no responsibility for the use of any circuitry other than circuitry which is part of a product of FORCE COMPUTERS Inc./GmbH. FORCE COMPUTERS does not convey to the purchaser of the product described herein any license under the patent rights of FORCE COMPUTERS Inc./GmbH nor the rights of others. All product names as mentioned herein are the trademarks or registered trademarks of their respective companies. Contents Table of Contents UsingThisManual .......................................................... ix 1 Introduction.................................................................1 1.1 Specification............................................................2 1.2 OrderingInformation....................................................6 2 Installation..................................................................7 2.1 SafetyNote.............................................................7 2.2 InstallationPrerequisitesandRequirements.................................8 2.2.1 Requirements....................................................8 2.2.2 TerminalConnection..............................................9 2.2.3 Functional and Location Overview ...................................9 2.3 Automatic Power Up – Voltage Sensor and Watchdog Timer ..................11 2.4 SwitchSettings.........................................................11 2.5 FrontPanel............................................................15 2.6 SYS68K/CPU-60 Parameters and 16-bit Timers – CIO . ....................17 2.7 SerialI/OPorts–SCC...................................................17 2.8 SCSI..................................................................21 2.9 FloppyDisk–FDC.....................................................23 2.10 Ethernet–LAN........................................................23 2.11 VMEbusP2ConnectorPinout............................................24 2.12 SYS68K/IOBP-1........................................................28 2.13 TestingtheCPUBoardUsingVMEPROM.................................30 3 Hardware..................................................................33 3.1 SYS68K/CPU-60 Memory Map ...........................................36 3.2 SYS68K/CPU-60 Interrupt Map ..........................................38 SYS68K/CPU-60 Page i Contents 3.3 SYS68K/CPU-60 Parameters and Timers – CIO Z8536 . ....................40 3.3.1 MEM-60DRAMCapacityandCIO1Timer3 .........................41 3.3.2 Flash VPP, Floppy Disk Control, and CIO1 Timer 2 . ....................42 3.3.3 MODE x Rotary Switch Setting .....................................43 3.3.4 On-board DRAM Capacity and Automatic A24 Expansion ...............44 3.3.5 Board ID and DIAG Display . ......................................44 3.3.6 A24-to-A32 Address Translation ....................................45 3.4 68060CPU............................................................45 3.4.1 Hardware Interface of the 68060 CPU . .............................45 3.4.2 Instruction Set of the 68060 CPU....................................46 3.4.3 VectorTableofthe68060CPU.....................................46 3.5 WatchdogTimer.......................................................48 3.5.1 Watchdog Operation..............................................48 3.5.2 Watchdog Register Map...........................................49 3.6 RIALTO Bus Bridge ....................................................50 3.6.1 RegisterSet.....................................................50 3.6.2 Bridge Configuration Register ......................................50 3.7 FGA-002GateArray....................................................51 3.8 DRAM ................................................................52 3.8.1 RegisterSet.....................................................53 3.8.2 Memory Configuration Register ....................................54 3.8.3 Memory Diagnostic Register . ......................................55 3.8.4 DRAMPerformance..............................................56 3.8.5 Reading the DRAM Capacity. ......................................57 3.8.6 DRAMOrganization.............................................57 3.8.7 Cache Coherence and Snooping.....................................58 3.8.8 DRAMAccessfromthe68060CPU.................................59 3.8.9 DRAM Access via the VMEbus ....................................60 3.8.10 DRAM Access from the Ethernet-Controller...........................61 3.8.11 DRAM Access from the SCSI-Controller .............................61 3.9 UserSRAM(factoryoption)..............................................61 3.9.1 BackupPowerfortheUserSRAM..................................62 204077 June 1999 Page ii SYS68K/CPU-60 Contents 3.10 SystemPROM.........................................................62 3.10.1 Device Types for the System PROM .................................63 3.10.2 Address Map of the System PROM ..................................63 3.10.3 Reading and Programming the System PROM .........................64 3.11 BootPROM...........................................................64 3.11.1 Boot PROM Address Map and Factory Options ........................66 3.11.2 ProgrammingtheBootPROM......................................67 3.12 UserFlash.............................................................68 3.12.1 ProgrammingtheUserFlash.......................................68 3.13 LocalSRAM...........................................................69 3.13.1 LocalSRAMOrganization.........................................69 3.13.2 Devices Types for the Local SRAM .................................70 3.13.3 BackupPowerfortheLocalSRAM..................................71 3.14 Real-Time Clock – RTC 72423 ............................................71 3.14.1 RTC Registers Address Map . ......................................72 3.14.2 Reading from or Writing to the RTC 72423 ...........................73 3.14.3 Backup Power for the RTC 72423 ...................................74 3.15 VMEbusInterface......................................................75 3.15.1 Exception Signals SYSFAIL, SYSRESET, and ACFAIL.................76 3.15.2 Master Interface: Address Modifier (AM) Codes . ....................77 3.15.3 MasterInterface:DataTransferSize.................................78 3.15.4 Master Interface: Burst to VMEbus ..................................80 3.15.5 Slave Interface: Access Address....................................81 3.15.6 Slave Interface: DRAM Data Transfer Size............................81 3.15.7 Slave Interface: Address Modifier Decoding and A24 Slave Mode .........81 3.15.8 Slave Interface: Locked Cycles .....................................82 3.16 VMEbusArbitration....................................................83 3.16.1 Single-Level VMEbus Arbiter ......................................83 3.16.2 VMEbusRequester...............................................83 3.16.3 VMEbusReleaseModes..........................................84 3.16.4 VMEbusGrantDriver............................................86 3.17 VMEbusSlot-1.........................................................86 SYS68K/CPU-60 Page iii Contents 3.17.1 Slot-1 (System Controller) Functions.................................87 3.17.2 Slot-1 Detection . ...............................................87 3.17.3 Slot-1 Status Register .............................................88 3.17.4 TheSYSCLKDriver.............................................88 3.17.5 VMEbusTimer..................................................89 3.18 Serial I/O – SCC AM 85C30 ..............................................89 3.18.1 RS-485Configuration............................................90 3.19 SCSI – 53C720SE.......................................................92 3.19.1 SCSIRegisterMap...............................................93 3.19.2 CommunicationacrosstheSCSIbus.................................93 3.20 Floppy Disk – FDC 37C65C ..............................................94 3.21 Ethernet – LAN AM 79C965A ............................................96 3.21.1 RegisterAccess.................................................98
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