The ITRS Design Technology and System Drivers Roadmap: Process and Status
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The ITRS Design Technology and System Drivers Roadmap: Process and Status Andrew B. Kahng CSE and ECE Depts., Univ. of California at San Diego [email protected] ABSTRACT progress of design technology. The Design technology working group (TWG) is one of 16 working • Understanding of contexts and needs for technology. Con- groups in the International Technology Roadmap for Semiconduc- texts ranging from process technology to market forces affect tors (ITRS) effort. It is responsible for the ITRS’ Design Chap- the need for technology. For example, the trajectory of mo- ter, which roadmaps design technology requirements and poten- bile consumer SOC products has driven rapid innovation in tial solutions for elements of the semiconductor supply chain that low-power design techniques spanning embedded memory are produced by the electronic design automation (EDA) indus- design, power and clock gating, dynamic voltage scaling, try. The Design TWG is also responsible for the ITRS’ System etc. At the same time, these low-power design techniques Drivers Chapter, which roadmaps the key product classes that drive must acknowledge process and material attributes such as the leading-edge requirements for process and design technolo- discreteness of FinFET device widths starting at the 16nm gies. Through these activities, the Design TWG sets a number foundry node, or increasingly dominant reliability and aging of fundamental parameters in the overall ITRS: layout density, die mechanisms. size, maximum on-chip clock frequency, total chip power, SOC and • Holistic selection of potential solutions. Technology roadmap- MPU architecture models, etc. This paper reviews the process by ping must holistically model and predict impacts of potential which the Design TWG evolves its roadmap content, and some of technology solutions, at many levels. For example, solutions the key modeling and roadmapping questions that the semiconduc- to a “power crisis” in IC design may come from manufac- tor and EDA industries will face in the near term. turing technologists (e.g., process innovation to reduce Vth variation), device and circuit technologists (introduction of 1. INTRODUCTION FinFET and resistive RAM), and system designers (hetero- As noted in [13], technology roadmaps seek “precompetitive” geneous multi-core SOC architectures) – as well as design specifications of future technical requirements and challenges. Po- and test technologists (asynchronous design flow, on-chip tential solutions are identified, investigated, pruned, productized, variability monitoring and adaptivity, etc.). All potential so- standardized, and delivered to the marketplace – in a synchronized, lutions cost money to develop and deploy. Thus, as discussed timely, and cost-effective manner – to ensure a continued stream in [11], a mindset of “shared red bricks” in the semiconductor of technology benefits. The International Technology Roadmap for technology roadmap is critical to achieve proper allocation of 1 Semiconductors (ITRS) [22] is one of the most successful roadmap- R&D resources. ping efforts ever: well over 1000 scientists and engineers world- wide collaborate to synchronize a wide range of industries and The ITRS Design Technology Working Group. The Design technologies (automated test equipment, assembly and packaging, technology working group (TWG) is one of 16 TWGs in the ITRS. photomask, electronic design automation (EDA), lithography, in- With over 50 industry and academic contributors from all five re- terconnect, device, etc.) so that the “Moore’s Law” semiconductor gional semiconductor industry associations (USA, EU, Japan, Tai- value proposition can continue. The broad scope of the ITRS is wan, Korea), the Design TWG is responsible for the ITRS Design essential, e.g., the roadmap for design technology must compre- Chapter, which roadmaps design technology requirements and po- hend (i) lithography and restricted design rules; (ii) die stacking and tential solutions relevant to the EDA industry, and the ITRS System 3D integration; (iii) device and interconnect electrical performance, Drivers Chapter, which roadmaps the key product classes that drive variability and robustness; (iv) ATE, BIST and BISR overheads and leading-edge requirements for process and design technologies. production costs; (v) product-level trajectories for RF blocks, IO Figure 1 shows how the Design and System Drivers chapters bandwidth and processing capability; and many other futures. The have consistently evolved over the past decade. First, the Design ITRS’s 15-year horizon reflects the lead times needed to identify Chapter gives a quantified Design Technology roadmap with met- and develop production-worthy technologies. rics, potential solutions, and mappings from requirements to po- All technology roadmaps struggle with the tension between “road- tential solutions. This matches the structure and metrics-oriented mapping” and “extrapolation”. An uncalibrated roadmap lacks cred- “look and feel” of other ITRS chapters. Second, an increasingly ibility. On the other hand, unthinking extrapolation from historical comprehensive set of System Drivers has been developed that main- data risks “driving by the rear-view mirror”, and can result in ab- tain alignment to key segments of the semiconductor industry. Each surd projections at the 15-year horizon. Meaningful roadmapping update to the System Drivers (e.g., the acknowledgment of a hard of technology requirements and potential solutions requires at least platform power limit in the MPU roadmap, starting in 2007) has the following elements. ripple effects across Overall Roadmap Technology Characteristics (ORTCs) such as layout density, transistor count, die size, chip • Metrics. What cannot be measured cannot be tracked or power and frequency – as well as fundamental technology metrics improved. EDA tools heuristically address large-scale, NP- owned by other technology working groups. These interactions are hard optimizations, and design quality is strongly determined 2 by flow and methodology (“it’s the magician, not the wand”). conceptually depicted in Figure 2. The System Drivers also enable Thus, it is challenging to identify metrics that capture the 1In ITRS parlance, a “red brick” is a technology requirement that has no known solution (the term stems from the coloring convention in ITRS technology requirement tables). For example, to solve the problem of poor interconnect RC scaling, are Permission to make digital or hard copies of all or part of this work for R&D dollars best invested in new dielectric materials, new interconnect and barrier personal or classroom use is granted without fee provided that copies are materials, better overlay control, more accurate signal integrity analyses in EDA tools, scalable many-core GALS architectures, or ...? Or, to solve the problem of exploding not made or distributed for profit or commercial advantage and that copies (and widening) modes and corners in signoff, should variation be reduced in the bear this notice and the full citation on the first page. To copy otherwise, to process itself, or should statistical signoffs be adopted, or should “signoff at typical” republish, to post on servers or to redistribute to lists, requires prior specific be adopted in combination with adaptivity [3], or ...? permission and/or a fee. 2In over 17 years of NTRS and ITRS roadmap participation, I have witnessed a steady DAC’13, May 29 - June 07 2013, Austin, TX, USA. rise in the prominence of “design” within the ITRS. Originally highly process-centric, Copyright 2013 ACM 978-1-4503-2071-9/13/05 ...$15.00. the roadmap now increasingly relies on “design-based equivalent scaling” [24] and 2011 More Than 2010 Moore 1. Increasingly Quantitative Roadmap Roadmap 20092009 More Than 2. Increasingly Complete Driver Set Moore RF RF + Analog and 20082008 More Than + Analog 3. Increasing More Than Moore Content Moore and Mixed Mixed Signal Extension Signal Driver More Than +iNEMI Driver Start Continued Moore synch 20072007 Extension + Software Updated +iNEMI Drivers + Software (MPU, SOC, More Than ˎ) Moore Updated Updated Analysis Consumer Consumer +iNEMI Stationary, 20062006 Updated Portable SOC and Consumer Architecture MPU Stationary, Drivers Upgraded Consumer ,and Portable DFM, 20052005 Stationary, Networking Consumer and System- Portable, Drivers Stationary, Networking Level, Networking Consumer Portable Drivers Verification 20042004 Drivers Additional Portable Drivers Design Upgraded Sections Driver RF + Driver Revised Metrics System Driversrs Revised Analog and Study Design DFM Chapter Design Revised Design Extension Mixed Power Technology Metrics Explore Technology Design System- Signal Design Design Metric DFM Design Metrics Metrics Level Section Technology Chapter Extension Metrics Extension Roadmap Figure 1: Roadmap from ITRS System Drivers and Design chapters. [Source: ITRS Design ITWG 2011 Public Conference presentation, December 2011, Songdo, Korea.] jointly owned with the Test TWG. The roadmap for off-chip IO bandwidth is jointly owned with the Test TWG and the Assembly and Packaging (A&P) TWG. And the roadmap for 3D/TSV based integration is jointly owned with a number of other TWGs, no- tably A&P, Test, Interconnect and Front-End Processing (FEP). All of these interactions entail asynchronous, off-line dialogues year- round with designers, EDA technologists and researchers so that perspectives from IC design, and from IC design automation, are correctly represented. ITRS challenges and technology requirements directly